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Ian Campbellcba69ee2014-05-05 11:52:26 +01001/*
2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3 *
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
7 *
8 * Some init for sunxi platform.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
Hans de Goede66203772014-06-13 22:55:49 +020014#include <i2c.h>
Ian Campbell58358232014-05-05 11:52:28 +010015#include <netdev.h>
16#include <miiphy.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010017#include <serial.h>
18#ifdef CONFIG_SPL_BUILD
19#include <spl.h>
20#endif
21#include <asm/gpio.h>
22#include <asm/io.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/sys_proto.h>
26#include <asm/arch/timer.h>
27
Ian Campbell799aff32014-07-06 20:03:20 +010028#include <linux/compiler.h>
29
Ian Campbellcba69ee2014-05-05 11:52:26 +010030#ifdef CONFIG_SPL_BUILD
31/* Pointer to the global data structure for SPL */
32DECLARE_GLOBAL_DATA_PTR;
33
34/* The sunxi internal brom will try to loader external bootloader
35 * from mmc0, nand flash, mmc2.
36 * Unfortunately we can't check how SPL was loaded so assume
37 * it's always the first SD/MMC controller
38 */
39u32 spl_boot_device(void)
40{
41 return BOOT_DEVICE_MMC1;
42}
43
44/* No confirmation data available in SPL yet. Hardcode bootmode */
45u32 spl_boot_mode(void)
46{
47 return MMCSD_MODE_RAW;
48}
49#endif
50
51int gpio_init(void)
52{
Hans de Goedef84269c2014-06-09 11:36:58 +020053#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
Ian Campbellcba69ee2014-05-05 11:52:26 +010054 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
55 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080056 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
Hans de Goedef84269c2014-06-09 11:36:58 +020057#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
58 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
59 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080060 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
Maxime Ripard77115392014-10-03 20:16:28 +080061#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
62 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
63 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
64 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
Hans de Goedef84269c2014-06-09 11:36:58 +020065#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
66 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
67 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080068 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
Hans de Goedef84269c2014-06-09 11:36:58 +020069#else
70#error Unsupported console port number. Please fix pin mux settings in board.c
71#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +010072
73 return 0;
74}
75
76void reset_cpu(ulong addr)
77{
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +080078#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
Hans de Goedec7e79de2014-06-09 11:36:56 +020079 static const struct sunxi_wdog *wdog =
80 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
81
82 /* Set the watchdog for its shortest interval (.5s) and wait */
83 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
84 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedeae5de5a2014-06-13 22:55:52 +020085
86 while (1) {
87 /* sun5i sometimes gets stuck without this */
88 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
89 }
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +080090#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */
91 static const struct sunxi_wdog *wdog =
92 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
93
94 /* Set the watchdog for its shortest interval (.5s) and wait */
95 writel(WDT_CFG_RESET, &wdog->cfg);
96 writel(WDT_MODE_EN, &wdog->mode);
97 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
98#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +010099}
100
101/* do some early init */
102void s_init(void)
103{
104#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
105 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
106 asm volatile(
107 "mrc p15, 0, r0, c1, c0, 1\n"
108 "orr r0, r0, #1 << 6\n"
109 "mcr p15, 0, r0, c1, c0, 1\n");
110#endif
111
112 clock_init();
113 timer_init();
114 gpio_init();
Hans de Goede66203772014-06-13 22:55:49 +0200115 i2c_init_board();
Ian Campbellcba69ee2014-05-05 11:52:26 +0100116
117#ifdef CONFIG_SPL_BUILD
118 gd = &gdata;
119 preloader_console_init();
120
Hans de Goede66203772014-06-13 22:55:49 +0200121#ifdef CONFIG_SPL_I2C_SUPPORT
122 /* Needed early by sunxi_board_init if PMU is enabled */
123 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
124#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100125 sunxi_board_init();
126#endif
127}
128
129#ifndef CONFIG_SYS_DCACHE_OFF
130void enable_caches(void)
131{
132 /* Enable D-cache. I-cache is already enabled in start.S */
133 dcache_enable();
134}
135#endif
Ian Campbell58358232014-05-05 11:52:28 +0100136
137#ifdef CONFIG_CMD_NET
138/*
139 * Initializes on-chip ethernet controllers.
140 * to override, implement board_eth_init()
141 */
142int cpu_eth_init(bd_t *bis)
143{
Ian Campbell799aff32014-07-06 20:03:20 +0100144 __maybe_unused int rc;
Ian Campbell58358232014-05-05 11:52:28 +0100145
Hans de Goedefc703002014-07-26 17:09:13 +0200146#ifdef CONFIG_MACPWR
147 gpio_direction_output(CONFIG_MACPWR, 1);
148 mdelay(200);
149#endif
150
Hans de Goedec26fb9d2014-06-09 11:37:00 +0200151#ifdef CONFIG_SUNXI_EMAC
152 rc = sunxi_emac_initialize(bis);
153 if (rc < 0) {
154 printf("sunxi: failed to initialize emac\n");
155 return rc;
156 }
157#endif
158
Ian Campbell58358232014-05-05 11:52:28 +0100159#ifdef CONFIG_SUNXI_GMAC
160 rc = sunxi_gmac_initialize(bis);
161 if (rc < 0) {
162 printf("sunxi: failed to initialize gmac\n");
163 return rc;
164 }
165#endif
166
167 return 0;
168}
169#endif