Blame - arch/powerpc/include/asm/config_mpc85xx.h - github/trini/u-boot

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Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	1	/*
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	3	*
Wolfgang Denk	1a45966	2013-07-08 09:37:19 +0200	[diff] [blame]	4	* SPDX-License-Identifier: GPL-2.0+
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	5	*/
				6
				7	#ifndef _ASM_MPC85xx_CONFIG_H_
				8	#define _ASM_MPC85xx_CONFIG_H_
				9
				10	/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
				11
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	12	#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
				13	#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
				14	#endif
				15
York Sun	2a5fcb8	2012-10-28 08:12:54 +0000	[diff] [blame]	16	/*
				17	* This macro should be removed when we no longer care about backwards
				18	* compatibility with older operating systems.
				19	*/
				20	#define CONFIG_PPC_SPINTABLE_COMPATIBLE
				21
York Sun	57495e4	2012-10-08 07:44:22 +0000	[diff] [blame]	22	#define FSL_DDR_VER_4_7 47
				23
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	24	/* Number of TLB CAM entries we have on FSL Book-E chips */
				25	#if defined(CONFIG_E500MC)
				26	#define CONFIG_SYS_NUM_TLBCAMS 64
				27	#elif defined(CONFIG_E500)
				28	#define CONFIG_SYS_NUM_TLBCAMS 16
				29	#endif
				30
				31	#if defined(CONFIG_MPC8536)
				32	#define CONFIG_MAX_CPUS 1
				33	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	34	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	35	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	36	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	37
Wolfgang Denk	d1a24f0	2011-02-02 22:36:10 +0100	[diff] [blame]	38	#elif defined(CONFIG_MPC8540)
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	39	#define CONFIG_MAX_CPUS 1
				40	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	41	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	42
Wolfgang Denk	d1a24f0	2011-02-02 22:36:10 +0100	[diff] [blame]	43	#elif defined(CONFIG_MPC8541)
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	44	#define CONFIG_MAX_CPUS 1
				45	#define CONFIG_SYS_FSL_NUM_LAWS 8
				46	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	47	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	48
				49	#elif defined(CONFIG_MPC8544)
				50	#define CONFIG_MAX_CPUS 1
				51	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	52	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	53	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	54	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	55
				56	#elif defined(CONFIG_MPC8548)
				57	#define CONFIG_MAX_CPUS 1
				58	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	59	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	60	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	61	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	5ace299	2011-09-16 09:54:30 -0500	[diff] [blame]	62	#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala	2b3a1cd	2011-10-03 08:37:57 -0500	[diff] [blame]	63	#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhao	aada81d	2011-10-03 08:38:50 -0500	[diff] [blame]	64	#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	65	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				66	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				67	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				68	#define CONFIG_SYS_FSL_RMU
				69	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	70
				71	#elif defined(CONFIG_MPC8555)
				72	#define CONFIG_MAX_CPUS 1
				73	#define CONFIG_SYS_FSL_NUM_LAWS 8
				74	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	75	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	76
				77	#elif defined(CONFIG_MPC8560)
				78	#define CONFIG_MAX_CPUS 1
				79	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	80	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	81
				82	#elif defined(CONFIG_MPC8568)
				83	#define CONFIG_MAX_CPUS 1
				84	#define CONFIG_SYS_FSL_NUM_LAWS 10
				85	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	fdb4dad	2011-01-31 23:09:25 -0600	[diff] [blame]	86	#define QE_MURAM_SIZE 0x10000UL
				87	#define MAX_QE_RISC 2
				88	#define QE_NUM_OF_SNUM 28
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	89	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	90	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				91	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				92	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				93	#define CONFIG_SYS_FSL_RMU
				94	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	95
				96	#elif defined(CONFIG_MPC8569)
				97	#define CONFIG_MAX_CPUS 1
				98	#define CONFIG_SYS_FSL_NUM_LAWS 10
				99	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	fdb4dad	2011-01-31 23:09:25 -0600	[diff] [blame]	100	#define QE_MURAM_SIZE 0x20000UL
				101	#define MAX_QE_RISC 4
				102	#define QE_NUM_OF_SNUM 46
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	103	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	104	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				105	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				106	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				107	#define CONFIG_SYS_FSL_RMU
				108	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	109
				110	#elif defined(CONFIG_MPC8572)
				111	#define CONFIG_MAX_CPUS 2
				112	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	113	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	114	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	115	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	eb0aff7	2011-01-25 21:51:27 -0800	[diff] [blame]	116	#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun	9167191	2011-01-25 22:05:49 -0800	[diff] [blame]	117	#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	118
				119	#elif defined(CONFIG_P1010)
				120	#define CONFIG_MAX_CPUS 1
Priyanka Jain	32c8cfb	2011-02-09 09:24:10 +0530	[diff] [blame]	121	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	122	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	123	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	124	#define CONFIG_TSECV2
				125	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	126	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				127	#define CONFIG_NUM_DDR_CONTROLLERS 1
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	128	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	129	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	130	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh	1b719e6	2011-03-23 15:20:43 +0530	[diff] [blame]	131	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	42aee64	2011-06-30 03:00:28 -0500	[diff] [blame]	132	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	fb855f4	2011-06-29 16:32:52 +0530	[diff] [blame]	133	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal	bc6bbd6	2011-07-07 20:36:47 +0530	[diff] [blame]	134	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	135
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	136	/* P1011 is single core version of P1020 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	137	#elif defined(CONFIG_P1011)
				138	#define CONFIG_MAX_CPUS 1
				139	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	140	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	141	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	142	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	143	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	144	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	145	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				146	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	147
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	148	/* P1012 is single core version of P1021 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	149	#elif defined(CONFIG_P1012)
				150	#define CONFIG_MAX_CPUS 1
				151	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	152	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	153	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	154	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	155	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	156	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	157	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				158	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	159	#define QE_MURAM_SIZE 0x6000UL
				160	#define MAX_QE_RISC 1
				161	#define QE_NUM_OF_SNUM 28
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	162
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	163	/* P1013 is single core version of P1022 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	164	#elif defined(CONFIG_P1013)
				165	#define CONFIG_MAX_CPUS 1
				166	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	167	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	168	#define CONFIG_TSECV2
				169	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	170	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	2d7534a	2011-01-30 17:06:20 -0600	[diff] [blame]	171	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				172	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				173	#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	174
				175	#elif defined(CONFIG_P1014)
				176	#define CONFIG_MAX_CPUS 1
Priyanka Jain	32c8cfb	2011-02-09 09:24:10 +0530	[diff] [blame]	177	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	178	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	179	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	180	#define CONFIG_TSECV2
				181	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	182	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				183	#define CONFIG_NUM_DDR_CONTROLLERS 1
				184	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh	1b719e6	2011-03-23 15:20:43 +0530	[diff] [blame]	185	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	42aee64	2011-06-30 03:00:28 -0500	[diff] [blame]	186	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	fb855f4	2011-06-29 16:32:52 +0530	[diff] [blame]	187	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal	bc6bbd6	2011-07-07 20:36:47 +0530	[diff] [blame]	188	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	189
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	190	/* P1017 is single core version of P1023 */
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	191	#elif defined(CONFIG_P1017)
				192	#define CONFIG_MAX_CPUS 1
				193	#define CONFIG_SYS_FSL_NUM_LAWS 12
				194	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				195	#define CONFIG_SYS_NUM_FMAN 1
				196	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				197	#define CONFIG_NUM_DDR_CONTROLLERS 1
				198	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				199	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	200	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	201	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	202	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	203
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	204	#elif defined(CONFIG_P1020)
				205	#define CONFIG_MAX_CPUS 2
				206	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	207	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	208	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	209	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	210	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	211	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	212	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				213	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	214
				215	#elif defined(CONFIG_P1021)
				216	#define CONFIG_MAX_CPUS 2
				217	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	218	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	219	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	220	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	221	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	222	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	223	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				224	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	225	#define QE_MURAM_SIZE 0x6000UL
				226	#define MAX_QE_RISC 1
				227	#define QE_NUM_OF_SNUM 28
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	228
				229	#elif defined(CONFIG_P1022)
				230	#define CONFIG_MAX_CPUS 2
				231	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	232	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	233	#define CONFIG_TSECV2
				234	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	235	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	2d7534a	2011-01-30 17:06:20 -0600	[diff] [blame]	236	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				237	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				238	#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	239
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	240	#elif defined(CONFIG_P1023)
				241	#define CONFIG_MAX_CPUS 2
				242	#define CONFIG_SYS_FSL_NUM_LAWS 12
				243	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				244	#define CONFIG_SYS_NUM_FMAN 1
				245	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				246	#define CONFIG_NUM_DDR_CONTROLLERS 1
				247	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				248	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	249	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	250	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	251	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	252
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	253	/* P1024 is lower end variant of P1020 */
				254	#elif defined(CONFIG_P1024)
				255	#define CONFIG_MAX_CPUS 2
				256	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	257	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	258	#define CONFIG_TSECV2
				259	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				260	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	261	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	262	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				263	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				264
				265	/* P1025 is lower end variant of P1021 */
				266	#elif defined(CONFIG_P1025)
				267	#define CONFIG_MAX_CPUS 2
				268	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	269	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	270	#define CONFIG_TSECV2
				271	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				272	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	273	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	274	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				275	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	276	#define QE_MURAM_SIZE 0x6000UL
				277	#define MAX_QE_RISC 1
				278	#define QE_NUM_OF_SNUM 28
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	279
				280	/* P2010 is single core version of P2020 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	281	#elif defined(CONFIG_P2010)
				282	#define CONFIG_MAX_CPUS 1
				283	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	284	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	285	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	286	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	6e7f0bc0	2011-01-26 01:43:15 -0600	[diff] [blame]	287	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	5103a03	2011-01-29 15:36:10 -0600	[diff] [blame]	288	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	289
				290	#elif defined(CONFIG_P2020)
				291	#define CONFIG_MAX_CPUS 2
				292	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	293	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	294	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	295	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	6e7f0bc0	2011-01-26 01:43:15 -0600	[diff] [blame]	296	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	5103a03	2011-01-29 15:36:10 -0600	[diff] [blame]	297	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	298	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				299	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				300	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				301	#define CONFIG_SYS_FSL_RMU
				302	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	303
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	304	#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	305	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	306	#define CONFIG_MAX_CPUS 4
				307	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
				308	#define CONFIG_SYS_FSL_NUM_LAWS 32
				309	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				310	#define CONFIG_SYS_NUM_FMAN 1
				311	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				312	#define CONFIG_SYS_NUM_FM1_10GEC 1
				313	#define CONFIG_NUM_DDR_CONTROLLERS 1
				314	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				315	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				316	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	317	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	318	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				319	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	320	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	321	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	5e23ab0	2012-05-07 07:26:47 +0000	[diff] [blame]	322	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	323	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	324	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	325	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	326	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	327	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				328	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				329	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	330	#define CONFIG_SYS_FSL_ERRATUM_A004510
				331	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				332	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				333	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	334	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	335	#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	336
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	337	#elif defined(CONFIG_PPC_P3041)
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	338	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	339	#define CONFIG_MAX_CPUS 4
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	340	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	341	#define CONFIG_SYS_FSL_NUM_LAWS 32
				342	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	fbee0f7	2011-01-25 12:42:32 -0600	[diff] [blame]	343	#define CONFIG_SYS_NUM_FMAN 1
				344	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				345	#define CONFIG_SYS_NUM_FM1_10GEC 1
				346	#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	347	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	348	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	349	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	350	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	86221f0	2011-04-13 00:08:51 -0500	[diff] [blame]	351	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				352	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	353	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3000976	2011-04-19 15:28:41 +0800	[diff] [blame]	354	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	57125f2	2012-08-08 18:04:53 +0000	[diff] [blame]	355	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	356	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	357	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	358	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	359	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	360	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				361	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				362	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	363	#define CONFIG_SYS_FSL_ERRATUM_A004510
				364	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				365	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				366	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	367	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	368	#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	369
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	370	#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	371	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	372	#define CONFIG_MAX_CPUS 8
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	373	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	374	#define CONFIG_SYS_FSL_NUM_LAWS 32
				375	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				376	#define CONFIG_SYS_NUM_FMAN 2
				377	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				378	#define CONFIG_SYS_NUM_FM2_DTSEC 4
				379	#define CONFIG_SYS_NUM_FM1_10GEC 1
				380	#define CONFIG_SYS_NUM_FM2_10GEC 1
				381	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	382	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	383	#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	384	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	385	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	386	#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
				387	#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun	fa8d23c	2011-01-10 12:03:01 +0000	[diff] [blame]	388	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	389	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				390	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				391	#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R61911	4e0be34	2012-09-18 09:50:08 +0000	[diff] [blame]	392	#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	393	#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun	5e23ab0	2012-05-07 07:26:47 +0000	[diff] [blame]	394	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	395	#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medve	df8af0b	2010-08-31 22:57:38 -0500	[diff] [blame]	396	#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi	d90fdba	2011-04-18 17:16:00 -0500	[diff] [blame]	397	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi	da30b9f	2011-04-01 13:19:36 -0500	[diff] [blame]	398	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	399	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	400	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	401	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				402	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				403	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				404	#define CONFIG_SYS_FSL_RMU
				405	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	406	#define CONFIG_SYS_FSL_ERRATUM_A004510
				407	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
				408	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	409	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	410	#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabi	d607b96	2012-11-01 08:20:23 +0000	[diff] [blame]	411	#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chen	c0a4e6b	2012-11-26 23:49:45 +0000	[diff] [blame]	412	#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	413
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	414	#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun	ffd06e0	2012-10-08 07:44:30 +0000	[diff] [blame]	415	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	416	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	417	#define CONFIG_MAX_CPUS 2
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	418	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	419	#define CONFIG_SYS_FSL_NUM_LAWS 32
				420	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	fbee0f7	2011-01-25 12:42:32 -0600	[diff] [blame]	421	#define CONFIG_SYS_NUM_FMAN 1
				422	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				423	#define CONFIG_SYS_NUM_FM1_10GEC 1
				424	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	425	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	426	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	427	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	428	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	86221f0	2011-04-13 00:08:51 -0500	[diff] [blame]	429	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				430	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	431	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3000976	2011-04-19 15:28:41 +0800	[diff] [blame]	432	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	433	#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	434	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	435	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	436	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				437	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				438	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	439	#define CONFIG_SYS_FSL_ERRATUM_A004510
				440	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				441	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	442	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	443
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	444	#elif defined(CONFIG_PPC_P5040)
Timur Tabi	1956e43	2012-10-23 10:48:09 +0000	[diff] [blame]	445	#define CONFIG_SYS_PPC64
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	446	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
				447	#define CONFIG_MAX_CPUS 4
				448	#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
				449	#define CONFIG_SYS_FSL_NUM_LAWS 32
				450	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				451	#define CONFIG_SYS_NUM_FMAN 2
				452	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				453	#define CONFIG_SYS_NUM_FM1_10GEC 1
				454	#define CONFIG_SYS_NUM_FM2_DTSEC 5
				455	#define CONFIG_SYS_NUM_FM2_10GEC 1
				456	#define CONFIG_NUM_DDR_CONTROLLERS 2
				457	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				458	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				459	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				460	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				461	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				462	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				463	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				464	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	465	#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	466	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
				467	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
				468	#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	469	#define CONFIG_SYS_FSL_ERRATUM_A004510
				470	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				471	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
				472
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	473	#elif defined(CONFIG_BSC9131)
				474	#define CONFIG_MAX_CPUS 1
				475	#define CONFIG_FSL_SDHC_V2_3
				476	#define CONFIG_SYS_FSL_NUM_LAWS 12
				477	#define CONFIG_TSECV2
				478	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				479	#define CONFIG_NUM_DDR_CONTROLLERS 1
Priyanka Jain	765b0bd	2013-04-04 09:31:54 +0530	[diff] [blame]	480	#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
				481	#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	482	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	483	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				484	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	485	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				486
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	487	#elif defined(CONFIG_BSC9132)
				488	#define CONFIG_MAX_CPUS 2
				489	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				490	#define CONFIG_FSL_SDHC_V2_3
				491	#define CONFIG_SYS_FSL_NUM_LAWS 12
				492	#define CONFIG_TSECV2
				493	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				494	#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun	061ffed	2013-04-18 19:31:01 -0700	[diff] [blame]	495	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	496	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				497	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	498	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				499	#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
				500	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
				501
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	502	#elif defined(CONFIG_PPC_T4240) \|\| defined(CONFIG_PPC_T4160)
				503	#define CONFIG_E6500
York Sun	ffd06e0	2012-10-08 07:44:30 +0000	[diff] [blame]	504	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	505	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				506	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	507	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	508	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	509	#ifdef CONFIG_PPC_T4240
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	510	#define CONFIG_MAX_CPUS 12
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	511	#define CONFIG_SYS_NUM_FM1_DTSEC 8
				512	#define CONFIG_SYS_NUM_FM1_10GEC 2
				513	#define CONFIG_SYS_NUM_FM2_DTSEC 8
				514	#define CONFIG_SYS_NUM_FM2_10GEC 2
				515	#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	516	#else
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	517	#define CONFIG_MAX_CPUS 8
York Sun	3d2972f	2013-03-25 07:40:05 +0000	[diff] [blame]	518	#define CONFIG_SYS_NUM_FM1_DTSEC 7
				519	#define CONFIG_SYS_NUM_FM1_10GEC 1
				520	#define CONFIG_SYS_NUM_FM2_DTSEC 7
				521	#define CONFIG_SYS_NUM_FM2_10GEC 1
				522	#define CONFIG_NUM_DDR_CONTROLLERS 2
				523	#endif
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	524	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				525	#define CONFIG_SYS_FSL_NUM_LAWS 32
				526	#define CONFIG_SYS_FSL_SRDS_3
				527	#define CONFIG_SYS_FSL_SRDS_4
				528	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				529	#define CONFIG_SYS_NUM_FMAN 2
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	530	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	531	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	532	#define CONFIG_SYS_FMAN_V3
				533	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				534	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				535	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
				536	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				537	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				538	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				539	#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
				540	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				541	#define CONFIG_SYS_FSL_ERRATUM_A004468
				542	#define CONFIG_SYS_FSL_ERRATUM_A_004934
				543	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	8212519	2013-05-15 17:50:13 -0500	[diff] [blame]	544	#define CONFIG_SYS_FSL_ERRATUM_A006593
York Sun	b624084	2013-03-25 07:33:29 +0000	[diff] [blame]	545	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				546	#define CONFIG_SYS_FSL_PCI_VER_3_X
				547
Poonam Aggrwal	8fa0102	2013-03-25 07:40:20 +0000	[diff] [blame]	548	#elif defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_B4420)
				549	#define CONFIG_E6500
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	550	#define CONFIG_SYS_PPC64 /* 64-bit core */
				551	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				552	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
				553	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	554	#define CONFIG_SYS_FSL_NUM_LAWS 32
				555	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				556	#define CONFIG_SYS_NUM_FMAN 1
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	557	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	362ee04	2013-05-16 10:18:13 +0800	[diff] [blame]	558	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	559	#define CONFIG_SYS_FMAN_V3
				560	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				561	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				562	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				563	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				564	#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu	04feb57	2013-02-27 21:56:54 +0000	[diff] [blame]	565	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	8212519	2013-05-15 17:50:13 -0500	[diff] [blame]	566	#define CONFIG_SYS_FSL_ERRATUM_A006593
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	567	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				568
Poonam Aggrwal	8fa0102	2013-03-25 07:40:20 +0000	[diff] [blame]	569	#ifdef CONFIG_PPC_B4860
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	570	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	571	#define CONFIG_MAX_CPUS 4
				572	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	573	#define CONFIG_SYS_NUM_FM1_DTSEC 6
				574	#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwal	e394ceb	2012-12-23 19:22:33 +0000	[diff] [blame]	575	#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	576	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				577	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				578	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Poonam Aggrwal	8fa0102	2013-03-25 07:40:20 +0000	[diff] [blame]	579	#else
				580	#define CONFIG_MAX_CPUS 2
				581	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
				582	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
				583	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				584	#define CONFIG_SYS_NUM_FM1_10GEC 0
				585	#define CONFIG_NUM_DDR_CONTROLLERS 1
				586	#endif
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	587
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	588	#elif defined(CONFIG_PPC_T1040)
				589	#define CONFIG_E5500
				590	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				591	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	592	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun	5f208d1	2013-03-25 07:40:06 +0000	[diff] [blame]	593	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
				594	#define CONFIG_MAX_CPUS 4
				595	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				596	#define CONFIG_SYS_FSL_NUM_LAWS 16
				597	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				598	#define CONFIG_SYS_NUM_FMAN 1
				599	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				600	#define CONFIG_NUM_DDR_CONTROLLERS 1
				601	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
				602	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
				603	#define CONFIG_SYS_FMAN_V3
				604	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				605	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				606	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				607	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				608	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				609	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				610	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				611	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				612	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				613	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				614
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	615	#else
				616	#error Processor type not defined for this platform
				617	#endif
				618
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	619	#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
				620	#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
				621	#endif
				622
York Sun	f698143	2013-03-25 07:40:07 +0000	[diff] [blame]	623	#ifdef CONFIG_E6500
				624	#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
				625	#else
				626	#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
				627	#endif
				628
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	629	#endif /* _ASM_MPC85xx_CONFIG_H_ */