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Ilya Yanok36fab992009-08-11 02:32:54 +04001/*
Scott Woodcfcbf8c2009-09-02 16:45:31 -05002 * Copyright 2004-2007 Freescale Semiconductor, Inc.
Ilya Yanok36fab992009-08-11 02:32:54 +04003 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <common.h>
22#include <nand.h>
23#include <linux/err.h>
24#include <asm/io.h>
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +000025#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
26 defined(CONFIG_MX51) || defined(CONFIG_MX53)
Ilya Yanok36fab992009-08-11 02:32:54 +040027#include <asm/arch/imx-regs.h>
28#endif
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020029#include <fsl_nfc.h>
Ilya Yanok36fab992009-08-11 02:32:54 +040030
31#define DRIVER_NAME "mxc_nand"
32
Ilya Yanok36fab992009-08-11 02:32:54 +040033typedef enum {false, true} bool;
34
35struct mxc_nand_host {
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020036 struct mtd_info mtd;
37 struct nand_chip *nand;
Ilya Yanok36fab992009-08-11 02:32:54 +040038
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020039 struct fsl_nfc_regs __iomem *regs;
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +000040#ifdef MXC_NFC_V3_2
41 struct fsl_nfc_ip_regs __iomem *ip_regs;
42#endif
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020043 int spare_only;
44 int status_request;
45 int pagesize_2k;
46 int clk_act;
47 uint16_t col_addr;
48 unsigned int page_addr;
Ilya Yanok36fab992009-08-11 02:32:54 +040049};
50
51static struct mxc_nand_host mxc_host;
52static struct mxc_nand_host *host = &mxc_host;
53
54/* Define delays in microsec for NAND device operations */
55#define TROP_US_DELAY 2000
56/* Macros to get byte and bit positions of ECC */
57#define COLPOS(x) ((x) >> 3)
58#define BITPOS(x) ((x) & 0xf)
59
60/* Define single bit Error positions in Main & Spare area */
61#define MAIN_SINGLEBIT_ERROR 0x4
62#define SPARE_SINGLEBIT_ERROR 0x1
63
64/* OOB placement block for use with hardware ecc generation */
John Rigbyb081c2e2010-01-26 19:24:18 -070065#if defined(MXC_NFC_V1)
66#ifndef CONFIG_SYS_NAND_LARGEPAGE
Ilya Yanok36fab992009-08-11 02:32:54 +040067static struct nand_ecclayout nand_hw_eccoob = {
68 .eccbytes = 5,
69 .eccpos = {6, 7, 8, 9, 10},
John Rigbyb081c2e2010-01-26 19:24:18 -070070 .oobfree = { {0, 5}, {11, 5}, }
Ilya Yanok36fab992009-08-11 02:32:54 +040071};
72#else
John Rigbyb081c2e2010-01-26 19:24:18 -070073static struct nand_ecclayout nand_hw_eccoob2k = {
74 .eccbytes = 20,
75 .eccpos = {
76 6, 7, 8, 9, 10,
77 22, 23, 24, 25, 26,
78 38, 39, 40, 41, 42,
79 54, 55, 56, 57, 58,
80 },
81 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
Ilya Yanok36fab992009-08-11 02:32:54 +040082};
83#endif
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +000084#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
John Rigbyb081c2e2010-01-26 19:24:18 -070085#ifndef CONFIG_SYS_NAND_LARGEPAGE
86static struct nand_ecclayout nand_hw_eccoob = {
87 .eccbytes = 9,
88 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
89 .oobfree = { {2, 5} }
Magnus Liljac4832df2010-01-17 17:46:10 +010090};
John Rigbyb081c2e2010-01-26 19:24:18 -070091#else
92static struct nand_ecclayout nand_hw_eccoob2k = {
93 .eccbytes = 36,
94 .eccpos = {
95 7, 8, 9, 10, 11, 12, 13, 14, 15,
96 23, 24, 25, 26, 27, 28, 29, 30, 31,
97 39, 40, 41, 42, 43, 44, 45, 46, 47,
98 55, 56, 57, 58, 59, 60, 61, 62, 63,
99 },
100 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
101};
102#endif
103#endif
Magnus Liljac4832df2010-01-17 17:46:10 +0100104
Magnus Liljaf6a97482009-11-11 20:18:43 +0100105static int is_16bit_nand(void)
106{
Fabio Estevama430e912013-04-11 09:35:35 +0000107#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
108 return 1;
Magnus Liljaf6a97482009-11-11 20:18:43 +0100109#else
Magnus Liljaf6a97482009-11-11 20:18:43 +0100110 return 0;
Magnus Liljaf6a97482009-11-11 20:18:43 +0100111#endif
Fabio Estevama430e912013-04-11 09:35:35 +0000112}
Magnus Liljaf6a97482009-11-11 20:18:43 +0100113
Ilya Yanok36fab992009-08-11 02:32:54 +0400114static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
115{
116 uint32_t *d = dest;
117
118 size >>= 2;
119 while (size--)
120 __raw_writel(__raw_readl(source++), d++);
121 return dest;
122}
123
124/*
125 * This function polls the NANDFC to wait for the basic operation to
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000126 * complete by checking the INT bit.
Ilya Yanok36fab992009-08-11 02:32:54 +0400127 */
128static void wait_op_done(struct mxc_nand_host *host, int max_retries,
129 uint16_t param)
130{
131 uint32_t tmp;
132
133 while (max_retries-- > 0) {
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000134#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000135 tmp = readnfc(&host->regs->config2);
136 if (tmp & NFC_V1_V2_CONFIG2_INT) {
137 tmp &= ~NFC_V1_V2_CONFIG2_INT;
138 writenfc(tmp, &host->regs->config2);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000139#elif defined(MXC_NFC_V3_2)
140 tmp = readnfc(&host->ip_regs->ipc);
141 if (tmp & NFC_V3_IPC_INT) {
142 tmp &= ~NFC_V3_IPC_INT;
143 writenfc(tmp, &host->ip_regs->ipc);
144#endif
Ilya Yanok36fab992009-08-11 02:32:54 +0400145 break;
146 }
147 udelay(1);
148 }
149 if (max_retries < 0) {
150 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
151 __func__, param);
152 }
153}
154
155/*
156 * This function issues the specified command to the NAND device and
157 * waits for completion.
158 */
159static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
160{
161 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
162
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000163 writenfc(cmd, &host->regs->flash_cmd);
164 writenfc(NFC_CMD, &host->regs->operation);
Ilya Yanok36fab992009-08-11 02:32:54 +0400165
166 /* Wait for operation to complete */
167 wait_op_done(host, TROP_US_DELAY, cmd);
168}
169
170/*
171 * This function sends an address (or partial address) to the
172 * NAND device. The address is used to select the source/destination for
173 * a NAND command.
174 */
175static void send_addr(struct mxc_nand_host *host, uint16_t addr)
176{
177 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
178
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000179 writenfc(addr, &host->regs->flash_addr);
180 writenfc(NFC_ADDR, &host->regs->operation);
Ilya Yanok36fab992009-08-11 02:32:54 +0400181
182 /* Wait for operation to complete */
183 wait_op_done(host, TROP_US_DELAY, addr);
184}
185
186/*
Helmut Raiger780f30b2011-07-06 09:40:28 +0200187 * This function requests the NANDFC to initiate the transfer
Ilya Yanok36fab992009-08-11 02:32:54 +0400188 * of data currently in the NANDFC RAM buffer to the NAND device.
189 */
190static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
191 int spare_only)
192{
John Rigbyb081c2e2010-01-26 19:24:18 -0700193 if (spare_only)
194 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
195
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000196 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700197 int i;
198 /*
199 * The controller copies the 64 bytes of spare data from
200 * the first 16 bytes of each of the 4 64 byte spare buffers.
201 * Copy the contiguous data starting in spare_area[0] to
202 * the four spare area buffers.
203 */
204 for (i = 1; i < 4; i++) {
205 void __iomem *src = &host->regs->spare_area[0][i * 16];
206 void __iomem *dst = &host->regs->spare_area[i][0];
207
208 mxc_nand_memcpy32(dst, src, 16);
209 }
210 }
Ilya Yanok36fab992009-08-11 02:32:54 +0400211
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000212#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000213 writenfc(buf_id, &host->regs->buf_addr);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000214#elif defined(MXC_NFC_V3_2)
215 uint32_t tmp = readnfc(&host->regs->config1);
216 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
217 tmp |= NFC_V3_CONFIG1_RBA(buf_id);
218 writenfc(tmp, &host->regs->config1);
219#endif
Ilya Yanok36fab992009-08-11 02:32:54 +0400220
221 /* Configure spare or page+spare access */
222 if (!host->pagesize_2k) {
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000223 uint32_t config1 = readnfc(&host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400224 if (spare_only)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000225 config1 |= NFC_CONFIG1_SP_EN;
Ilya Yanok36fab992009-08-11 02:32:54 +0400226 else
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000227 config1 &= ~NFC_CONFIG1_SP_EN;
228 writenfc(config1, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400229 }
230
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000231 writenfc(NFC_INPUT, &host->regs->operation);
Ilya Yanok36fab992009-08-11 02:32:54 +0400232
233 /* Wait for operation to complete */
234 wait_op_done(host, TROP_US_DELAY, spare_only);
235}
236
237/*
Helmut Raiger780f30b2011-07-06 09:40:28 +0200238 * Requests NANDFC to initiate the transfer of data from the
Ilya Yanok36fab992009-08-11 02:32:54 +0400239 * NAND device into in the NANDFC ram buffer.
240 */
241static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
242 int spare_only)
243{
244 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
245
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000246#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000247 writenfc(buf_id, &host->regs->buf_addr);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000248#elif defined(MXC_NFC_V3_2)
249 uint32_t tmp = readnfc(&host->regs->config1);
250 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
251 tmp |= NFC_V3_CONFIG1_RBA(buf_id);
252 writenfc(tmp, &host->regs->config1);
253#endif
Ilya Yanok36fab992009-08-11 02:32:54 +0400254
255 /* Configure spare or page+spare access */
256 if (!host->pagesize_2k) {
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000257 uint32_t config1 = readnfc(&host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400258 if (spare_only)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000259 config1 |= NFC_CONFIG1_SP_EN;
Ilya Yanok36fab992009-08-11 02:32:54 +0400260 else
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000261 config1 &= ~NFC_CONFIG1_SP_EN;
262 writenfc(config1, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400263 }
264
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000265 writenfc(NFC_OUTPUT, &host->regs->operation);
Ilya Yanok36fab992009-08-11 02:32:54 +0400266
267 /* Wait for operation to complete */
268 wait_op_done(host, TROP_US_DELAY, spare_only);
John Rigbyb081c2e2010-01-26 19:24:18 -0700269
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000270 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700271 int i;
272
273 /*
274 * The controller copies the 64 bytes of spare data to
275 * the first 16 bytes of each of the 4 spare buffers.
276 * Make the data contiguous starting in spare_area[0].
277 */
278 for (i = 1; i < 4; i++) {
279 void __iomem *src = &host->regs->spare_area[i][0];
280 void __iomem *dst = &host->regs->spare_area[0][i * 16];
281
282 mxc_nand_memcpy32(dst, src, 16);
283 }
284 }
Ilya Yanok36fab992009-08-11 02:32:54 +0400285}
286
287/* Request the NANDFC to perform a read of the NAND device ID. */
288static void send_read_id(struct mxc_nand_host *host)
289{
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000290 uint32_t tmp;
Ilya Yanok36fab992009-08-11 02:32:54 +0400291
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000292#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Ilya Yanok36fab992009-08-11 02:32:54 +0400293 /* NANDFC buffer 0 is used for device ID output */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000294 writenfc(0x0, &host->regs->buf_addr);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000295#elif defined(MXC_NFC_V3_2)
296 tmp = readnfc(&host->regs->config1);
297 tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
298 writenfc(tmp, &host->regs->config1);
299#endif
Ilya Yanok36fab992009-08-11 02:32:54 +0400300
301 /* Read ID into main buffer */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000302 tmp = readnfc(&host->regs->config1);
303 tmp &= ~NFC_CONFIG1_SP_EN;
304 writenfc(tmp, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400305
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000306 writenfc(NFC_ID, &host->regs->operation);
Ilya Yanok36fab992009-08-11 02:32:54 +0400307
308 /* Wait for operation to complete */
309 wait_op_done(host, TROP_US_DELAY, 0);
310}
311
312/*
313 * This function requests the NANDFC to perform a read of the
314 * NAND device status and returns the current status.
315 */
316static uint16_t get_dev_status(struct mxc_nand_host *host)
317{
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000318#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
John Rigbyb081c2e2010-01-26 19:24:18 -0700319 void __iomem *main_buf = host->regs->main_area[1];
Ilya Yanok36fab992009-08-11 02:32:54 +0400320 uint32_t store;
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000321#endif
322 uint32_t ret, tmp;
Ilya Yanok36fab992009-08-11 02:32:54 +0400323 /* Issue status request to NAND device */
324
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000325#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Ilya Yanok36fab992009-08-11 02:32:54 +0400326 /* store the main area1 first word, later do recovery */
327 store = readl(main_buf);
328 /* NANDFC buffer 1 is used for device status */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000329 writenfc(1, &host->regs->buf_addr);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000330#endif
Ilya Yanok36fab992009-08-11 02:32:54 +0400331
332 /* Read status into main buffer */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000333 tmp = readnfc(&host->regs->config1);
334 tmp &= ~NFC_CONFIG1_SP_EN;
335 writenfc(tmp, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400336
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000337 writenfc(NFC_STATUS, &host->regs->operation);
Ilya Yanok36fab992009-08-11 02:32:54 +0400338
339 /* Wait for operation to complete */
340 wait_op_done(host, TROP_US_DELAY, 0);
341
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000342#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Ilya Yanok36fab992009-08-11 02:32:54 +0400343 /*
344 * Status is placed in first word of main buffer
345 * get status, then recovery area 1 data
346 */
347 ret = readw(main_buf);
348 writel(store, main_buf);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000349#elif defined(MXC_NFC_V3_2)
350 ret = readnfc(&host->regs->config1) >> 16;
351#endif
Ilya Yanok36fab992009-08-11 02:32:54 +0400352
353 return ret;
354}
355
356/* This function is used by upper layer to checks if device is ready */
357static int mxc_nand_dev_ready(struct mtd_info *mtd)
358{
359 /*
360 * NFC handles R/B internally. Therefore, this function
361 * always returns status as ready.
362 */
363 return 1;
364}
365
John Rigbyb081c2e2010-01-26 19:24:18 -0700366static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
367{
368 struct nand_chip *nand_chip = mtd->priv;
369 struct mxc_nand_host *host = nand_chip->priv;
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000370#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000371 uint16_t tmp = readnfc(&host->regs->config1);
John Rigbyb081c2e2010-01-26 19:24:18 -0700372
373 if (on)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000374 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
John Rigbyb081c2e2010-01-26 19:24:18 -0700375 else
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000376 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
377 writenfc(tmp, &host->regs->config1);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000378#elif defined(MXC_NFC_V3_2)
379 uint32_t tmp = readnfc(&host->ip_regs->config2);
380
381 if (on)
382 tmp |= NFC_V3_CONFIG2_ECC_EN;
383 else
384 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
385 writenfc(tmp, &host->ip_regs->config2);
386#endif
John Rigbyb081c2e2010-01-26 19:24:18 -0700387}
388
Benoît Thébaudeau0e499b02012-08-13 22:50:07 +0200389#ifdef CONFIG_MXC_NAND_HWECC
390static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
391{
392 /*
393 * If HW ECC is enabled, we turn it on during init. There is
394 * no need to enable again here.
395 */
396}
397
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +0000398#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
John Rigbyb081c2e2010-01-26 19:24:18 -0700399static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
400 struct nand_chip *chip,
401 int page, int sndcmd)
402{
403 struct mxc_nand_host *host = chip->priv;
404 uint8_t *buf = chip->oob_poi;
405 int length = mtd->oobsize;
406 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
407 uint8_t *bufpoi = buf;
408 int i, toread;
409
410 MTDDEBUG(MTD_DEBUG_LEVEL0,
411 "%s: Reading OOB area of page %u to oob %p\n",
Benoît Thébaudeau78ee7b12013-04-11 09:35:40 +0000412 __func__, page, buf);
John Rigbyb081c2e2010-01-26 19:24:18 -0700413
414 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
415 for (i = 0; i < chip->ecc.steps; i++) {
416 toread = min_t(int, length, chip->ecc.prepad);
417 if (toread) {
418 chip->read_buf(mtd, bufpoi, toread);
419 bufpoi += toread;
420 length -= toread;
421 }
422 bufpoi += chip->ecc.bytes;
423 host->col_addr += chip->ecc.bytes;
424 length -= chip->ecc.bytes;
425
426 toread = min_t(int, length, chip->ecc.postpad);
427 if (toread) {
428 chip->read_buf(mtd, bufpoi, toread);
429 bufpoi += toread;
430 length -= toread;
431 }
432 }
433 if (length > 0)
434 chip->read_buf(mtd, bufpoi, length);
435
436 _mxc_nand_enable_hwecc(mtd, 0);
437 chip->cmdfunc(mtd, NAND_CMD_READOOB,
438 mtd->writesize + chip->ecc.prepad, page);
439 bufpoi = buf + chip->ecc.prepad;
440 length = mtd->oobsize - chip->ecc.prepad;
441 for (i = 0; i < chip->ecc.steps; i++) {
442 toread = min_t(int, length, chip->ecc.bytes);
443 chip->read_buf(mtd, bufpoi, toread);
444 bufpoi += eccpitch;
445 length -= eccpitch;
446 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
447 }
448 _mxc_nand_enable_hwecc(mtd, 1);
449 return 1;
450}
451
452static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
453 struct nand_chip *chip,
454 uint8_t *buf,
455 int page)
456{
457 struct mxc_nand_host *host = chip->priv;
458 int eccsize = chip->ecc.size;
459 int eccbytes = chip->ecc.bytes;
460 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
461 uint8_t *oob = chip->oob_poi;
462 int steps, size;
463 int n;
464
465 _mxc_nand_enable_hwecc(mtd, 0);
Benoît Thébaudeau3ec9d6e2013-04-11 09:35:41 +0000466 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
John Rigbyb081c2e2010-01-26 19:24:18 -0700467
468 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
469 host->col_addr = n * eccsize;
470 chip->read_buf(mtd, buf, eccsize);
471 buf += eccsize;
472
473 host->col_addr = mtd->writesize + n * eccpitch;
474 if (chip->ecc.prepad) {
475 chip->read_buf(mtd, oob, chip->ecc.prepad);
476 oob += chip->ecc.prepad;
477 }
478
479 chip->read_buf(mtd, oob, eccbytes);
480 oob += eccbytes;
481
482 if (chip->ecc.postpad) {
483 chip->read_buf(mtd, oob, chip->ecc.postpad);
484 oob += chip->ecc.postpad;
485 }
486 }
487
488 size = mtd->oobsize - (oob - chip->oob_poi);
489 if (size)
490 chip->read_buf(mtd, oob, size);
Benoît Thébaudeau7c28a1c2012-08-13 22:50:19 +0200491 _mxc_nand_enable_hwecc(mtd, 1);
John Rigbyb081c2e2010-01-26 19:24:18 -0700492
493 return 0;
494}
495
496static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
497 struct nand_chip *chip,
498 uint8_t *buf,
499 int page)
500{
501 struct mxc_nand_host *host = chip->priv;
502 int n, eccsize = chip->ecc.size;
503 int eccbytes = chip->ecc.bytes;
504 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
505 int eccsteps = chip->ecc.steps;
506 uint8_t *p = buf;
507 uint8_t *oob = chip->oob_poi;
508
509 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
Benoît Thébaudeau3ec9d6e2013-04-11 09:35:41 +0000510 page, buf, oob);
John Rigbyb081c2e2010-01-26 19:24:18 -0700511
Helmut Raiger780f30b2011-07-06 09:40:28 +0200512 /* first read the data area and the available portion of OOB */
John Rigbyb081c2e2010-01-26 19:24:18 -0700513 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
514 int stat;
515
516 host->col_addr = n * eccsize;
517
518 chip->read_buf(mtd, p, eccsize);
519
520 host->col_addr = mtd->writesize + n * eccpitch;
521
522 if (chip->ecc.prepad) {
523 chip->read_buf(mtd, oob, chip->ecc.prepad);
524 oob += chip->ecc.prepad;
525 }
526
527 stat = chip->ecc.correct(mtd, p, oob, NULL);
528
529 if (stat < 0)
530 mtd->ecc_stats.failed++;
531 else
532 mtd->ecc_stats.corrected += stat;
533 oob += eccbytes;
534
535 if (chip->ecc.postpad) {
536 chip->read_buf(mtd, oob, chip->ecc.postpad);
537 oob += chip->ecc.postpad;
538 }
539 }
540
541 /* Calculate remaining oob bytes */
542 n = mtd->oobsize - (oob - chip->oob_poi);
543 if (n)
544 chip->read_buf(mtd, oob, n);
545
546 /* Then switch ECC off and read the OOB area to get the ECC code */
547 _mxc_nand_enable_hwecc(mtd, 0);
Benoît Thébaudeau3ec9d6e2013-04-11 09:35:41 +0000548 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
John Rigbyb081c2e2010-01-26 19:24:18 -0700549 eccsteps = chip->ecc.steps;
550 oob = chip->oob_poi + chip->ecc.prepad;
551 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
552 host->col_addr = mtd->writesize +
553 n * eccpitch +
554 chip->ecc.prepad;
555 chip->read_buf(mtd, oob, eccbytes);
556 oob += eccbytes + chip->ecc.postpad;
557 }
558 _mxc_nand_enable_hwecc(mtd, 1);
559 return 0;
560}
561
562static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
563 struct nand_chip *chip, int page)
564{
565 struct mxc_nand_host *host = chip->priv;
566 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
567 int length = mtd->oobsize;
568 int i, len, status, steps = chip->ecc.steps;
569 const uint8_t *bufpoi = chip->oob_poi;
570
571 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
572 for (i = 0; i < steps; i++) {
573 len = min_t(int, length, eccpitch);
574
575 chip->write_buf(mtd, bufpoi, len);
576 bufpoi += len;
577 length -= len;
578 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
579 }
580 if (length > 0)
581 chip->write_buf(mtd, bufpoi, length);
582
583 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
584 status = chip->waitfunc(mtd, chip);
585 return status & NAND_STATUS_FAIL ? -EIO : 0;
586}
587
588static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
589 struct nand_chip *chip,
590 const uint8_t *buf)
591{
592 struct mxc_nand_host *host = chip->priv;
593 int eccsize = chip->ecc.size;
594 int eccbytes = chip->ecc.bytes;
595 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
596 uint8_t *oob = chip->oob_poi;
597 int steps, size;
598 int n;
599
600 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
601 host->col_addr = n * eccsize;
602 chip->write_buf(mtd, buf, eccsize);
603 buf += eccsize;
604
605 host->col_addr = mtd->writesize + n * eccpitch;
606
607 if (chip->ecc.prepad) {
608 chip->write_buf(mtd, oob, chip->ecc.prepad);
609 oob += chip->ecc.prepad;
610 }
611
612 host->col_addr += eccbytes;
613 oob += eccbytes;
614
615 if (chip->ecc.postpad) {
616 chip->write_buf(mtd, oob, chip->ecc.postpad);
617 oob += chip->ecc.postpad;
618 }
619 }
620
621 size = mtd->oobsize - (oob - chip->oob_poi);
622 if (size)
623 chip->write_buf(mtd, oob, size);
624}
625
626static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
627 struct nand_chip *chip,
628 const uint8_t *buf)
629{
630 struct mxc_nand_host *host = chip->priv;
631 int i, n, eccsize = chip->ecc.size;
632 int eccbytes = chip->ecc.bytes;
633 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
634 int eccsteps = chip->ecc.steps;
635 const uint8_t *p = buf;
636 uint8_t *oob = chip->oob_poi;
637
638 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
639
640 for (i = n = 0;
641 eccsteps;
642 n++, eccsteps--, i += eccbytes, p += eccsize) {
643 host->col_addr = n * eccsize;
644
645 chip->write_buf(mtd, p, eccsize);
646
647 host->col_addr = mtd->writesize + n * eccpitch;
648
649 if (chip->ecc.prepad) {
650 chip->write_buf(mtd, oob, chip->ecc.prepad);
651 oob += chip->ecc.prepad;
652 }
653
654 chip->write_buf(mtd, oob, eccbytes);
655 oob += eccbytes;
656
657 if (chip->ecc.postpad) {
658 chip->write_buf(mtd, oob, chip->ecc.postpad);
659 oob += chip->ecc.postpad;
660 }
661 }
662
663 /* Calculate remaining oob bytes */
664 i = mtd->oobsize - (oob - chip->oob_poi);
665 if (i)
666 chip->write_buf(mtd, oob, i);
667}
668
669static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
670 u_char *read_ecc, u_char *calc_ecc)
671{
672 struct nand_chip *nand_chip = mtd->priv;
673 struct mxc_nand_host *host = nand_chip->priv;
Benoît Thébaudeauc1db8dd2012-08-13 22:49:42 +0200674 uint32_t ecc_status = readl(&host->regs->ecc_status_result);
John Rigbyb081c2e2010-01-26 19:24:18 -0700675 int subpages = mtd->writesize / nand_chip->subpagesize;
676 int pg2blk_shift = nand_chip->phys_erase_shift -
677 nand_chip->page_shift;
678
679 do {
680 if ((ecc_status & 0xf) > 4) {
681 static int last_bad = -1;
682
683 if (last_bad != host->page_addr >> pg2blk_shift) {
684 last_bad = host->page_addr >> pg2blk_shift;
685 printk(KERN_DEBUG
686 "MXC_NAND: HWECC uncorrectable ECC error"
687 " in block %u page %u subpage %d\n",
688 last_bad, host->page_addr,
689 mtd->writesize / nand_chip->subpagesize
690 - subpages);
691 }
692 return -1;
693 }
694 ecc_status >>= 4;
695 subpages--;
696 } while (subpages > 0);
697
698 return 0;
699}
700#else
701#define mxc_nand_read_page_syndrome NULL
702#define mxc_nand_read_page_raw_syndrome NULL
703#define mxc_nand_read_oob_syndrome NULL
704#define mxc_nand_write_page_syndrome NULL
705#define mxc_nand_write_page_raw_syndrome NULL
706#define mxc_nand_write_oob_syndrome NULL
John Rigbyb081c2e2010-01-26 19:24:18 -0700707
Ilya Yanok36fab992009-08-11 02:32:54 +0400708static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
709 u_char *read_ecc, u_char *calc_ecc)
710{
711 struct nand_chip *nand_chip = mtd->priv;
712 struct mxc_nand_host *host = nand_chip->priv;
713
714 /*
715 * 1-Bit errors are automatically corrected in HW. No need for
716 * additional correction. 2-Bit errors cannot be corrected by
717 * HW ECC, so we need to return failure
718 */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +0000719 uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
Ilya Yanok36fab992009-08-11 02:32:54 +0400720
721 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
722 MTDDEBUG(MTD_DEBUG_LEVEL0,
723 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
724 return -1;
725 }
726
727 return 0;
728}
John Rigbyb081c2e2010-01-26 19:24:18 -0700729#endif
730
Ilya Yanok36fab992009-08-11 02:32:54 +0400731static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
732 u_char *ecc_code)
733{
734 return 0;
735}
736#endif
737
738static u_char mxc_nand_read_byte(struct mtd_info *mtd)
739{
740 struct nand_chip *nand_chip = mtd->priv;
741 struct mxc_nand_host *host = nand_chip->priv;
742 uint8_t ret = 0;
743 uint16_t col;
744 uint16_t __iomem *main_buf =
John Rigbyb081c2e2010-01-26 19:24:18 -0700745 (uint16_t __iomem *)host->regs->main_area[0];
Ilya Yanok36fab992009-08-11 02:32:54 +0400746 uint16_t __iomem *spare_buf =
John Rigbyb081c2e2010-01-26 19:24:18 -0700747 (uint16_t __iomem *)host->regs->spare_area[0];
Ilya Yanok36fab992009-08-11 02:32:54 +0400748 union {
749 uint16_t word;
750 uint8_t bytes[2];
751 } nfc_word;
752
753 /* Check for status request */
754 if (host->status_request)
755 return get_dev_status(host) & 0xFF;
756
757 /* Get column for 16-bit access */
758 col = host->col_addr >> 1;
759
760 /* If we are accessing the spare region */
761 if (host->spare_only)
762 nfc_word.word = readw(&spare_buf[col]);
763 else
764 nfc_word.word = readw(&main_buf[col]);
765
766 /* Pick upper/lower byte of word from RAM buffer */
767 ret = nfc_word.bytes[host->col_addr & 0x1];
768
769 /* Update saved column address */
770 if (nand_chip->options & NAND_BUSWIDTH_16)
771 host->col_addr += 2;
772 else
773 host->col_addr++;
774
775 return ret;
776}
777
778static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
779{
780 struct nand_chip *nand_chip = mtd->priv;
781 struct mxc_nand_host *host = nand_chip->priv;
782 uint16_t col, ret;
783 uint16_t __iomem *p;
784
785 MTDDEBUG(MTD_DEBUG_LEVEL3,
786 "mxc_nand_read_word(col = %d)\n", host->col_addr);
787
788 col = host->col_addr;
789 /* Adjust saved column address */
790 if (col < mtd->writesize && host->spare_only)
791 col += mtd->writesize;
792
793 if (col < mtd->writesize) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700794 p = (uint16_t __iomem *)(host->regs->main_area[0] +
795 (col >> 1));
Ilya Yanok36fab992009-08-11 02:32:54 +0400796 } else {
John Rigbyb081c2e2010-01-26 19:24:18 -0700797 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
Ilya Yanok36fab992009-08-11 02:32:54 +0400798 ((col - mtd->writesize) >> 1));
799 }
800
801 if (col & 1) {
802 union {
803 uint16_t word;
804 uint8_t bytes[2];
805 } nfc_word[3];
806
807 nfc_word[0].word = readw(p);
808 nfc_word[1].word = readw(p + 1);
809
810 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
811 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
812
813 ret = nfc_word[2].word;
814 } else {
815 ret = readw(p);
816 }
817
818 /* Update saved column address */
819 host->col_addr = col + 2;
820
821 return ret;
822}
823
824/*
825 * Write data of length len to buffer buf. The data to be
826 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
827 * Operation by the NFC, the data is written to NAND Flash
828 */
829static void mxc_nand_write_buf(struct mtd_info *mtd,
830 const u_char *buf, int len)
831{
832 struct nand_chip *nand_chip = mtd->priv;
833 struct mxc_nand_host *host = nand_chip->priv;
834 int n, col, i = 0;
835
836 MTDDEBUG(MTD_DEBUG_LEVEL3,
837 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
838 len);
839
840 col = host->col_addr;
841
842 /* Adjust saved column address */
843 if (col < mtd->writesize && host->spare_only)
844 col += mtd->writesize;
845
846 n = mtd->writesize + mtd->oobsize - col;
847 n = min(len, n);
848
849 MTDDEBUG(MTD_DEBUG_LEVEL3,
850 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
851
852 while (n > 0) {
853 void __iomem *p;
854
855 if (col < mtd->writesize) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700856 p = host->regs->main_area[0] + (col & ~3);
Ilya Yanok36fab992009-08-11 02:32:54 +0400857 } else {
John Rigbyb081c2e2010-01-26 19:24:18 -0700858 p = host->regs->spare_area[0] -
Ilya Yanok36fab992009-08-11 02:32:54 +0400859 mtd->writesize + (col & ~3);
860 }
861
862 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
863 __LINE__, p);
864
865 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
866 union {
867 uint32_t word;
868 uint8_t bytes[4];
869 } nfc_word;
870
871 nfc_word.word = readl(p);
872 nfc_word.bytes[col & 3] = buf[i++];
873 n--;
874 col++;
875
876 writel(nfc_word.word, p);
877 } else {
878 int m = mtd->writesize - col;
879
880 if (col >= mtd->writesize)
881 m += mtd->oobsize;
882
883 m = min(n, m) & ~3;
884
885 MTDDEBUG(MTD_DEBUG_LEVEL3,
886 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
887 __func__, __LINE__, n, m, i, col);
888
889 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
890 col += m;
891 i += m;
892 n -= m;
893 }
894 }
895 /* Update saved column address */
896 host->col_addr = col;
897}
898
899/*
900 * Read the data buffer from the NAND Flash. To read the data from NAND
901 * Flash first the data output cycle is initiated by the NFC, which copies
902 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
903 */
904static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
905{
906 struct nand_chip *nand_chip = mtd->priv;
907 struct mxc_nand_host *host = nand_chip->priv;
908 int n, col, i = 0;
909
910 MTDDEBUG(MTD_DEBUG_LEVEL3,
911 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
912
913 col = host->col_addr;
914
915 /* Adjust saved column address */
916 if (col < mtd->writesize && host->spare_only)
917 col += mtd->writesize;
918
919 n = mtd->writesize + mtd->oobsize - col;
920 n = min(len, n);
921
922 while (n > 0) {
923 void __iomem *p;
924
925 if (col < mtd->writesize) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700926 p = host->regs->main_area[0] + (col & ~3);
Ilya Yanok36fab992009-08-11 02:32:54 +0400927 } else {
John Rigbyb081c2e2010-01-26 19:24:18 -0700928 p = host->regs->spare_area[0] -
Ilya Yanok36fab992009-08-11 02:32:54 +0400929 mtd->writesize + (col & ~3);
930 }
931
932 if (((col | (int)&buf[i]) & 3) || n < 4) {
933 union {
934 uint32_t word;
935 uint8_t bytes[4];
936 } nfc_word;
937
938 nfc_word.word = readl(p);
939 buf[i++] = nfc_word.bytes[col & 3];
940 n--;
941 col++;
942 } else {
943 int m = mtd->writesize - col;
944
945 if (col >= mtd->writesize)
946 m += mtd->oobsize;
947
948 m = min(n, m) & ~3;
949 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
950
951 col += m;
952 i += m;
953 n -= m;
954 }
955 }
956 /* Update saved column address */
957 host->col_addr = col;
958}
959
960/*
961 * Used by the upper layer to verify the data in NAND Flash
962 * with the data in the buf.
963 */
964static int mxc_nand_verify_buf(struct mtd_info *mtd,
965 const u_char *buf, int len)
966{
967 u_char tmp[256];
968 uint bsize;
969
970 while (len) {
971 bsize = min(len, 256);
972 mxc_nand_read_buf(mtd, tmp, bsize);
973
974 if (memcmp(buf, tmp, bsize))
975 return 1;
976
977 buf += bsize;
978 len -= bsize;
979 }
980
981 return 0;
982}
983
984/*
985 * This function is used by upper layer for select and
986 * deselect of the NAND chip
987 */
988static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
989{
990 struct nand_chip *nand_chip = mtd->priv;
991 struct mxc_nand_host *host = nand_chip->priv;
992
993 switch (chip) {
994 case -1:
995 /* TODO: Disable the NFC clock */
996 if (host->clk_act)
997 host->clk_act = 0;
998 break;
999 case 0:
1000 /* TODO: Enable the NFC clock */
1001 if (!host->clk_act)
1002 host->clk_act = 1;
1003 break;
1004
1005 default:
1006 break;
1007 }
1008}
1009
1010/*
1011 * Used by the upper layer to write command to NAND Flash for
1012 * different operations to be carried out on NAND Flash
1013 */
John Rigbyb081c2e2010-01-26 19:24:18 -07001014void mxc_nand_command(struct mtd_info *mtd, unsigned command,
Ilya Yanok36fab992009-08-11 02:32:54 +04001015 int column, int page_addr)
1016{
1017 struct nand_chip *nand_chip = mtd->priv;
1018 struct mxc_nand_host *host = nand_chip->priv;
1019
1020 MTDDEBUG(MTD_DEBUG_LEVEL3,
1021 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1022 command, column, page_addr);
1023
1024 /* Reset command state information */
1025 host->status_request = false;
1026
1027 /* Command pre-processing step */
1028 switch (command) {
1029
1030 case NAND_CMD_STATUS:
1031 host->col_addr = 0;
1032 host->status_request = true;
1033 break;
1034
1035 case NAND_CMD_READ0:
John Rigbyb081c2e2010-01-26 19:24:18 -07001036 host->page_addr = page_addr;
Ilya Yanok36fab992009-08-11 02:32:54 +04001037 host->col_addr = column;
1038 host->spare_only = false;
1039 break;
1040
1041 case NAND_CMD_READOOB:
1042 host->col_addr = column;
1043 host->spare_only = true;
1044 if (host->pagesize_2k)
1045 command = NAND_CMD_READ0; /* only READ0 is valid */
1046 break;
1047
1048 case NAND_CMD_SEQIN:
1049 if (column >= mtd->writesize) {
1050 /*
1051 * before sending SEQIN command for partial write,
1052 * we need read one page out. FSL NFC does not support
Helmut Raiger780f30b2011-07-06 09:40:28 +02001053 * partial write. It always sends out 512+ecc+512+ecc
Ilya Yanok36fab992009-08-11 02:32:54 +04001054 * for large page nand flash. But for small page nand
1055 * flash, it does support SPARE ONLY operation.
1056 */
1057 if (host->pagesize_2k) {
1058 /* call ourself to read a page */
1059 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1060 page_addr);
1061 }
1062
1063 host->col_addr = column - mtd->writesize;
1064 host->spare_only = true;
1065
1066 /* Set program pointer to spare region */
1067 if (!host->pagesize_2k)
1068 send_cmd(host, NAND_CMD_READOOB);
1069 } else {
1070 host->spare_only = false;
1071 host->col_addr = column;
1072
1073 /* Set program pointer to page start */
1074 if (!host->pagesize_2k)
1075 send_cmd(host, NAND_CMD_READ0);
1076 }
1077 break;
1078
1079 case NAND_CMD_PAGEPROG:
1080 send_prog_page(host, 0, host->spare_only);
1081
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +02001082 if (host->pagesize_2k && is_mxc_nfc_1()) {
Helmut Raiger780f30b2011-07-06 09:40:28 +02001083 /* data in 4 areas */
Ilya Yanok36fab992009-08-11 02:32:54 +04001084 send_prog_page(host, 1, host->spare_only);
1085 send_prog_page(host, 2, host->spare_only);
1086 send_prog_page(host, 3, host->spare_only);
1087 }
1088
1089 break;
1090 }
1091
1092 /* Write out the command to the device. */
1093 send_cmd(host, command);
1094
1095 /* Write out column address, if necessary */
1096 if (column != -1) {
1097 /*
1098 * MXC NANDFC can only perform full page+spare or
Helmut Raiger780f30b2011-07-06 09:40:28 +02001099 * spare-only read/write. When the upper layers perform
1100 * a read/write buffer operation, we will use the saved
1101 * column address to index into the full page.
Ilya Yanok36fab992009-08-11 02:32:54 +04001102 */
1103 send_addr(host, 0);
1104 if (host->pagesize_2k)
1105 /* another col addr cycle for 2k page */
1106 send_addr(host, 0);
1107 }
1108
1109 /* Write out page address, if necessary */
1110 if (page_addr != -1) {
John Rigbyb081c2e2010-01-26 19:24:18 -07001111 u32 page_mask = nand_chip->pagemask;
1112 do {
1113 send_addr(host, page_addr & 0xFF);
1114 page_addr >>= 8;
1115 page_mask >>= 8;
1116 } while (page_mask);
Ilya Yanok36fab992009-08-11 02:32:54 +04001117 }
1118
1119 /* Command post-processing step */
1120 switch (command) {
1121
1122 case NAND_CMD_RESET:
1123 break;
1124
1125 case NAND_CMD_READOOB:
1126 case NAND_CMD_READ0:
1127 if (host->pagesize_2k) {
1128 /* send read confirm command */
1129 send_cmd(host, NAND_CMD_READSTART);
1130 /* read for each AREA */
1131 send_read_page(host, 0, host->spare_only);
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +02001132 if (is_mxc_nfc_1()) {
John Rigbyb081c2e2010-01-26 19:24:18 -07001133 send_read_page(host, 1, host->spare_only);
1134 send_read_page(host, 2, host->spare_only);
1135 send_read_page(host, 3, host->spare_only);
1136 }
Ilya Yanok36fab992009-08-11 02:32:54 +04001137 } else {
1138 send_read_page(host, 0, host->spare_only);
1139 }
1140 break;
1141
1142 case NAND_CMD_READID:
1143 host->col_addr = 0;
1144 send_read_id(host);
1145 break;
1146
1147 case NAND_CMD_PAGEPROG:
1148 break;
1149
1150 case NAND_CMD_STATUS:
1151 break;
1152
1153 case NAND_CMD_ERASE2:
1154 break;
1155 }
1156}
1157
Timo Ketolaa1028732012-04-18 22:55:31 +00001158#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1159
1160static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1161static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1162
1163static struct nand_bbt_descr bbt_main_descr = {
1164 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1165 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1166 .offs = 0,
1167 .len = 4,
1168 .veroffs = 4,
1169 .maxblocks = 4,
1170 .pattern = bbt_pattern,
1171};
1172
1173static struct nand_bbt_descr bbt_mirror_descr = {
1174 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1175 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1176 .offs = 0,
1177 .len = 4,
1178 .veroffs = 4,
1179 .maxblocks = 4,
1180 .pattern = mirror_pattern,
1181};
1182
1183#endif
1184
Ilya Yanok36fab992009-08-11 02:32:54 +04001185int board_nand_init(struct nand_chip *this)
1186{
Ilya Yanok36fab992009-08-11 02:32:54 +04001187 struct mtd_info *mtd;
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +00001188#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1189 uint32_t tmp;
Tom Riniefa1f432012-09-18 09:24:22 -07001190#endif
Ilya Yanok36fab992009-08-11 02:32:54 +04001191
Timo Ketolaa1028732012-04-18 22:55:31 +00001192#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1193 this->options |= NAND_USE_FLASH_BBT;
1194 this->bbt_td = &bbt_main_descr;
1195 this->bbt_md = &bbt_mirror_descr;
1196#endif
1197
Ilya Yanok36fab992009-08-11 02:32:54 +04001198 /* structures must be linked */
1199 mtd = &host->mtd;
1200 mtd->priv = this;
1201 host->nand = this;
1202
1203 /* 5 us command delay time */
1204 this->chip_delay = 5;
1205
1206 this->priv = host;
1207 this->dev_ready = mxc_nand_dev_ready;
1208 this->cmdfunc = mxc_nand_command;
1209 this->select_chip = mxc_nand_select_chip;
1210 this->read_byte = mxc_nand_read_byte;
1211 this->read_word = mxc_nand_read_word;
1212 this->write_buf = mxc_nand_write_buf;
1213 this->read_buf = mxc_nand_read_buf;
1214 this->verify_buf = mxc_nand_verify_buf;
1215
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +02001216 host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +00001217#ifdef MXC_NFC_V3_2
1218 host->ip_regs =
1219 (struct fsl_nfc_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1220#endif
Ilya Yanok36fab992009-08-11 02:32:54 +04001221 host->clk_act = 1;
1222
1223#ifdef CONFIG_MXC_NAND_HWECC
1224 this->ecc.calculate = mxc_nand_calculate_ecc;
1225 this->ecc.hwctl = mxc_nand_enable_hwecc;
1226 this->ecc.correct = mxc_nand_correct_data;
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +00001227 if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
John Rigbyb081c2e2010-01-26 19:24:18 -07001228 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1229 this->ecc.read_page = mxc_nand_read_page_syndrome;
1230 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1231 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1232 this->ecc.write_page = mxc_nand_write_page_syndrome;
1233 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1234 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1235 this->ecc.bytes = 9;
1236 this->ecc.prepad = 7;
1237 } else {
1238 this->ecc.mode = NAND_ECC_HW;
1239 }
1240
1241 host->pagesize_2k = 0;
1242
Ilya Yanok36fab992009-08-11 02:32:54 +04001243 this->ecc.size = 512;
Benoît Thébaudeau0e499b02012-08-13 22:50:07 +02001244 _mxc_nand_enable_hwecc(mtd, 1);
Ilya Yanok36fab992009-08-11 02:32:54 +04001245#else
1246 this->ecc.layout = &nand_soft_eccoob;
1247 this->ecc.mode = NAND_ECC_SOFT;
Benoît Thébaudeau0e499b02012-08-13 22:50:07 +02001248 _mxc_nand_enable_hwecc(mtd, 0);
Ilya Yanok36fab992009-08-11 02:32:54 +04001249#endif
Ilya Yanok36fab992009-08-11 02:32:54 +04001250 /* Reset NAND */
1251 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1252
Benoît Thébaudeau13927f02012-08-13 22:50:30 +02001253 /* NAND bus width determines access functions used by upper layer */
1254 if (is_16bit_nand())
1255 this->options |= NAND_BUSWIDTH_16;
1256
1257#ifdef CONFIG_SYS_NAND_LARGEPAGE
1258 host->pagesize_2k = 1;
1259 this->ecc.layout = &nand_hw_eccoob2k;
1260#else
1261 host->pagesize_2k = 0;
1262 this->ecc.layout = &nand_hw_eccoob;
1263#endif
1264
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +00001265#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +02001266#ifdef MXC_NFC_V2_1
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +00001267 tmp = readnfc(&host->regs->config1);
1268 tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1269 tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1270 writenfc(tmp, &host->regs->config1);
Benoît Thébaudeau13927f02012-08-13 22:50:30 +02001271 if (host->pagesize_2k)
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +00001272 writenfc(64/2, &host->regs->spare_area_size);
Benoît Thébaudeau13927f02012-08-13 22:50:30 +02001273 else
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +00001274 writenfc(16/2, &host->regs->spare_area_size);
Benoît Thébaudeau13927f02012-08-13 22:50:30 +02001275#endif
1276
Ilya Yanok36fab992009-08-11 02:32:54 +04001277 /*
1278 * preset operation
1279 * Unlock the internal RAM Buffer
1280 */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +00001281 writenfc(0x2, &host->regs->config);
Ilya Yanok36fab992009-08-11 02:32:54 +04001282
1283 /* Blocks to be unlocked */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +00001284 writenfc(0x0, &host->regs->unlockstart_blkaddr);
Helmut Raigerb4b1e762011-07-06 19:04:41 +02001285 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1286 * unlockend_blkaddr, but the magic 0x4000 does not always work
1287 * when writing more than some 32 megabytes (on 2k page nands)
1288 * However 0xFFFF doesn't seem to have this kind
1289 * of limitation (tried it back and forth several times).
1290 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1291 * only, but probably this was not tested there for v1.
1292 * The very same limitation seems to apply to this kernel driver.
1293 * This might be NAND chip specific and the i.MX31 datasheet is
1294 * extremely vague about the semantics of this register.
1295 */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +00001296 writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
Ilya Yanok36fab992009-08-11 02:32:54 +04001297
1298 /* Unlock Block Command for given address range */
Benoît Thébaudeau2dc0aa02013-04-11 09:35:36 +00001299 writenfc(0x4, &host->regs->wrprot);
Benoît Thébaudeau35537bc2013-04-11 09:35:37 +00001300#elif defined(MXC_NFC_V3_2)
1301 writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1302 writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1303
1304 /* Unlock the internal RAM Buffer */
1305 writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1306 &host->ip_regs->wrprot);
1307
1308 /* Blocks to be unlocked */
1309 for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1310 writenfc(0x0 | 0xFFFF << 16,
1311 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1312
1313 writenfc(0, &host->ip_regs->ipc);
1314
1315 tmp = readnfc(&host->ip_regs->config2);
1316 tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1317 NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1318 tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1319
1320 if (host->pagesize_2k) {
1321 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1322 tmp |= NFC_V3_CONFIG2_PS_2048;
1323 } else {
1324 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1325 tmp |= NFC_V3_CONFIG2_PS_512;
1326 }
1327
1328 writenfc(tmp, &host->ip_regs->config2);
1329
1330 tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1331 NFC_V3_CONFIG3_NO_SDMA |
1332 NFC_V3_CONFIG3_RBB_MODE |
1333 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1334 NFC_V3_CONFIG3_ADD_OP(0);
1335
1336 if (!(this->options & NAND_BUSWIDTH_16))
1337 tmp |= NFC_V3_CONFIG3_FW8;
1338
1339 writenfc(tmp, &host->ip_regs->config3);
1340
1341 writenfc(0, &host->ip_regs->delay_line);
1342#endif
Ilya Yanok36fab992009-08-11 02:32:54 +04001343
Benoît Thébaudeau365b2c02012-08-13 22:48:26 +02001344 return 0;
Ilya Yanok36fab992009-08-11 02:32:54 +04001345}