blob: 647be0b7ef347d2e59a192ddf4aca7702cf93a81 [file] [log] [blame]
Ilya Yanok36fab992009-08-11 02:32:54 +04001/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <common.h>
22#include <nand.h>
23#include <linux/err.h>
24#include <asm/io.h>
25#ifdef CONFIG_MX27
26#include <asm/arch/imx-regs.h>
27#endif
28
29#define DRIVER_NAME "mxc_nand"
30
31struct nfc_regs {
32/* NFC RAM BUFFER Main area 0 */
33 uint8_t main_area0[0x200];
34 uint8_t main_area1[0x200];
35 uint8_t main_area2[0x200];
36 uint8_t main_area3[0x200];
37/* SPARE BUFFER Spare area 0 */
38 uint8_t spare_area0[0x10];
39 uint8_t spare_area1[0x10];
40 uint8_t spare_area2[0x10];
41 uint8_t spare_area3[0x10];
42 uint8_t pad[0x5c0];
43/* NFC registers */
44 uint16_t nfc_buf_size;
45 uint16_t reserved;
46 uint16_t nfc_buf_addr;
47 uint16_t nfc_flash_addr;
48 uint16_t nfc_flash_cmd;
49 uint16_t nfc_config;
50 uint16_t nfc_ecc_status_result;
51 uint16_t nfc_rsltmain_area;
52 uint16_t nfc_rsltspare_area;
53 uint16_t nfc_wrprot;
54 uint16_t nfc_unlockstart_blkaddr;
55 uint16_t nfc_unlockend_blkaddr;
56 uint16_t nfc_nf_wrprst;
57 uint16_t nfc_config1;
58 uint16_t nfc_config2;
59};
60
61/*
62 * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
63 * for Command operation
64 */
65#define NFC_CMD 0x1
66
67/*
68 * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
69 * for Address operation
70 */
71#define NFC_ADDR 0x2
72
73/*
74 * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
75 * for Input operation
76 */
77#define NFC_INPUT 0x4
78
79/*
80 * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
81 * for Data Output operation
82 */
83#define NFC_OUTPUT 0x8
84
85/*
86 * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
87 * for Read ID operation
88 */
89#define NFC_ID 0x10
90
91/*
92 * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
93 * for Read Status operation
94 */
95#define NFC_STATUS 0x20
96
97/*
98 * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
99 * Status operation
100 */
101#define NFC_INT 0x8000
102
103#define NFC_SP_EN (1 << 2)
104#define NFC_ECC_EN (1 << 3)
105#define NFC_BIG (1 << 5)
106#define NFC_RST (1 << 6)
107#define NFC_CE (1 << 7)
108#define NFC_ONE_CYCLE (1 << 8)
109
110typedef enum {false, true} bool;
111
112struct mxc_nand_host {
113 struct mtd_info mtd;
114 struct nand_chip *nand;
115
116 struct nfc_regs __iomem *regs;
117 int spare_only;
118 int status_request;
119 int pagesize_2k;
120 int clk_act;
121 uint16_t col_addr;
122};
123
124static struct mxc_nand_host mxc_host;
125static struct mxc_nand_host *host = &mxc_host;
126
127/* Define delays in microsec for NAND device operations */
128#define TROP_US_DELAY 2000
129/* Macros to get byte and bit positions of ECC */
130#define COLPOS(x) ((x) >> 3)
131#define BITPOS(x) ((x) & 0xf)
132
133/* Define single bit Error positions in Main & Spare area */
134#define MAIN_SINGLEBIT_ERROR 0x4
135#define SPARE_SINGLEBIT_ERROR 0x1
136
137/* OOB placement block for use with hardware ecc generation */
138#ifdef CONFIG_MXC_NAND_HWECC
139static struct nand_ecclayout nand_hw_eccoob = {
140 .eccbytes = 5,
141 .eccpos = {6, 7, 8, 9, 10},
142 .oobfree = {{0, 5}, {11, 5}, }
143};
144#else
145static struct nand_ecclayout nand_soft_eccoob = {
146 .eccbytes = 6,
147 .eccpos = {6, 7, 8, 9, 10, 11},
148 .oobfree = {{0, 5}, {12, 4}, }
149};
150#endif
151
152static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
153{
154 uint32_t *d = dest;
155
156 size >>= 2;
157 while (size--)
158 __raw_writel(__raw_readl(source++), d++);
159 return dest;
160}
161
162/*
163 * This function polls the NANDFC to wait for the basic operation to
164 * complete by checking the INT bit of config2 register.
165 */
166static void wait_op_done(struct mxc_nand_host *host, int max_retries,
167 uint16_t param)
168{
169 uint32_t tmp;
170
171 while (max_retries-- > 0) {
172 if (readw(&host->regs->nfc_config2) & NFC_INT) {
173 tmp = readw(&host->regs->nfc_config2);
174 tmp &= ~NFC_INT;
175 writew(tmp, &host->regs->nfc_config2);
176 break;
177 }
178 udelay(1);
179 }
180 if (max_retries < 0) {
181 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
182 __func__, param);
183 }
184}
185
186/*
187 * This function issues the specified command to the NAND device and
188 * waits for completion.
189 */
190static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
191{
192 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
193
194 writew(cmd, &host->regs->nfc_flash_cmd);
195 writew(NFC_CMD, &host->regs->nfc_config2);
196
197 /* Wait for operation to complete */
198 wait_op_done(host, TROP_US_DELAY, cmd);
199}
200
201/*
202 * This function sends an address (or partial address) to the
203 * NAND device. The address is used to select the source/destination for
204 * a NAND command.
205 */
206static void send_addr(struct mxc_nand_host *host, uint16_t addr)
207{
208 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
209
210 writew(addr, &host->regs->nfc_flash_addr);
211 writew(NFC_ADDR, &host->regs->nfc_config2);
212
213 /* Wait for operation to complete */
214 wait_op_done(host, TROP_US_DELAY, addr);
215}
216
217/*
218 * This function requests the NANDFC to initate the transfer
219 * of data currently in the NANDFC RAM buffer to the NAND device.
220 */
221static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
222 int spare_only)
223{
224 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
225
226 writew(buf_id, &host->regs->nfc_buf_addr);
227
228 /* Configure spare or page+spare access */
229 if (!host->pagesize_2k) {
230 uint16_t config1 = readw(&host->regs->nfc_config1);
231 if (spare_only)
232 config1 |= NFC_SP_EN;
233 else
234 config1 &= ~(NFC_SP_EN);
235 writew(config1, &host->regs->nfc_config1);
236 }
237
238 writew(NFC_INPUT, &host->regs->nfc_config2);
239
240 /* Wait for operation to complete */
241 wait_op_done(host, TROP_US_DELAY, spare_only);
242}
243
244/*
245 * Requests NANDFC to initated the transfer of data from the
246 * NAND device into in the NANDFC ram buffer.
247 */
248static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
249 int spare_only)
250{
251 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
252
253 writew(buf_id, &host->regs->nfc_buf_addr);
254
255 /* Configure spare or page+spare access */
256 if (!host->pagesize_2k) {
257 uint32_t config1 = readw(&host->regs->nfc_config1);
258 if (spare_only)
259 config1 |= NFC_SP_EN;
260 else
261 config1 &= ~NFC_SP_EN;
262 writew(config1, &host->regs->nfc_config1);
263 }
264
265 writew(NFC_OUTPUT, &host->regs->nfc_config2);
266
267 /* Wait for operation to complete */
268 wait_op_done(host, TROP_US_DELAY, spare_only);
269}
270
271/* Request the NANDFC to perform a read of the NAND device ID. */
272static void send_read_id(struct mxc_nand_host *host)
273{
274 uint16_t tmp;
275
276 /* NANDFC buffer 0 is used for device ID output */
277 writew(0x0, &host->regs->nfc_buf_addr);
278
279 /* Read ID into main buffer */
280 tmp = readw(&host->regs->nfc_config1);
281 tmp &= ~NFC_SP_EN;
282 writew(tmp, &host->regs->nfc_config1);
283
284 writew(NFC_ID, &host->regs->nfc_config2);
285
286 /* Wait for operation to complete */
287 wait_op_done(host, TROP_US_DELAY, 0);
288}
289
290/*
291 * This function requests the NANDFC to perform a read of the
292 * NAND device status and returns the current status.
293 */
294static uint16_t get_dev_status(struct mxc_nand_host *host)
295{
296 void __iomem *main_buf = host->regs->main_area1;
297 uint32_t store;
298 uint16_t ret, tmp;
299 /* Issue status request to NAND device */
300
301 /* store the main area1 first word, later do recovery */
302 store = readl(main_buf);
303 /* NANDFC buffer 1 is used for device status */
304 writew(1, &host->regs->nfc_buf_addr);
305
306 /* Read status into main buffer */
307 tmp = readw(&host->regs->nfc_config1);
308 tmp &= ~NFC_SP_EN;
309 writew(tmp, &host->regs->nfc_config1);
310
311 writew(NFC_STATUS, &host->regs->nfc_config2);
312
313 /* Wait for operation to complete */
314 wait_op_done(host, TROP_US_DELAY, 0);
315
316 /*
317 * Status is placed in first word of main buffer
318 * get status, then recovery area 1 data
319 */
320 ret = readw(main_buf);
321 writel(store, main_buf);
322
323 return ret;
324}
325
326/* This function is used by upper layer to checks if device is ready */
327static int mxc_nand_dev_ready(struct mtd_info *mtd)
328{
329 /*
330 * NFC handles R/B internally. Therefore, this function
331 * always returns status as ready.
332 */
333 return 1;
334}
335
336#ifdef CONFIG_MXC_NAND_HWECC
337static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
338{
339 /*
340 * If HW ECC is enabled, we turn it on during init. There is
341 * no need to enable again here.
342 */
343}
344
345static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
346 u_char *read_ecc, u_char *calc_ecc)
347{
348 struct nand_chip *nand_chip = mtd->priv;
349 struct mxc_nand_host *host = nand_chip->priv;
350
351 /*
352 * 1-Bit errors are automatically corrected in HW. No need for
353 * additional correction. 2-Bit errors cannot be corrected by
354 * HW ECC, so we need to return failure
355 */
356 uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
357
358 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
359 MTDDEBUG(MTD_DEBUG_LEVEL0,
360 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
361 return -1;
362 }
363
364 return 0;
365}
366
367static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
368 u_char *ecc_code)
369{
370 return 0;
371}
372#endif
373
374static u_char mxc_nand_read_byte(struct mtd_info *mtd)
375{
376 struct nand_chip *nand_chip = mtd->priv;
377 struct mxc_nand_host *host = nand_chip->priv;
378 uint8_t ret = 0;
379 uint16_t col;
380 uint16_t __iomem *main_buf =
381 (uint16_t __iomem *)host->regs->main_area0;
382 uint16_t __iomem *spare_buf =
383 (uint16_t __iomem *)host->regs->spare_area0;
384 union {
385 uint16_t word;
386 uint8_t bytes[2];
387 } nfc_word;
388
389 /* Check for status request */
390 if (host->status_request)
391 return get_dev_status(host) & 0xFF;
392
393 /* Get column for 16-bit access */
394 col = host->col_addr >> 1;
395
396 /* If we are accessing the spare region */
397 if (host->spare_only)
398 nfc_word.word = readw(&spare_buf[col]);
399 else
400 nfc_word.word = readw(&main_buf[col]);
401
402 /* Pick upper/lower byte of word from RAM buffer */
403 ret = nfc_word.bytes[host->col_addr & 0x1];
404
405 /* Update saved column address */
406 if (nand_chip->options & NAND_BUSWIDTH_16)
407 host->col_addr += 2;
408 else
409 host->col_addr++;
410
411 return ret;
412}
413
414static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
415{
416 struct nand_chip *nand_chip = mtd->priv;
417 struct mxc_nand_host *host = nand_chip->priv;
418 uint16_t col, ret;
419 uint16_t __iomem *p;
420
421 MTDDEBUG(MTD_DEBUG_LEVEL3,
422 "mxc_nand_read_word(col = %d)\n", host->col_addr);
423
424 col = host->col_addr;
425 /* Adjust saved column address */
426 if (col < mtd->writesize && host->spare_only)
427 col += mtd->writesize;
428
429 if (col < mtd->writesize) {
430 p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
431 } else {
432 p = (uint16_t __iomem *)(host->regs->spare_area0 +
433 ((col - mtd->writesize) >> 1));
434 }
435
436 if (col & 1) {
437 union {
438 uint16_t word;
439 uint8_t bytes[2];
440 } nfc_word[3];
441
442 nfc_word[0].word = readw(p);
443 nfc_word[1].word = readw(p + 1);
444
445 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
446 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
447
448 ret = nfc_word[2].word;
449 } else {
450 ret = readw(p);
451 }
452
453 /* Update saved column address */
454 host->col_addr = col + 2;
455
456 return ret;
457}
458
459/*
460 * Write data of length len to buffer buf. The data to be
461 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
462 * Operation by the NFC, the data is written to NAND Flash
463 */
464static void mxc_nand_write_buf(struct mtd_info *mtd,
465 const u_char *buf, int len)
466{
467 struct nand_chip *nand_chip = mtd->priv;
468 struct mxc_nand_host *host = nand_chip->priv;
469 int n, col, i = 0;
470
471 MTDDEBUG(MTD_DEBUG_LEVEL3,
472 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
473 len);
474
475 col = host->col_addr;
476
477 /* Adjust saved column address */
478 if (col < mtd->writesize && host->spare_only)
479 col += mtd->writesize;
480
481 n = mtd->writesize + mtd->oobsize - col;
482 n = min(len, n);
483
484 MTDDEBUG(MTD_DEBUG_LEVEL3,
485 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
486
487 while (n > 0) {
488 void __iomem *p;
489
490 if (col < mtd->writesize) {
491 p = host->regs->main_area0 + (col & ~3);
492 } else {
493 p = host->regs->spare_area0 -
494 mtd->writesize + (col & ~3);
495 }
496
497 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
498 __LINE__, p);
499
500 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
501 union {
502 uint32_t word;
503 uint8_t bytes[4];
504 } nfc_word;
505
506 nfc_word.word = readl(p);
507 nfc_word.bytes[col & 3] = buf[i++];
508 n--;
509 col++;
510
511 writel(nfc_word.word, p);
512 } else {
513 int m = mtd->writesize - col;
514
515 if (col >= mtd->writesize)
516 m += mtd->oobsize;
517
518 m = min(n, m) & ~3;
519
520 MTDDEBUG(MTD_DEBUG_LEVEL3,
521 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
522 __func__, __LINE__, n, m, i, col);
523
524 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
525 col += m;
526 i += m;
527 n -= m;
528 }
529 }
530 /* Update saved column address */
531 host->col_addr = col;
532}
533
534/*
535 * Read the data buffer from the NAND Flash. To read the data from NAND
536 * Flash first the data output cycle is initiated by the NFC, which copies
537 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
538 */
539static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
540{
541 struct nand_chip *nand_chip = mtd->priv;
542 struct mxc_nand_host *host = nand_chip->priv;
543 int n, col, i = 0;
544
545 MTDDEBUG(MTD_DEBUG_LEVEL3,
546 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
547
548 col = host->col_addr;
549
550 /* Adjust saved column address */
551 if (col < mtd->writesize && host->spare_only)
552 col += mtd->writesize;
553
554 n = mtd->writesize + mtd->oobsize - col;
555 n = min(len, n);
556
557 while (n > 0) {
558 void __iomem *p;
559
560 if (col < mtd->writesize) {
561 p = host->regs->main_area0 + (col & ~3);
562 } else {
563 p = host->regs->spare_area0 -
564 mtd->writesize + (col & ~3);
565 }
566
567 if (((col | (int)&buf[i]) & 3) || n < 4) {
568 union {
569 uint32_t word;
570 uint8_t bytes[4];
571 } nfc_word;
572
573 nfc_word.word = readl(p);
574 buf[i++] = nfc_word.bytes[col & 3];
575 n--;
576 col++;
577 } else {
578 int m = mtd->writesize - col;
579
580 if (col >= mtd->writesize)
581 m += mtd->oobsize;
582
583 m = min(n, m) & ~3;
584 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
585
586 col += m;
587 i += m;
588 n -= m;
589 }
590 }
591 /* Update saved column address */
592 host->col_addr = col;
593}
594
595/*
596 * Used by the upper layer to verify the data in NAND Flash
597 * with the data in the buf.
598 */
599static int mxc_nand_verify_buf(struct mtd_info *mtd,
600 const u_char *buf, int len)
601{
602 u_char tmp[256];
603 uint bsize;
604
605 while (len) {
606 bsize = min(len, 256);
607 mxc_nand_read_buf(mtd, tmp, bsize);
608
609 if (memcmp(buf, tmp, bsize))
610 return 1;
611
612 buf += bsize;
613 len -= bsize;
614 }
615
616 return 0;
617}
618
619/*
620 * This function is used by upper layer for select and
621 * deselect of the NAND chip
622 */
623static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
624{
625 struct nand_chip *nand_chip = mtd->priv;
626 struct mxc_nand_host *host = nand_chip->priv;
627
628 switch (chip) {
629 case -1:
630 /* TODO: Disable the NFC clock */
631 if (host->clk_act)
632 host->clk_act = 0;
633 break;
634 case 0:
635 /* TODO: Enable the NFC clock */
636 if (!host->clk_act)
637 host->clk_act = 1;
638 break;
639
640 default:
641 break;
642 }
643}
644
645/*
646 * Used by the upper layer to write command to NAND Flash for
647 * different operations to be carried out on NAND Flash
648 */
649static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
650 int column, int page_addr)
651{
652 struct nand_chip *nand_chip = mtd->priv;
653 struct mxc_nand_host *host = nand_chip->priv;
654
655 MTDDEBUG(MTD_DEBUG_LEVEL3,
656 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
657 command, column, page_addr);
658
659 /* Reset command state information */
660 host->status_request = false;
661
662 /* Command pre-processing step */
663 switch (command) {
664
665 case NAND_CMD_STATUS:
666 host->col_addr = 0;
667 host->status_request = true;
668 break;
669
670 case NAND_CMD_READ0:
671 host->col_addr = column;
672 host->spare_only = false;
673 break;
674
675 case NAND_CMD_READOOB:
676 host->col_addr = column;
677 host->spare_only = true;
678 if (host->pagesize_2k)
679 command = NAND_CMD_READ0; /* only READ0 is valid */
680 break;
681
682 case NAND_CMD_SEQIN:
683 if (column >= mtd->writesize) {
684 /*
685 * before sending SEQIN command for partial write,
686 * we need read one page out. FSL NFC does not support
687 * partial write. It alway send out 512+ecc+512+ecc ...
688 * for large page nand flash. But for small page nand
689 * flash, it does support SPARE ONLY operation.
690 */
691 if (host->pagesize_2k) {
692 /* call ourself to read a page */
693 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
694 page_addr);
695 }
696
697 host->col_addr = column - mtd->writesize;
698 host->spare_only = true;
699
700 /* Set program pointer to spare region */
701 if (!host->pagesize_2k)
702 send_cmd(host, NAND_CMD_READOOB);
703 } else {
704 host->spare_only = false;
705 host->col_addr = column;
706
707 /* Set program pointer to page start */
708 if (!host->pagesize_2k)
709 send_cmd(host, NAND_CMD_READ0);
710 }
711 break;
712
713 case NAND_CMD_PAGEPROG:
714 send_prog_page(host, 0, host->spare_only);
715
716 if (host->pagesize_2k) {
717 /* data in 4 areas datas */
718 send_prog_page(host, 1, host->spare_only);
719 send_prog_page(host, 2, host->spare_only);
720 send_prog_page(host, 3, host->spare_only);
721 }
722
723 break;
724 }
725
726 /* Write out the command to the device. */
727 send_cmd(host, command);
728
729 /* Write out column address, if necessary */
730 if (column != -1) {
731 /*
732 * MXC NANDFC can only perform full page+spare or
733 * spare-only read/write. When the upper layers
734 * layers perform a read/write buf operation,
735 * we will used the saved column adress to index into
736 * the full page.
737 */
738 send_addr(host, 0);
739 if (host->pagesize_2k)
740 /* another col addr cycle for 2k page */
741 send_addr(host, 0);
742 }
743
744 /* Write out page address, if necessary */
745 if (page_addr != -1) {
746 /* paddr_0 - p_addr_7 */
747 send_addr(host, (page_addr & 0xff));
748
749 if (host->pagesize_2k) {
750 send_addr(host, (page_addr >> 8) & 0xFF);
751 if (mtd->size >= 0x10000000) {
752 /* paddr_8 - paddr_15 */
753 send_addr(host, (page_addr >> 8) & 0xff);
754 send_addr(host, (page_addr >> 16) & 0xff);
755 } else {
756 /* paddr_8 - paddr_15 */
757 send_addr(host, (page_addr >> 8) & 0xff);
758 }
759 } else {
760 /* One more address cycle for higher density devices */
761 if (mtd->size >= 0x4000000) {
762 /* paddr_8 - paddr_15 */
763 send_addr(host, (page_addr >> 8) & 0xff);
764 send_addr(host, (page_addr >> 16) & 0xff);
765 } else {
766 /* paddr_8 - paddr_15 */
767 send_addr(host, (page_addr >> 8) & 0xff);
768 }
769 }
770 }
771
772 /* Command post-processing step */
773 switch (command) {
774
775 case NAND_CMD_RESET:
776 break;
777
778 case NAND_CMD_READOOB:
779 case NAND_CMD_READ0:
780 if (host->pagesize_2k) {
781 /* send read confirm command */
782 send_cmd(host, NAND_CMD_READSTART);
783 /* read for each AREA */
784 send_read_page(host, 0, host->spare_only);
785 send_read_page(host, 1, host->spare_only);
786 send_read_page(host, 2, host->spare_only);
787 send_read_page(host, 3, host->spare_only);
788 } else {
789 send_read_page(host, 0, host->spare_only);
790 }
791 break;
792
793 case NAND_CMD_READID:
794 host->col_addr = 0;
795 send_read_id(host);
796 break;
797
798 case NAND_CMD_PAGEPROG:
799 break;
800
801 case NAND_CMD_STATUS:
802 break;
803
804 case NAND_CMD_ERASE2:
805 break;
806 }
807}
808
809int board_nand_init(struct nand_chip *this)
810{
811 struct system_control_regs *sc_regs =
812 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
813 struct mtd_info *mtd;
814 uint16_t tmp;
815 int err = 0;
816
817 /* structures must be linked */
818 mtd = &host->mtd;
819 mtd->priv = this;
820 host->nand = this;
821
822 /* 5 us command delay time */
823 this->chip_delay = 5;
824
825 this->priv = host;
826 this->dev_ready = mxc_nand_dev_ready;
827 this->cmdfunc = mxc_nand_command;
828 this->select_chip = mxc_nand_select_chip;
829 this->read_byte = mxc_nand_read_byte;
830 this->read_word = mxc_nand_read_word;
831 this->write_buf = mxc_nand_write_buf;
832 this->read_buf = mxc_nand_read_buf;
833 this->verify_buf = mxc_nand_verify_buf;
834
835 host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
836 host->clk_act = 1;
837
838#ifdef CONFIG_MXC_NAND_HWECC
839 this->ecc.calculate = mxc_nand_calculate_ecc;
840 this->ecc.hwctl = mxc_nand_enable_hwecc;
841 this->ecc.correct = mxc_nand_correct_data;
842 this->ecc.mode = NAND_ECC_HW;
843 this->ecc.size = 512;
844 this->ecc.bytes = 3;
845 this->ecc.layout = &nand_hw_eccoob;
846 tmp = readw(&host->regs->nfc_config1);
847 tmp |= NFC_ECC_EN;
848 writew(tmp, &host->regs->nfc_config1);
849#else
850 this->ecc.layout = &nand_soft_eccoob;
851 this->ecc.mode = NAND_ECC_SOFT;
852 tmp = readw(&host->regs->nfc_config1);
853 tmp &= ~NFC_ECC_EN;
854 writew(tmp, &host->regs->nfc_config1);
855#endif
856
857 /* Reset NAND */
858 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
859
860 /*
861 * preset operation
862 * Unlock the internal RAM Buffer
863 */
864 writew(0x2, &host->regs->nfc_config);
865
866 /* Blocks to be unlocked */
867 writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
868 writew(0x4000, &host->regs->nfc_unlockend_blkaddr);
869
870 /* Unlock Block Command for given address range */
871 writew(0x4, &host->regs->nfc_wrprot);
872
873 /* NAND bus width determines access funtions used by upper layer */
874 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
875 this->options |= NAND_BUSWIDTH_16;
876
877 host->pagesize_2k = 0;
878
879 return err;
880}