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Ilya Yanok36fab992009-08-11 02:32:54 +04001/*
Scott Woodcfcbf8c2009-09-02 16:45:31 -05002 * Copyright 2004-2007 Freescale Semiconductor, Inc.
Ilya Yanok36fab992009-08-11 02:32:54 +04003 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <common.h>
22#include <nand.h>
23#include <linux/err.h>
24#include <asm/io.h>
Stefano Babic58c758f2011-01-14 03:35:21 +000025#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
Ilya Yanok36fab992009-08-11 02:32:54 +040026#include <asm/arch/imx-regs.h>
27#endif
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020028#include <fsl_nfc.h>
Ilya Yanok36fab992009-08-11 02:32:54 +040029
30#define DRIVER_NAME "mxc_nand"
31
Ilya Yanok36fab992009-08-11 02:32:54 +040032typedef enum {false, true} bool;
33
34struct mxc_nand_host {
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020035 struct mtd_info mtd;
36 struct nand_chip *nand;
Ilya Yanok36fab992009-08-11 02:32:54 +040037
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +020038 struct fsl_nfc_regs __iomem *regs;
39 int spare_only;
40 int status_request;
41 int pagesize_2k;
42 int clk_act;
43 uint16_t col_addr;
44 unsigned int page_addr;
Ilya Yanok36fab992009-08-11 02:32:54 +040045};
46
47static struct mxc_nand_host mxc_host;
48static struct mxc_nand_host *host = &mxc_host;
49
50/* Define delays in microsec for NAND device operations */
51#define TROP_US_DELAY 2000
52/* Macros to get byte and bit positions of ECC */
53#define COLPOS(x) ((x) >> 3)
54#define BITPOS(x) ((x) & 0xf)
55
56/* Define single bit Error positions in Main & Spare area */
57#define MAIN_SINGLEBIT_ERROR 0x4
58#define SPARE_SINGLEBIT_ERROR 0x1
59
60/* OOB placement block for use with hardware ecc generation */
John Rigbyb081c2e2010-01-26 19:24:18 -070061#if defined(MXC_NFC_V1)
62#ifndef CONFIG_SYS_NAND_LARGEPAGE
Ilya Yanok36fab992009-08-11 02:32:54 +040063static struct nand_ecclayout nand_hw_eccoob = {
64 .eccbytes = 5,
65 .eccpos = {6, 7, 8, 9, 10},
John Rigbyb081c2e2010-01-26 19:24:18 -070066 .oobfree = { {0, 5}, {11, 5}, }
Ilya Yanok36fab992009-08-11 02:32:54 +040067};
68#else
John Rigbyb081c2e2010-01-26 19:24:18 -070069static struct nand_ecclayout nand_hw_eccoob2k = {
70 .eccbytes = 20,
71 .eccpos = {
72 6, 7, 8, 9, 10,
73 22, 23, 24, 25, 26,
74 38, 39, 40, 41, 42,
75 54, 55, 56, 57, 58,
76 },
77 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
Ilya Yanok36fab992009-08-11 02:32:54 +040078};
79#endif
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +020080#elif defined(MXC_NFC_V2_1)
John Rigbyb081c2e2010-01-26 19:24:18 -070081#ifndef CONFIG_SYS_NAND_LARGEPAGE
82static struct nand_ecclayout nand_hw_eccoob = {
83 .eccbytes = 9,
84 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
85 .oobfree = { {2, 5} }
Magnus Liljac4832df2010-01-17 17:46:10 +010086};
John Rigbyb081c2e2010-01-26 19:24:18 -070087#else
88static struct nand_ecclayout nand_hw_eccoob2k = {
89 .eccbytes = 36,
90 .eccpos = {
91 7, 8, 9, 10, 11, 12, 13, 14, 15,
92 23, 24, 25, 26, 27, 28, 29, 30, 31,
93 39, 40, 41, 42, 43, 44, 45, 46, 47,
94 55, 56, 57, 58, 59, 60, 61, 62, 63,
95 },
96 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
97};
98#endif
99#endif
Magnus Liljac4832df2010-01-17 17:46:10 +0100100
Magnus Liljaf6a97482009-11-11 20:18:43 +0100101#ifdef CONFIG_MX27
102static int is_16bit_nand(void)
103{
104 struct system_control_regs *sc_regs =
105 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
106
107 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
108 return 1;
109 else
110 return 0;
111}
112#elif defined(CONFIG_MX31)
113static int is_16bit_nand(void)
114{
115 struct clock_control_regs *sc_regs =
116 (struct clock_control_regs *)CCM_BASE;
117
118 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
119 return 1;
120 else
121 return 0;
122}
Stefano Babic58c758f2011-01-14 03:35:21 +0000123#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
John Rigbyb081c2e2010-01-26 19:24:18 -0700124static int is_16bit_nand(void)
125{
Benoît Thébaudeau365b2c02012-08-13 22:48:26 +0200126 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
John Rigbyb081c2e2010-01-26 19:24:18 -0700127
128 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
129 return 1;
130 else
131 return 0;
132}
Magnus Liljaf6a97482009-11-11 20:18:43 +0100133#else
134#warning "8/16 bit NAND autodetection not supported"
135static int is_16bit_nand(void)
136{
137 return 0;
138}
139#endif
140
Ilya Yanok36fab992009-08-11 02:32:54 +0400141static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
142{
143 uint32_t *d = dest;
144
145 size >>= 2;
146 while (size--)
147 __raw_writel(__raw_readl(source++), d++);
148 return dest;
149}
150
151/*
152 * This function polls the NANDFC to wait for the basic operation to
153 * complete by checking the INT bit of config2 register.
154 */
155static void wait_op_done(struct mxc_nand_host *host, int max_retries,
156 uint16_t param)
157{
158 uint32_t tmp;
159
160 while (max_retries-- > 0) {
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200161 if (readw(&host->regs->config2) & NFC_INT) {
162 tmp = readw(&host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400163 tmp &= ~NFC_INT;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200164 writew(tmp, &host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400165 break;
166 }
167 udelay(1);
168 }
169 if (max_retries < 0) {
170 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
171 __func__, param);
172 }
173}
174
175/*
176 * This function issues the specified command to the NAND device and
177 * waits for completion.
178 */
179static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
180{
181 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
182
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200183 writew(cmd, &host->regs->flash_cmd);
184 writew(NFC_CMD, &host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400185
186 /* Wait for operation to complete */
187 wait_op_done(host, TROP_US_DELAY, cmd);
188}
189
190/*
191 * This function sends an address (or partial address) to the
192 * NAND device. The address is used to select the source/destination for
193 * a NAND command.
194 */
195static void send_addr(struct mxc_nand_host *host, uint16_t addr)
196{
197 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
198
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200199 writew(addr, &host->regs->flash_addr);
200 writew(NFC_ADDR, &host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400201
202 /* Wait for operation to complete */
203 wait_op_done(host, TROP_US_DELAY, addr);
204}
205
206/*
Helmut Raiger780f30b2011-07-06 09:40:28 +0200207 * This function requests the NANDFC to initiate the transfer
Ilya Yanok36fab992009-08-11 02:32:54 +0400208 * of data currently in the NANDFC RAM buffer to the NAND device.
209 */
210static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
211 int spare_only)
212{
John Rigbyb081c2e2010-01-26 19:24:18 -0700213 if (spare_only)
214 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
215
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +0200216 if (is_mxc_nfc_21()) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700217 int i;
218 /*
219 * The controller copies the 64 bytes of spare data from
220 * the first 16 bytes of each of the 4 64 byte spare buffers.
221 * Copy the contiguous data starting in spare_area[0] to
222 * the four spare area buffers.
223 */
224 for (i = 1; i < 4; i++) {
225 void __iomem *src = &host->regs->spare_area[0][i * 16];
226 void __iomem *dst = &host->regs->spare_area[i][0];
227
228 mxc_nand_memcpy32(dst, src, 16);
229 }
230 }
Ilya Yanok36fab992009-08-11 02:32:54 +0400231
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200232 writew(buf_id, &host->regs->buf_addr);
Ilya Yanok36fab992009-08-11 02:32:54 +0400233
234 /* Configure spare or page+spare access */
235 if (!host->pagesize_2k) {
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200236 uint16_t config1 = readw(&host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400237 if (spare_only)
238 config1 |= NFC_SP_EN;
239 else
Benoît Thébaudeau365b2c02012-08-13 22:48:26 +0200240 config1 &= ~NFC_SP_EN;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200241 writew(config1, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400242 }
243
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200244 writew(NFC_INPUT, &host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400245
246 /* Wait for operation to complete */
247 wait_op_done(host, TROP_US_DELAY, spare_only);
248}
249
250/*
Helmut Raiger780f30b2011-07-06 09:40:28 +0200251 * Requests NANDFC to initiate the transfer of data from the
Ilya Yanok36fab992009-08-11 02:32:54 +0400252 * NAND device into in the NANDFC ram buffer.
253 */
254static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
255 int spare_only)
256{
257 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
258
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200259 writew(buf_id, &host->regs->buf_addr);
Ilya Yanok36fab992009-08-11 02:32:54 +0400260
261 /* Configure spare or page+spare access */
262 if (!host->pagesize_2k) {
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200263 uint32_t config1 = readw(&host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400264 if (spare_only)
265 config1 |= NFC_SP_EN;
266 else
267 config1 &= ~NFC_SP_EN;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200268 writew(config1, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400269 }
270
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200271 writew(NFC_OUTPUT, &host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400272
273 /* Wait for operation to complete */
274 wait_op_done(host, TROP_US_DELAY, spare_only);
John Rigbyb081c2e2010-01-26 19:24:18 -0700275
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +0200276 if (is_mxc_nfc_21()) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700277 int i;
278
279 /*
280 * The controller copies the 64 bytes of spare data to
281 * the first 16 bytes of each of the 4 spare buffers.
282 * Make the data contiguous starting in spare_area[0].
283 */
284 for (i = 1; i < 4; i++) {
285 void __iomem *src = &host->regs->spare_area[i][0];
286 void __iomem *dst = &host->regs->spare_area[0][i * 16];
287
288 mxc_nand_memcpy32(dst, src, 16);
289 }
290 }
Ilya Yanok36fab992009-08-11 02:32:54 +0400291}
292
293/* Request the NANDFC to perform a read of the NAND device ID. */
294static void send_read_id(struct mxc_nand_host *host)
295{
296 uint16_t tmp;
297
298 /* NANDFC buffer 0 is used for device ID output */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200299 writew(0x0, &host->regs->buf_addr);
Ilya Yanok36fab992009-08-11 02:32:54 +0400300
301 /* Read ID into main buffer */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200302 tmp = readw(&host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400303 tmp &= ~NFC_SP_EN;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200304 writew(tmp, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400305
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200306 writew(NFC_ID, &host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400307
308 /* Wait for operation to complete */
309 wait_op_done(host, TROP_US_DELAY, 0);
310}
311
312/*
313 * This function requests the NANDFC to perform a read of the
314 * NAND device status and returns the current status.
315 */
316static uint16_t get_dev_status(struct mxc_nand_host *host)
317{
John Rigbyb081c2e2010-01-26 19:24:18 -0700318 void __iomem *main_buf = host->regs->main_area[1];
Ilya Yanok36fab992009-08-11 02:32:54 +0400319 uint32_t store;
320 uint16_t ret, tmp;
321 /* Issue status request to NAND device */
322
323 /* store the main area1 first word, later do recovery */
324 store = readl(main_buf);
325 /* NANDFC buffer 1 is used for device status */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200326 writew(1, &host->regs->buf_addr);
Ilya Yanok36fab992009-08-11 02:32:54 +0400327
328 /* Read status into main buffer */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200329 tmp = readw(&host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400330 tmp &= ~NFC_SP_EN;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200331 writew(tmp, &host->regs->config1);
Ilya Yanok36fab992009-08-11 02:32:54 +0400332
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200333 writew(NFC_STATUS, &host->regs->config2);
Ilya Yanok36fab992009-08-11 02:32:54 +0400334
335 /* Wait for operation to complete */
336 wait_op_done(host, TROP_US_DELAY, 0);
337
338 /*
339 * Status is placed in first word of main buffer
340 * get status, then recovery area 1 data
341 */
342 ret = readw(main_buf);
343 writel(store, main_buf);
344
345 return ret;
346}
347
348/* This function is used by upper layer to checks if device is ready */
349static int mxc_nand_dev_ready(struct mtd_info *mtd)
350{
351 /*
352 * NFC handles R/B internally. Therefore, this function
353 * always returns status as ready.
354 */
355 return 1;
356}
357
John Rigbyb081c2e2010-01-26 19:24:18 -0700358static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
359{
360 struct nand_chip *nand_chip = mtd->priv;
361 struct mxc_nand_host *host = nand_chip->priv;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200362 uint16_t tmp = readw(&host->regs->config1);
John Rigbyb081c2e2010-01-26 19:24:18 -0700363
364 if (on)
365 tmp |= NFC_ECC_EN;
366 else
367 tmp &= ~NFC_ECC_EN;
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200368 writew(tmp, &host->regs->config1);
John Rigbyb081c2e2010-01-26 19:24:18 -0700369}
370
Benoît Thébaudeau0e499b02012-08-13 22:50:07 +0200371#ifdef CONFIG_MXC_NAND_HWECC
372static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
373{
374 /*
375 * If HW ECC is enabled, we turn it on during init. There is
376 * no need to enable again here.
377 */
378}
379
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +0200380#ifdef MXC_NFC_V2_1
John Rigbyb081c2e2010-01-26 19:24:18 -0700381static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
382 struct nand_chip *chip,
383 int page, int sndcmd)
384{
385 struct mxc_nand_host *host = chip->priv;
386 uint8_t *buf = chip->oob_poi;
387 int length = mtd->oobsize;
388 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
389 uint8_t *bufpoi = buf;
390 int i, toread;
391
392 MTDDEBUG(MTD_DEBUG_LEVEL0,
393 "%s: Reading OOB area of page %u to oob %p\n",
394 __FUNCTION__, host->page_addr, buf);
395
396 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
397 for (i = 0; i < chip->ecc.steps; i++) {
398 toread = min_t(int, length, chip->ecc.prepad);
399 if (toread) {
400 chip->read_buf(mtd, bufpoi, toread);
401 bufpoi += toread;
402 length -= toread;
403 }
404 bufpoi += chip->ecc.bytes;
405 host->col_addr += chip->ecc.bytes;
406 length -= chip->ecc.bytes;
407
408 toread = min_t(int, length, chip->ecc.postpad);
409 if (toread) {
410 chip->read_buf(mtd, bufpoi, toread);
411 bufpoi += toread;
412 length -= toread;
413 }
414 }
415 if (length > 0)
416 chip->read_buf(mtd, bufpoi, length);
417
418 _mxc_nand_enable_hwecc(mtd, 0);
419 chip->cmdfunc(mtd, NAND_CMD_READOOB,
420 mtd->writesize + chip->ecc.prepad, page);
421 bufpoi = buf + chip->ecc.prepad;
422 length = mtd->oobsize - chip->ecc.prepad;
423 for (i = 0; i < chip->ecc.steps; i++) {
424 toread = min_t(int, length, chip->ecc.bytes);
425 chip->read_buf(mtd, bufpoi, toread);
426 bufpoi += eccpitch;
427 length -= eccpitch;
428 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
429 }
430 _mxc_nand_enable_hwecc(mtd, 1);
431 return 1;
432}
433
434static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
435 struct nand_chip *chip,
436 uint8_t *buf,
437 int page)
438{
439 struct mxc_nand_host *host = chip->priv;
440 int eccsize = chip->ecc.size;
441 int eccbytes = chip->ecc.bytes;
442 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
443 uint8_t *oob = chip->oob_poi;
444 int steps, size;
445 int n;
446
447 _mxc_nand_enable_hwecc(mtd, 0);
448 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
449
450 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
451 host->col_addr = n * eccsize;
452 chip->read_buf(mtd, buf, eccsize);
453 buf += eccsize;
454
455 host->col_addr = mtd->writesize + n * eccpitch;
456 if (chip->ecc.prepad) {
457 chip->read_buf(mtd, oob, chip->ecc.prepad);
458 oob += chip->ecc.prepad;
459 }
460
461 chip->read_buf(mtd, oob, eccbytes);
462 oob += eccbytes;
463
464 if (chip->ecc.postpad) {
465 chip->read_buf(mtd, oob, chip->ecc.postpad);
466 oob += chip->ecc.postpad;
467 }
468 }
469
470 size = mtd->oobsize - (oob - chip->oob_poi);
471 if (size)
472 chip->read_buf(mtd, oob, size);
Benoît Thébaudeau7c28a1c2012-08-13 22:50:19 +0200473 _mxc_nand_enable_hwecc(mtd, 1);
John Rigbyb081c2e2010-01-26 19:24:18 -0700474
475 return 0;
476}
477
478static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
479 struct nand_chip *chip,
480 uint8_t *buf,
481 int page)
482{
483 struct mxc_nand_host *host = chip->priv;
484 int n, eccsize = chip->ecc.size;
485 int eccbytes = chip->ecc.bytes;
486 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
487 int eccsteps = chip->ecc.steps;
488 uint8_t *p = buf;
489 uint8_t *oob = chip->oob_poi;
490
491 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
492 host->page_addr, buf, oob);
493
Helmut Raiger780f30b2011-07-06 09:40:28 +0200494 /* first read the data area and the available portion of OOB */
John Rigbyb081c2e2010-01-26 19:24:18 -0700495 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
496 int stat;
497
498 host->col_addr = n * eccsize;
499
500 chip->read_buf(mtd, p, eccsize);
501
502 host->col_addr = mtd->writesize + n * eccpitch;
503
504 if (chip->ecc.prepad) {
505 chip->read_buf(mtd, oob, chip->ecc.prepad);
506 oob += chip->ecc.prepad;
507 }
508
509 stat = chip->ecc.correct(mtd, p, oob, NULL);
510
511 if (stat < 0)
512 mtd->ecc_stats.failed++;
513 else
514 mtd->ecc_stats.corrected += stat;
515 oob += eccbytes;
516
517 if (chip->ecc.postpad) {
518 chip->read_buf(mtd, oob, chip->ecc.postpad);
519 oob += chip->ecc.postpad;
520 }
521 }
522
523 /* Calculate remaining oob bytes */
524 n = mtd->oobsize - (oob - chip->oob_poi);
525 if (n)
526 chip->read_buf(mtd, oob, n);
527
528 /* Then switch ECC off and read the OOB area to get the ECC code */
529 _mxc_nand_enable_hwecc(mtd, 0);
530 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
531 eccsteps = chip->ecc.steps;
532 oob = chip->oob_poi + chip->ecc.prepad;
533 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
534 host->col_addr = mtd->writesize +
535 n * eccpitch +
536 chip->ecc.prepad;
537 chip->read_buf(mtd, oob, eccbytes);
538 oob += eccbytes + chip->ecc.postpad;
539 }
540 _mxc_nand_enable_hwecc(mtd, 1);
541 return 0;
542}
543
544static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
545 struct nand_chip *chip, int page)
546{
547 struct mxc_nand_host *host = chip->priv;
548 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
549 int length = mtd->oobsize;
550 int i, len, status, steps = chip->ecc.steps;
551 const uint8_t *bufpoi = chip->oob_poi;
552
553 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
554 for (i = 0; i < steps; i++) {
555 len = min_t(int, length, eccpitch);
556
557 chip->write_buf(mtd, bufpoi, len);
558 bufpoi += len;
559 length -= len;
560 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
561 }
562 if (length > 0)
563 chip->write_buf(mtd, bufpoi, length);
564
565 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
566 status = chip->waitfunc(mtd, chip);
567 return status & NAND_STATUS_FAIL ? -EIO : 0;
568}
569
570static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
571 struct nand_chip *chip,
572 const uint8_t *buf)
573{
574 struct mxc_nand_host *host = chip->priv;
575 int eccsize = chip->ecc.size;
576 int eccbytes = chip->ecc.bytes;
577 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
578 uint8_t *oob = chip->oob_poi;
579 int steps, size;
580 int n;
581
582 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
583 host->col_addr = n * eccsize;
584 chip->write_buf(mtd, buf, eccsize);
585 buf += eccsize;
586
587 host->col_addr = mtd->writesize + n * eccpitch;
588
589 if (chip->ecc.prepad) {
590 chip->write_buf(mtd, oob, chip->ecc.prepad);
591 oob += chip->ecc.prepad;
592 }
593
594 host->col_addr += eccbytes;
595 oob += eccbytes;
596
597 if (chip->ecc.postpad) {
598 chip->write_buf(mtd, oob, chip->ecc.postpad);
599 oob += chip->ecc.postpad;
600 }
601 }
602
603 size = mtd->oobsize - (oob - chip->oob_poi);
604 if (size)
605 chip->write_buf(mtd, oob, size);
606}
607
608static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
609 struct nand_chip *chip,
610 const uint8_t *buf)
611{
612 struct mxc_nand_host *host = chip->priv;
613 int i, n, eccsize = chip->ecc.size;
614 int eccbytes = chip->ecc.bytes;
615 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
616 int eccsteps = chip->ecc.steps;
617 const uint8_t *p = buf;
618 uint8_t *oob = chip->oob_poi;
619
620 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
621
622 for (i = n = 0;
623 eccsteps;
624 n++, eccsteps--, i += eccbytes, p += eccsize) {
625 host->col_addr = n * eccsize;
626
627 chip->write_buf(mtd, p, eccsize);
628
629 host->col_addr = mtd->writesize + n * eccpitch;
630
631 if (chip->ecc.prepad) {
632 chip->write_buf(mtd, oob, chip->ecc.prepad);
633 oob += chip->ecc.prepad;
634 }
635
636 chip->write_buf(mtd, oob, eccbytes);
637 oob += eccbytes;
638
639 if (chip->ecc.postpad) {
640 chip->write_buf(mtd, oob, chip->ecc.postpad);
641 oob += chip->ecc.postpad;
642 }
643 }
644
645 /* Calculate remaining oob bytes */
646 i = mtd->oobsize - (oob - chip->oob_poi);
647 if (i)
648 chip->write_buf(mtd, oob, i);
649}
650
651static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
652 u_char *read_ecc, u_char *calc_ecc)
653{
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
Benoît Thébaudeauc1db8dd2012-08-13 22:49:42 +0200656 uint32_t ecc_status = readl(&host->regs->ecc_status_result);
John Rigbyb081c2e2010-01-26 19:24:18 -0700657 int subpages = mtd->writesize / nand_chip->subpagesize;
658 int pg2blk_shift = nand_chip->phys_erase_shift -
659 nand_chip->page_shift;
660
661 do {
662 if ((ecc_status & 0xf) > 4) {
663 static int last_bad = -1;
664
665 if (last_bad != host->page_addr >> pg2blk_shift) {
666 last_bad = host->page_addr >> pg2blk_shift;
667 printk(KERN_DEBUG
668 "MXC_NAND: HWECC uncorrectable ECC error"
669 " in block %u page %u subpage %d\n",
670 last_bad, host->page_addr,
671 mtd->writesize / nand_chip->subpagesize
672 - subpages);
673 }
674 return -1;
675 }
676 ecc_status >>= 4;
677 subpages--;
678 } while (subpages > 0);
679
680 return 0;
681}
682#else
683#define mxc_nand_read_page_syndrome NULL
684#define mxc_nand_read_page_raw_syndrome NULL
685#define mxc_nand_read_oob_syndrome NULL
686#define mxc_nand_write_page_syndrome NULL
687#define mxc_nand_write_page_raw_syndrome NULL
688#define mxc_nand_write_oob_syndrome NULL
John Rigbyb081c2e2010-01-26 19:24:18 -0700689
Ilya Yanok36fab992009-08-11 02:32:54 +0400690static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
691 u_char *read_ecc, u_char *calc_ecc)
692{
693 struct nand_chip *nand_chip = mtd->priv;
694 struct mxc_nand_host *host = nand_chip->priv;
695
696 /*
697 * 1-Bit errors are automatically corrected in HW. No need for
698 * additional correction. 2-Bit errors cannot be corrected by
699 * HW ECC, so we need to return failure
700 */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +0200701 uint16_t ecc_status = readw(&host->regs->ecc_status_result);
Ilya Yanok36fab992009-08-11 02:32:54 +0400702
703 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
704 MTDDEBUG(MTD_DEBUG_LEVEL0,
705 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
706 return -1;
707 }
708
709 return 0;
710}
John Rigbyb081c2e2010-01-26 19:24:18 -0700711#endif
712
Ilya Yanok36fab992009-08-11 02:32:54 +0400713static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
714 u_char *ecc_code)
715{
716 return 0;
717}
718#endif
719
720static u_char mxc_nand_read_byte(struct mtd_info *mtd)
721{
722 struct nand_chip *nand_chip = mtd->priv;
723 struct mxc_nand_host *host = nand_chip->priv;
724 uint8_t ret = 0;
725 uint16_t col;
726 uint16_t __iomem *main_buf =
John Rigbyb081c2e2010-01-26 19:24:18 -0700727 (uint16_t __iomem *)host->regs->main_area[0];
Ilya Yanok36fab992009-08-11 02:32:54 +0400728 uint16_t __iomem *spare_buf =
John Rigbyb081c2e2010-01-26 19:24:18 -0700729 (uint16_t __iomem *)host->regs->spare_area[0];
Ilya Yanok36fab992009-08-11 02:32:54 +0400730 union {
731 uint16_t word;
732 uint8_t bytes[2];
733 } nfc_word;
734
735 /* Check for status request */
736 if (host->status_request)
737 return get_dev_status(host) & 0xFF;
738
739 /* Get column for 16-bit access */
740 col = host->col_addr >> 1;
741
742 /* If we are accessing the spare region */
743 if (host->spare_only)
744 nfc_word.word = readw(&spare_buf[col]);
745 else
746 nfc_word.word = readw(&main_buf[col]);
747
748 /* Pick upper/lower byte of word from RAM buffer */
749 ret = nfc_word.bytes[host->col_addr & 0x1];
750
751 /* Update saved column address */
752 if (nand_chip->options & NAND_BUSWIDTH_16)
753 host->col_addr += 2;
754 else
755 host->col_addr++;
756
757 return ret;
758}
759
760static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
761{
762 struct nand_chip *nand_chip = mtd->priv;
763 struct mxc_nand_host *host = nand_chip->priv;
764 uint16_t col, ret;
765 uint16_t __iomem *p;
766
767 MTDDEBUG(MTD_DEBUG_LEVEL3,
768 "mxc_nand_read_word(col = %d)\n", host->col_addr);
769
770 col = host->col_addr;
771 /* Adjust saved column address */
772 if (col < mtd->writesize && host->spare_only)
773 col += mtd->writesize;
774
775 if (col < mtd->writesize) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700776 p = (uint16_t __iomem *)(host->regs->main_area[0] +
777 (col >> 1));
Ilya Yanok36fab992009-08-11 02:32:54 +0400778 } else {
John Rigbyb081c2e2010-01-26 19:24:18 -0700779 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
Ilya Yanok36fab992009-08-11 02:32:54 +0400780 ((col - mtd->writesize) >> 1));
781 }
782
783 if (col & 1) {
784 union {
785 uint16_t word;
786 uint8_t bytes[2];
787 } nfc_word[3];
788
789 nfc_word[0].word = readw(p);
790 nfc_word[1].word = readw(p + 1);
791
792 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
793 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
794
795 ret = nfc_word[2].word;
796 } else {
797 ret = readw(p);
798 }
799
800 /* Update saved column address */
801 host->col_addr = col + 2;
802
803 return ret;
804}
805
806/*
807 * Write data of length len to buffer buf. The data to be
808 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
809 * Operation by the NFC, the data is written to NAND Flash
810 */
811static void mxc_nand_write_buf(struct mtd_info *mtd,
812 const u_char *buf, int len)
813{
814 struct nand_chip *nand_chip = mtd->priv;
815 struct mxc_nand_host *host = nand_chip->priv;
816 int n, col, i = 0;
817
818 MTDDEBUG(MTD_DEBUG_LEVEL3,
819 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
820 len);
821
822 col = host->col_addr;
823
824 /* Adjust saved column address */
825 if (col < mtd->writesize && host->spare_only)
826 col += mtd->writesize;
827
828 n = mtd->writesize + mtd->oobsize - col;
829 n = min(len, n);
830
831 MTDDEBUG(MTD_DEBUG_LEVEL3,
832 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
833
834 while (n > 0) {
835 void __iomem *p;
836
837 if (col < mtd->writesize) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700838 p = host->regs->main_area[0] + (col & ~3);
Ilya Yanok36fab992009-08-11 02:32:54 +0400839 } else {
John Rigbyb081c2e2010-01-26 19:24:18 -0700840 p = host->regs->spare_area[0] -
Ilya Yanok36fab992009-08-11 02:32:54 +0400841 mtd->writesize + (col & ~3);
842 }
843
844 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
845 __LINE__, p);
846
847 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
848 union {
849 uint32_t word;
850 uint8_t bytes[4];
851 } nfc_word;
852
853 nfc_word.word = readl(p);
854 nfc_word.bytes[col & 3] = buf[i++];
855 n--;
856 col++;
857
858 writel(nfc_word.word, p);
859 } else {
860 int m = mtd->writesize - col;
861
862 if (col >= mtd->writesize)
863 m += mtd->oobsize;
864
865 m = min(n, m) & ~3;
866
867 MTDDEBUG(MTD_DEBUG_LEVEL3,
868 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
869 __func__, __LINE__, n, m, i, col);
870
871 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
872 col += m;
873 i += m;
874 n -= m;
875 }
876 }
877 /* Update saved column address */
878 host->col_addr = col;
879}
880
881/*
882 * Read the data buffer from the NAND Flash. To read the data from NAND
883 * Flash first the data output cycle is initiated by the NFC, which copies
884 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
885 */
886static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
887{
888 struct nand_chip *nand_chip = mtd->priv;
889 struct mxc_nand_host *host = nand_chip->priv;
890 int n, col, i = 0;
891
892 MTDDEBUG(MTD_DEBUG_LEVEL3,
893 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
894
895 col = host->col_addr;
896
897 /* Adjust saved column address */
898 if (col < mtd->writesize && host->spare_only)
899 col += mtd->writesize;
900
901 n = mtd->writesize + mtd->oobsize - col;
902 n = min(len, n);
903
904 while (n > 0) {
905 void __iomem *p;
906
907 if (col < mtd->writesize) {
John Rigbyb081c2e2010-01-26 19:24:18 -0700908 p = host->regs->main_area[0] + (col & ~3);
Ilya Yanok36fab992009-08-11 02:32:54 +0400909 } else {
John Rigbyb081c2e2010-01-26 19:24:18 -0700910 p = host->regs->spare_area[0] -
Ilya Yanok36fab992009-08-11 02:32:54 +0400911 mtd->writesize + (col & ~3);
912 }
913
914 if (((col | (int)&buf[i]) & 3) || n < 4) {
915 union {
916 uint32_t word;
917 uint8_t bytes[4];
918 } nfc_word;
919
920 nfc_word.word = readl(p);
921 buf[i++] = nfc_word.bytes[col & 3];
922 n--;
923 col++;
924 } else {
925 int m = mtd->writesize - col;
926
927 if (col >= mtd->writesize)
928 m += mtd->oobsize;
929
930 m = min(n, m) & ~3;
931 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
932
933 col += m;
934 i += m;
935 n -= m;
936 }
937 }
938 /* Update saved column address */
939 host->col_addr = col;
940}
941
942/*
943 * Used by the upper layer to verify the data in NAND Flash
944 * with the data in the buf.
945 */
946static int mxc_nand_verify_buf(struct mtd_info *mtd,
947 const u_char *buf, int len)
948{
949 u_char tmp[256];
950 uint bsize;
951
952 while (len) {
953 bsize = min(len, 256);
954 mxc_nand_read_buf(mtd, tmp, bsize);
955
956 if (memcmp(buf, tmp, bsize))
957 return 1;
958
959 buf += bsize;
960 len -= bsize;
961 }
962
963 return 0;
964}
965
966/*
967 * This function is used by upper layer for select and
968 * deselect of the NAND chip
969 */
970static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
971{
972 struct nand_chip *nand_chip = mtd->priv;
973 struct mxc_nand_host *host = nand_chip->priv;
974
975 switch (chip) {
976 case -1:
977 /* TODO: Disable the NFC clock */
978 if (host->clk_act)
979 host->clk_act = 0;
980 break;
981 case 0:
982 /* TODO: Enable the NFC clock */
983 if (!host->clk_act)
984 host->clk_act = 1;
985 break;
986
987 default:
988 break;
989 }
990}
991
992/*
993 * Used by the upper layer to write command to NAND Flash for
994 * different operations to be carried out on NAND Flash
995 */
John Rigbyb081c2e2010-01-26 19:24:18 -0700996void mxc_nand_command(struct mtd_info *mtd, unsigned command,
Ilya Yanok36fab992009-08-11 02:32:54 +0400997 int column, int page_addr)
998{
999 struct nand_chip *nand_chip = mtd->priv;
1000 struct mxc_nand_host *host = nand_chip->priv;
1001
1002 MTDDEBUG(MTD_DEBUG_LEVEL3,
1003 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1004 command, column, page_addr);
1005
1006 /* Reset command state information */
1007 host->status_request = false;
1008
1009 /* Command pre-processing step */
1010 switch (command) {
1011
1012 case NAND_CMD_STATUS:
1013 host->col_addr = 0;
1014 host->status_request = true;
1015 break;
1016
1017 case NAND_CMD_READ0:
John Rigbyb081c2e2010-01-26 19:24:18 -07001018 host->page_addr = page_addr;
Ilya Yanok36fab992009-08-11 02:32:54 +04001019 host->col_addr = column;
1020 host->spare_only = false;
1021 break;
1022
1023 case NAND_CMD_READOOB:
1024 host->col_addr = column;
1025 host->spare_only = true;
1026 if (host->pagesize_2k)
1027 command = NAND_CMD_READ0; /* only READ0 is valid */
1028 break;
1029
1030 case NAND_CMD_SEQIN:
1031 if (column >= mtd->writesize) {
1032 /*
1033 * before sending SEQIN command for partial write,
1034 * we need read one page out. FSL NFC does not support
Helmut Raiger780f30b2011-07-06 09:40:28 +02001035 * partial write. It always sends out 512+ecc+512+ecc
Ilya Yanok36fab992009-08-11 02:32:54 +04001036 * for large page nand flash. But for small page nand
1037 * flash, it does support SPARE ONLY operation.
1038 */
1039 if (host->pagesize_2k) {
1040 /* call ourself to read a page */
1041 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1042 page_addr);
1043 }
1044
1045 host->col_addr = column - mtd->writesize;
1046 host->spare_only = true;
1047
1048 /* Set program pointer to spare region */
1049 if (!host->pagesize_2k)
1050 send_cmd(host, NAND_CMD_READOOB);
1051 } else {
1052 host->spare_only = false;
1053 host->col_addr = column;
1054
1055 /* Set program pointer to page start */
1056 if (!host->pagesize_2k)
1057 send_cmd(host, NAND_CMD_READ0);
1058 }
1059 break;
1060
1061 case NAND_CMD_PAGEPROG:
1062 send_prog_page(host, 0, host->spare_only);
1063
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +02001064 if (host->pagesize_2k && is_mxc_nfc_1()) {
Helmut Raiger780f30b2011-07-06 09:40:28 +02001065 /* data in 4 areas */
Ilya Yanok36fab992009-08-11 02:32:54 +04001066 send_prog_page(host, 1, host->spare_only);
1067 send_prog_page(host, 2, host->spare_only);
1068 send_prog_page(host, 3, host->spare_only);
1069 }
1070
1071 break;
1072 }
1073
1074 /* Write out the command to the device. */
1075 send_cmd(host, command);
1076
1077 /* Write out column address, if necessary */
1078 if (column != -1) {
1079 /*
1080 * MXC NANDFC can only perform full page+spare or
Helmut Raiger780f30b2011-07-06 09:40:28 +02001081 * spare-only read/write. When the upper layers perform
1082 * a read/write buffer operation, we will use the saved
1083 * column address to index into the full page.
Ilya Yanok36fab992009-08-11 02:32:54 +04001084 */
1085 send_addr(host, 0);
1086 if (host->pagesize_2k)
1087 /* another col addr cycle for 2k page */
1088 send_addr(host, 0);
1089 }
1090
1091 /* Write out page address, if necessary */
1092 if (page_addr != -1) {
John Rigbyb081c2e2010-01-26 19:24:18 -07001093 u32 page_mask = nand_chip->pagemask;
1094 do {
1095 send_addr(host, page_addr & 0xFF);
1096 page_addr >>= 8;
1097 page_mask >>= 8;
1098 } while (page_mask);
Ilya Yanok36fab992009-08-11 02:32:54 +04001099 }
1100
1101 /* Command post-processing step */
1102 switch (command) {
1103
1104 case NAND_CMD_RESET:
1105 break;
1106
1107 case NAND_CMD_READOOB:
1108 case NAND_CMD_READ0:
1109 if (host->pagesize_2k) {
1110 /* send read confirm command */
1111 send_cmd(host, NAND_CMD_READSTART);
1112 /* read for each AREA */
1113 send_read_page(host, 0, host->spare_only);
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +02001114 if (is_mxc_nfc_1()) {
John Rigbyb081c2e2010-01-26 19:24:18 -07001115 send_read_page(host, 1, host->spare_only);
1116 send_read_page(host, 2, host->spare_only);
1117 send_read_page(host, 3, host->spare_only);
1118 }
Ilya Yanok36fab992009-08-11 02:32:54 +04001119 } else {
1120 send_read_page(host, 0, host->spare_only);
1121 }
1122 break;
1123
1124 case NAND_CMD_READID:
1125 host->col_addr = 0;
1126 send_read_id(host);
1127 break;
1128
1129 case NAND_CMD_PAGEPROG:
1130 break;
1131
1132 case NAND_CMD_STATUS:
1133 break;
1134
1135 case NAND_CMD_ERASE2:
1136 break;
1137 }
1138}
1139
Timo Ketolaa1028732012-04-18 22:55:31 +00001140#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1141
1142static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1143static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1144
1145static struct nand_bbt_descr bbt_main_descr = {
1146 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1147 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1148 .offs = 0,
1149 .len = 4,
1150 .veroffs = 4,
1151 .maxblocks = 4,
1152 .pattern = bbt_pattern,
1153};
1154
1155static struct nand_bbt_descr bbt_mirror_descr = {
1156 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1157 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1158 .offs = 0,
1159 .len = 4,
1160 .veroffs = 4,
1161 .maxblocks = 4,
1162 .pattern = mirror_pattern,
1163};
1164
1165#endif
1166
Ilya Yanok36fab992009-08-11 02:32:54 +04001167int board_nand_init(struct nand_chip *this)
1168{
Ilya Yanok36fab992009-08-11 02:32:54 +04001169 struct mtd_info *mtd;
Tom Riniefa1f432012-09-18 09:24:22 -07001170#ifdef MXC_NFC_V2_1
Ilya Yanok36fab992009-08-11 02:32:54 +04001171 uint16_t tmp;
Tom Riniefa1f432012-09-18 09:24:22 -07001172#endif
Ilya Yanok36fab992009-08-11 02:32:54 +04001173
Timo Ketolaa1028732012-04-18 22:55:31 +00001174#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1175 this->options |= NAND_USE_FLASH_BBT;
1176 this->bbt_td = &bbt_main_descr;
1177 this->bbt_md = &bbt_mirror_descr;
1178#endif
1179
Ilya Yanok36fab992009-08-11 02:32:54 +04001180 /* structures must be linked */
1181 mtd = &host->mtd;
1182 mtd->priv = this;
1183 host->nand = this;
1184
1185 /* 5 us command delay time */
1186 this->chip_delay = 5;
1187
1188 this->priv = host;
1189 this->dev_ready = mxc_nand_dev_ready;
1190 this->cmdfunc = mxc_nand_command;
1191 this->select_chip = mxc_nand_select_chip;
1192 this->read_byte = mxc_nand_read_byte;
1193 this->read_word = mxc_nand_read_word;
1194 this->write_buf = mxc_nand_write_buf;
1195 this->read_buf = mxc_nand_read_buf;
1196 this->verify_buf = mxc_nand_verify_buf;
1197
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +02001198 host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
Ilya Yanok36fab992009-08-11 02:32:54 +04001199 host->clk_act = 1;
1200
1201#ifdef CONFIG_MXC_NAND_HWECC
1202 this->ecc.calculate = mxc_nand_calculate_ecc;
1203 this->ecc.hwctl = mxc_nand_enable_hwecc;
1204 this->ecc.correct = mxc_nand_correct_data;
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +02001205 if (is_mxc_nfc_21()) {
John Rigbyb081c2e2010-01-26 19:24:18 -07001206 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1207 this->ecc.read_page = mxc_nand_read_page_syndrome;
1208 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1209 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1210 this->ecc.write_page = mxc_nand_write_page_syndrome;
1211 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1212 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1213 this->ecc.bytes = 9;
1214 this->ecc.prepad = 7;
1215 } else {
1216 this->ecc.mode = NAND_ECC_HW;
1217 }
1218
1219 host->pagesize_2k = 0;
1220
Ilya Yanok36fab992009-08-11 02:32:54 +04001221 this->ecc.size = 512;
Benoît Thébaudeau0e499b02012-08-13 22:50:07 +02001222 _mxc_nand_enable_hwecc(mtd, 1);
Ilya Yanok36fab992009-08-11 02:32:54 +04001223#else
1224 this->ecc.layout = &nand_soft_eccoob;
1225 this->ecc.mode = NAND_ECC_SOFT;
Benoît Thébaudeau0e499b02012-08-13 22:50:07 +02001226 _mxc_nand_enable_hwecc(mtd, 0);
Ilya Yanok36fab992009-08-11 02:32:54 +04001227#endif
Ilya Yanok36fab992009-08-11 02:32:54 +04001228 /* Reset NAND */
1229 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1230
Benoît Thébaudeau13927f02012-08-13 22:50:30 +02001231 /* NAND bus width determines access functions used by upper layer */
1232 if (is_16bit_nand())
1233 this->options |= NAND_BUSWIDTH_16;
1234
1235#ifdef CONFIG_SYS_NAND_LARGEPAGE
1236 host->pagesize_2k = 1;
1237 this->ecc.layout = &nand_hw_eccoob2k;
1238#else
1239 host->pagesize_2k = 0;
1240 this->ecc.layout = &nand_hw_eccoob;
1241#endif
1242
Benoît Thébaudeau9c60e752012-08-13 22:50:53 +02001243#ifdef MXC_NFC_V2_1
Benoît Thébaudeau13927f02012-08-13 22:50:30 +02001244 tmp = readw(&host->regs->config1);
1245 tmp |= NFC_ONE_CYCLE;
1246 tmp |= NFC_4_8N_ECC;
1247 writew(tmp, &host->regs->config1);
1248 if (host->pagesize_2k)
1249 writew(64/2, &host->regs->spare_area_size);
1250 else
1251 writew(16/2, &host->regs->spare_area_size);
1252#endif
1253
Ilya Yanok36fab992009-08-11 02:32:54 +04001254 /*
1255 * preset operation
1256 * Unlock the internal RAM Buffer
1257 */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +02001258 writew(0x2, &host->regs->config);
Ilya Yanok36fab992009-08-11 02:32:54 +04001259
1260 /* Blocks to be unlocked */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +02001261 writew(0x0, &host->regs->unlockstart_blkaddr);
Helmut Raigerb4b1e762011-07-06 19:04:41 +02001262 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1263 * unlockend_blkaddr, but the magic 0x4000 does not always work
1264 * when writing more than some 32 megabytes (on 2k page nands)
1265 * However 0xFFFF doesn't seem to have this kind
1266 * of limitation (tried it back and forth several times).
1267 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1268 * only, but probably this was not tested there for v1.
1269 * The very same limitation seems to apply to this kernel driver.
1270 * This might be NAND chip specific and the i.MX31 datasheet is
1271 * extremely vague about the semantics of this register.
1272 */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +02001273 writew(0xFFFF, &host->regs->unlockend_blkaddr);
Ilya Yanok36fab992009-08-11 02:32:54 +04001274
1275 /* Unlock Block Command for given address range */
Benoît Thébaudeau80c8ab72012-08-13 22:48:12 +02001276 writew(0x4, &host->regs->wrprot);
Ilya Yanok36fab992009-08-11 02:32:54 +04001277
Benoît Thébaudeau365b2c02012-08-13 22:48:26 +02001278 return 0;
Ilya Yanok36fab992009-08-11 02:32:54 +04001279}