Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 1 | if ARCH_SUNXI |
| 2 | |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 3 | # Note only one of these may be selected at a time! But hidden choices are |
| 4 | # not supported by Kconfig |
| 5 | config SUNXI_GEN_SUN4I |
| 6 | bool |
| 7 | ---help--- |
| 8 | Select this for sunxi SoCs which have resets and clocks set up |
| 9 | as the original A10 (mach-sun4i). |
| 10 | |
| 11 | config SUNXI_GEN_SUN6I |
| 12 | bool |
| 13 | ---help--- |
| 14 | Select this for sunxi SoCs which have sun6i like periphery, like |
| 15 | separate ahb reset control registers, custom pmic bus, new style |
| 16 | watchdog, etc. |
| 17 | |
| 18 | |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 19 | choice |
| 20 | prompt "Sunxi SoC Variant" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 21 | optional |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 22 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 23 | config MACH_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 24 | bool "sun4i (Allwinner A10)" |
| 25 | select CPU_V7 |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 26 | select SUNXI_GEN_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 27 | select SUPPORT_SPL |
| 28 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 29 | config MACH_SUN5I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 30 | bool "sun5i (Allwinner A13)" |
| 31 | select CPU_V7 |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 32 | select SUNXI_GEN_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 33 | select SUPPORT_SPL |
| 34 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 35 | config MACH_SUN6I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 36 | bool "sun6i (Allwinner A31)" |
| 37 | select CPU_V7 |
Chen-Yu Tsai | cc08ea4 | 2015-05-28 21:25:32 +0800 | [diff] [blame] | 38 | select CPU_V7_HAS_NONSEC |
| 39 | select CPU_V7_HAS_VIRT |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 40 | select SUNXI_GEN_SUN6I |
Hans de Goede | 8c2c9cf | 2014-10-25 20:18:10 +0200 | [diff] [blame] | 41 | select SUPPORT_SPL |
Chen-Yu Tsai | cc08ea4 | 2015-05-28 21:25:32 +0800 | [diff] [blame] | 42 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 43 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 44 | config MACH_SUN7I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 45 | bool "sun7i (Allwinner A20)" |
| 46 | select CPU_V7 |
Hans de Goede | ea624e1 | 2014-11-14 09:34:30 +0100 | [diff] [blame] | 47 | select CPU_V7_HAS_NONSEC |
| 48 | select CPU_V7_HAS_VIRT |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 49 | select SUNXI_GEN_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 50 | select SUPPORT_SPL |
Hans de Goede | b366fb9 | 2014-10-24 20:12:04 +0200 | [diff] [blame] | 51 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 52 | |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 53 | config MACH_SUN8I_A23 |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 54 | bool "sun8i (Allwinner A23)" |
| 55 | select CPU_V7 |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 56 | select CPU_V7_HAS_NONSEC |
| 57 | select CPU_V7_HAS_VIRT |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 58 | select SUNXI_GEN_SUN6I |
Hans de Goede | 08fd147 | 2014-12-07 14:34:27 +0100 | [diff] [blame] | 59 | select SUPPORT_SPL |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 60 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 61 | |
Vishnu Patekar | 8c3dacf | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 62 | config MACH_SUN8I_A33 |
| 63 | bool "sun8i (Allwinner A33)" |
| 64 | select CPU_V7 |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 65 | select CPU_V7_HAS_NONSEC |
| 66 | select CPU_V7_HAS_VIRT |
Vishnu Patekar | 8c3dacf | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 67 | select SUNXI_GEN_SUN6I |
| 68 | select SUPPORT_SPL |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 69 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Vishnu Patekar | 8c3dacf | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 70 | |
Jens Kuske | 1c27b7d | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 71 | config MACH_SUN8I_H3 |
| 72 | bool "sun8i (Allwinner H3)" |
| 73 | select CPU_V7 |
Chen-Yu Tsai | 853f6d1 | 2016-01-06 15:13:09 +0800 | [diff] [blame] | 74 | select CPU_V7_HAS_NONSEC |
| 75 | select CPU_V7_HAS_VIRT |
Jens Kuske | 1c27b7d | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 76 | select SUNXI_GEN_SUN6I |
Jens Kuske | 0404d53 | 2015-11-17 15:12:59 +0100 | [diff] [blame] | 77 | select SUPPORT_SPL |
Chen-Yu Tsai | 853f6d1 | 2016-01-06 15:13:09 +0800 | [diff] [blame] | 78 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Jens Kuske | 1c27b7d | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 79 | |
vishnupatekar | 762e24a | 2015-11-29 01:07:19 +0800 | [diff] [blame] | 80 | config MACH_SUN8I_A83T |
| 81 | bool "sun8i (Allwinner A83T)" |
| 82 | select CPU_V7 |
| 83 | select SUNXI_GEN_SUN6I |
| 84 | select SUPPORT_SPL |
| 85 | |
Hans de Goede | 1871a8c | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 86 | config MACH_SUN9I |
| 87 | bool "sun9i (Allwinner A80)" |
| 88 | select CPU_V7 |
| 89 | select SUNXI_GEN_SUN6I |
| 90 | |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 91 | endchoice |
Maxime Ripard | 8a6564d | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 92 | |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 93 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
| 94 | config MACH_SUN8I |
| 95 | bool |
vishnupatekar | 762e24a | 2015-11-29 01:07:19 +0800 | [diff] [blame] | 96 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 97 | |
Vishnu Patekar | f5fd8ca | 2016-01-12 01:20:58 +0800 | [diff] [blame] | 98 | config DRAM_TYPE |
| 99 | int "sunxi dram type" |
| 100 | depends on MACH_SUN8I_A83T |
| 101 | default 3 |
| 102 | ---help--- |
| 103 | Set the dram type, 3: DDR3, 7: LPDDR3 |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 104 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 105 | config DRAM_CLK |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 106 | int "sunxi dram clock speed" |
| 107 | default 312 if MACH_SUN6I || MACH_SUN8I |
| 108 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 109 | ---help--- |
| 110 | Set the dram clock speed, valid range 240 - 480, must be a multiple |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 111 | of 24. |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 112 | |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 113 | if MACH_SUN5I || MACH_SUN7I |
| 114 | config DRAM_MBUS_CLK |
| 115 | int "sunxi mbus clock speed" |
| 116 | default 300 |
| 117 | ---help--- |
| 118 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. |
| 119 | |
| 120 | endif |
| 121 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 122 | config DRAM_ZQ |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 123 | int "sunxi dram zq value" |
| 124 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I |
| 125 | default 127 if MACH_SUN7I |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 126 | ---help--- |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 127 | Set the dram zq value. |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 128 | |
Hans de Goede | 8975cdf | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 129 | config DRAM_ODT_EN |
| 130 | bool "sunxi dram odt enable" |
| 131 | default n if !MACH_SUN8I_A23 |
| 132 | default y if MACH_SUN8I_A23 |
| 133 | ---help--- |
| 134 | Select this to enable dram odt (on die termination). |
| 135 | |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 136 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
| 137 | config DRAM_EMR1 |
| 138 | int "sunxi dram emr1 value" |
| 139 | default 0 if MACH_SUN4I |
| 140 | default 4 if MACH_SUN5I || MACH_SUN7I |
| 141 | ---help--- |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 142 | Set the dram controller emr1 value. |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 143 | |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 144 | config DRAM_TPR3 |
| 145 | hex "sunxi dram tpr3 value" |
| 146 | default 0 |
| 147 | ---help--- |
| 148 | Set the dram controller tpr3 parameter. This parameter configures |
| 149 | the delay on the command lane and also phase shifts, which are |
| 150 | applied for sampling incoming read data. The default value 0 |
| 151 | means that no phase/delay adjustments are necessary. Properly |
| 152 | configuring this parameter increases reliability at high DRAM |
| 153 | clock speeds. |
| 154 | |
| 155 | config DRAM_DQS_GATING_DELAY |
| 156 | hex "sunxi dram dqs_gating_delay value" |
| 157 | default 0 |
| 158 | ---help--- |
| 159 | Set the dram controller dqs_gating_delay parmeter. Each byte |
| 160 | encodes the DQS gating delay for each byte lane. The delay |
| 161 | granularity is 1/4 cycle. For example, the value 0x05060606 |
| 162 | means that the delay is 5 quarter-cycles for one lane (1.25 |
| 163 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. |
| 164 | The default value 0 means autodetection. The results of hardware |
| 165 | autodetection are not very reliable and depend on the chip |
| 166 | temperature (sometimes producing different results on cold start |
| 167 | and warm reboot). But the accuracy of hardware autodetection |
| 168 | is usually good enough, unless running at really high DRAM |
| 169 | clocks speeds (up to 600MHz). If unsure, keep as 0. |
| 170 | |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 171 | choice |
| 172 | prompt "sunxi dram timings" |
| 173 | default DRAM_TIMINGS_VENDOR_MAGIC |
| 174 | ---help--- |
| 175 | Select the timings of the DDR3 chips. |
| 176 | |
| 177 | config DRAM_TIMINGS_VENDOR_MAGIC |
| 178 | bool "Magic vendor timings from Android" |
| 179 | ---help--- |
| 180 | The same DRAM timings as in the Allwinner boot0 bootloader. |
| 181 | |
| 182 | config DRAM_TIMINGS_DDR3_1066F_1333H |
| 183 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" |
| 184 | ---help--- |
| 185 | Use the timings of the standard JEDEC DDR3-1066F speed bin for |
| 186 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin |
| 187 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips |
| 188 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 |
| 189 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm |
| 190 | that down binning to DDR3-1066F is supported (because DDR3-1066F |
| 191 | uses a bit faster timings than DDR3-1333H). |
| 192 | |
| 193 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J |
| 194 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" |
| 195 | ---help--- |
| 196 | Use the timings of the slowest possible JEDEC speed bin for the |
| 197 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be |
| 198 | DDR3-800E, DDR3-1066G or DDR3-1333J. |
| 199 | |
| 200 | endchoice |
| 201 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 202 | endif |
| 203 | |
Hans de Goede | 8975cdf | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 204 | if MACH_SUN8I_A23 |
| 205 | config DRAM_ODT_CORRECTION |
| 206 | int "sunxi dram odt correction value" |
| 207 | default 0 |
| 208 | ---help--- |
| 209 | Set the dram odt correction value (range -255 - 255). In allwinner |
| 210 | fex files, this option is found in bits 8-15 of the u32 odt_en variable |
| 211 | in the [dram] section. When bit 31 of the odt_en variable is set |
| 212 | then the correction is negative. Usually the value for this is 0. |
| 213 | endif |
| 214 | |
Iain Paton | e71b422 | 2015-03-28 10:26:38 +0000 | [diff] [blame] | 215 | config SYS_CLK_FREQ |
| 216 | default 912000000 if MACH_SUN7I |
| 217 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I |
| 218 | |
Maxime Ripard | 8a6564d | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 219 | config SYS_CONFIG_NAME |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 220 | default "sun4i" if MACH_SUN4I |
| 221 | default "sun5i" if MACH_SUN5I |
| 222 | default "sun6i" if MACH_SUN6I |
| 223 | default "sun7i" if MACH_SUN7I |
| 224 | default "sun8i" if MACH_SUN8I |
Hans de Goede | 1871a8c | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 225 | default "sun9i" if MACH_SUN9I |
Hans de Goede | 6ae66f2 | 2014-08-01 09:28:24 +0200 | [diff] [blame] | 226 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 227 | config SYS_BOARD |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 228 | default "sunxi" |
| 229 | |
| 230 | config SYS_SOC |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 231 | default "sunxi" |
| 232 | |
Siarhei Siamashka | f0ce28e | 2014-12-25 02:34:47 +0200 | [diff] [blame] | 233 | config UART0_PORT_F |
| 234 | bool "UART0 on MicroSD breakout board" |
Siarhei Siamashka | f0ce28e | 2014-12-25 02:34:47 +0200 | [diff] [blame] | 235 | default n |
| 236 | ---help--- |
| 237 | Repurpose the SD card slot for getting access to the UART0 serial |
| 238 | console. Primarily useful only for low level u-boot debugging on |
| 239 | tablets, where normal UART0 is difficult to access and requires |
| 240 | device disassembly and/or soldering. As the SD card can't be used |
| 241 | at the same time, the system can be only booted in the FEL mode. |
| 242 | Only enable this if you really know what you are doing. |
| 243 | |
Hans de Goede | accc9e4 | 2014-10-22 14:56:36 +0200 | [diff] [blame] | 244 | config OLD_SUNXI_KERNEL_COMPAT |
| 245 | boolean "Enable workarounds for booting old kernels" |
| 246 | default n |
| 247 | ---help--- |
| 248 | Set this to enable various workarounds for old kernels, this results in |
| 249 | sub-optimal settings for newer kernels, only enable if needed. |
| 250 | |
Maxime Ripard | 44c7987 | 2015-10-15 22:04:07 +0200 | [diff] [blame] | 251 | config MMC |
| 252 | depends on !UART0_PORT_F |
| 253 | default y if ARCH_SUNXI |
| 254 | |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 255 | config MMC0_CD_PIN |
| 256 | string "Card detect pin for mmc0" |
| 257 | default "" |
| 258 | ---help--- |
| 259 | Set the card detect pin for mmc0, leave empty to not use cd. This |
| 260 | takes a string in the format understood by sunxi_name_to_gpio, e.g. |
| 261 | PH1 for pin 1 of port H. |
| 262 | |
| 263 | config MMC1_CD_PIN |
| 264 | string "Card detect pin for mmc1" |
| 265 | default "" |
| 266 | ---help--- |
| 267 | See MMC0_CD_PIN help text. |
| 268 | |
| 269 | config MMC2_CD_PIN |
| 270 | string "Card detect pin for mmc2" |
| 271 | default "" |
| 272 | ---help--- |
| 273 | See MMC0_CD_PIN help text. |
| 274 | |
| 275 | config MMC3_CD_PIN |
| 276 | string "Card detect pin for mmc3" |
| 277 | default "" |
| 278 | ---help--- |
| 279 | See MMC0_CD_PIN help text. |
| 280 | |
Paul Kocialkowski | 8deacca | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 281 | config MMC1_PINS |
| 282 | string "Pins for mmc1" |
| 283 | default "" |
| 284 | ---help--- |
| 285 | Set the pins used for mmc1, when applicable. This takes a string in the |
| 286 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. |
| 287 | |
| 288 | config MMC2_PINS |
| 289 | string "Pins for mmc2" |
| 290 | default "" |
| 291 | ---help--- |
| 292 | See MMC1_PINS help text. |
| 293 | |
| 294 | config MMC3_PINS |
| 295 | string "Pins for mmc3" |
| 296 | default "" |
| 297 | ---help--- |
| 298 | See MMC1_PINS help text. |
| 299 | |
Hans de Goede | 2ccfac0 | 2014-10-02 20:43:50 +0200 | [diff] [blame] | 300 | config MMC_SUNXI_SLOT_EXTRA |
| 301 | int "mmc extra slot number" |
| 302 | default -1 |
| 303 | ---help--- |
| 304 | sunxi builds always enable mmc0, some boards also have a second sdcard |
| 305 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable |
| 306 | support for this. |
| 307 | |
Hans de Goede | 4458b7a | 2015-01-07 15:26:06 +0100 | [diff] [blame] | 308 | config USB0_VBUS_PIN |
| 309 | string "Vbus enable pin for usb0 (otg)" |
| 310 | default "" |
| 311 | ---help--- |
| 312 | Set the Vbus enable pin for usb0 (otg). This takes a string in the |
| 313 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 314 | |
Hans de Goede | 52defe8 | 2015-02-16 22:13:43 +0100 | [diff] [blame] | 315 | config USB0_VBUS_DET |
| 316 | string "Vbus detect pin for usb0 (otg)" |
Hans de Goede | 52defe8 | 2015-02-16 22:13:43 +0100 | [diff] [blame] | 317 | default "" |
| 318 | ---help--- |
| 319 | Set the Vbus detect pin for usb0 (otg). This takes a string in the |
| 320 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 321 | |
Hans de Goede | 48c06c9 | 2015-06-14 17:29:53 +0200 | [diff] [blame] | 322 | config USB0_ID_DET |
| 323 | string "ID detect pin for usb0 (otg)" |
| 324 | default "" |
| 325 | ---help--- |
| 326 | Set the ID detect pin for usb0 (otg). This takes a string in the |
| 327 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 328 | |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 329 | config USB1_VBUS_PIN |
| 330 | string "Vbus enable pin for usb1 (ehci0)" |
| 331 | default "PH6" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | 76946df | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 332 | default "PH27" if MACH_SUN6I |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 333 | ---help--- |
| 334 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes |
| 335 | a string in the format understood by sunxi_name_to_gpio, e.g. |
| 336 | PH1 for pin 1 of port H. |
| 337 | |
| 338 | config USB2_VBUS_PIN |
| 339 | string "Vbus enable pin for usb2 (ehci1)" |
| 340 | default "PH3" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | 76946df | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 341 | default "PH24" if MACH_SUN6I |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 342 | ---help--- |
| 343 | See USB1_VBUS_PIN help text. |
| 344 | |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 345 | config I2C0_ENABLE |
| 346 | bool "Enable I2C/TWI controller 0" |
| 347 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
| 348 | default n if MACH_SUN6I || MACH_SUN8I |
| 349 | ---help--- |
| 350 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling |
| 351 | its clock and setting up the bus. This is especially useful on devices |
| 352 | with slaves connected to the bus or with pins exposed through e.g. an |
| 353 | expansion port/header. |
| 354 | |
| 355 | config I2C1_ENABLE |
| 356 | bool "Enable I2C/TWI controller 1" |
| 357 | default n |
| 358 | ---help--- |
| 359 | See I2C0_ENABLE help text. |
| 360 | |
| 361 | config I2C2_ENABLE |
| 362 | bool "Enable I2C/TWI controller 2" |
| 363 | default n |
| 364 | ---help--- |
| 365 | See I2C0_ENABLE help text. |
| 366 | |
| 367 | if MACH_SUN6I || MACH_SUN7I |
| 368 | config I2C3_ENABLE |
| 369 | bool "Enable I2C/TWI controller 3" |
| 370 | default n |
| 371 | ---help--- |
| 372 | See I2C0_ENABLE help text. |
| 373 | endif |
| 374 | |
Jelle van der Waa | 0d8382a | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 375 | if SUNXI_GEN_SUN6I |
Jelle van der Waa | 9d08268 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 376 | config R_I2C_ENABLE |
| 377 | bool "Enable the PRCM I2C/TWI controller" |
Jelle van der Waa | 0d8382a | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 378 | # This is used for the pmic on H3 |
| 379 | default y if SY8106A_POWER |
Jelle van der Waa | 9d08268 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 380 | ---help--- |
| 381 | Set this to y to enable the I2C controller which is part of the PRCM. |
Jelle van der Waa | 0d8382a | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 382 | endif |
Jelle van der Waa | 9d08268 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 383 | |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 384 | if MACH_SUN7I |
| 385 | config I2C4_ENABLE |
| 386 | bool "Enable I2C/TWI controller 4" |
| 387 | default n |
| 388 | ---help--- |
| 389 | See I2C0_ENABLE help text. |
| 390 | endif |
| 391 | |
Hans de Goede | 2fcf033 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 392 | config AXP_GPIO |
| 393 | boolean "Enable support for gpio-s on axp PMICs" |
| 394 | default n |
| 395 | ---help--- |
| 396 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. |
| 397 | |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 398 | config VIDEO |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 399 | boolean "Enable graphical uboot console on HDMI, LCD or VGA" |
vishnupatekar | 762e24a | 2015-11-29 01:07:19 +0800 | [diff] [blame] | 400 | depends on !MACH_SUN8I_A83T |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 401 | default y |
| 402 | ---help--- |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 403 | Say Y here to add support for using a cfb console on the HDMI, LCD |
| 404 | or VGA output found on most sunxi devices. See doc/README.video for |
| 405 | info on how to select the video output and mode. |
| 406 | |
Hans de Goede | 2fbf091 | 2014-12-23 23:04:35 +0100 | [diff] [blame] | 407 | config VIDEO_HDMI |
| 408 | boolean "HDMI output support" |
| 409 | depends on VIDEO && !MACH_SUN8I |
| 410 | default y |
| 411 | ---help--- |
| 412 | Say Y here to add support for outputting video over HDMI. |
| 413 | |
Hans de Goede | d9786d2 | 2014-12-25 13:58:06 +0100 | [diff] [blame] | 414 | config VIDEO_VGA |
| 415 | boolean "VGA output support" |
| 416 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
| 417 | default n |
| 418 | ---help--- |
| 419 | Say Y here to add support for outputting video over VGA. |
| 420 | |
Hans de Goede | e2bbdfb | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 421 | config VIDEO_VGA_VIA_LCD |
| 422 | boolean "VGA via LCD controller support" |
Chen-Yu Tsai | 2583d5b | 2015-01-12 18:02:10 +0800 | [diff] [blame] | 423 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
Hans de Goede | e2bbdfb | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 424 | default n |
| 425 | ---help--- |
| 426 | Say Y here to add support for external DACs connected to the parallel |
| 427 | LCD interface driving a VGA connector, such as found on the |
| 428 | Olimex A13 boards. |
| 429 | |
Hans de Goede | fb75d97 | 2015-01-25 15:33:07 +0100 | [diff] [blame] | 430 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
| 431 | boolean "Force sync active high for VGA via LCD controller support" |
| 432 | depends on VIDEO_VGA_VIA_LCD |
| 433 | default n |
| 434 | ---help--- |
| 435 | Say Y here if you've a board which uses opendrain drivers for the vga |
| 436 | hsync and vsync signals. Opendrain drivers cannot generate steep enough |
| 437 | positive edges for a stable video output, so on boards with opendrain |
| 438 | drivers the sync signals must always be active high. |
| 439 | |
Chen-Yu Tsai | 507e27d | 2015-01-12 18:02:11 +0800 | [diff] [blame] | 440 | config VIDEO_VGA_EXTERNAL_DAC_EN |
| 441 | string "LCD panel power enable pin" |
| 442 | depends on VIDEO_VGA_VIA_LCD |
| 443 | default "" |
| 444 | ---help--- |
| 445 | Set the enable pin for the external VGA DAC. This takes a string in the |
| 446 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 447 | |
Hans de Goede | 39920c8 | 2015-08-03 19:20:26 +0200 | [diff] [blame] | 448 | config VIDEO_COMPOSITE |
| 449 | boolean "Composite video output support" |
| 450 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
| 451 | default n |
| 452 | ---help--- |
| 453 | Say Y here to add support for outputting composite video. |
| 454 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 455 | config VIDEO_LCD_MODE |
| 456 | string "LCD panel timing details" |
| 457 | depends on VIDEO |
| 458 | default "" |
| 459 | ---help--- |
| 460 | LCD panel timing details string, leave empty if there is no LCD panel. |
| 461 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. |
| 462 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 |
Hans de Goede | 8addd3e | 2015-08-16 11:23:42 +0200 | [diff] [blame] | 463 | Also see: http://linux-sunxi.org/LCD |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 464 | |
Hans de Goede | 6515032 | 2015-01-13 13:21:46 +0100 | [diff] [blame] | 465 | config VIDEO_LCD_DCLK_PHASE |
| 466 | int "LCD panel display clock phase" |
| 467 | depends on VIDEO |
| 468 | default 1 |
| 469 | ---help--- |
| 470 | Select LCD panel display clock phase shift, range 0-3. |
| 471 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 472 | config VIDEO_LCD_POWER |
| 473 | string "LCD panel power enable pin" |
| 474 | depends on VIDEO |
| 475 | default "" |
| 476 | ---help--- |
| 477 | Set the power enable pin for the LCD panel. This takes a string in the |
| 478 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 479 | |
Hans de Goede | 242e3d8 | 2015-02-16 17:26:41 +0100 | [diff] [blame] | 480 | config VIDEO_LCD_RESET |
| 481 | string "LCD panel reset pin" |
| 482 | depends on VIDEO |
| 483 | default "" |
| 484 | ---help--- |
| 485 | Set the reset pin for the LCD panel. This takes a string in the format |
| 486 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 487 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 488 | config VIDEO_LCD_BL_EN |
| 489 | string "LCD panel backlight enable pin" |
| 490 | depends on VIDEO |
| 491 | default "" |
| 492 | ---help--- |
| 493 | Set the backlight enable pin for the LCD panel. This takes a string in the |
| 494 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of |
| 495 | port H. |
| 496 | |
| 497 | config VIDEO_LCD_BL_PWM |
| 498 | string "LCD panel backlight pwm pin" |
| 499 | depends on VIDEO |
| 500 | default "" |
| 501 | ---help--- |
| 502 | Set the backlight pwm pin for the LCD panel. This takes a string in the |
| 503 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 504 | |
Hans de Goede | a7403ae | 2015-01-22 21:02:42 +0100 | [diff] [blame] | 505 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
| 506 | bool "LCD panel backlight pwm is inverted" |
| 507 | depends on VIDEO |
| 508 | default y |
| 509 | ---help--- |
| 510 | Set this if the backlight pwm output is active low. |
| 511 | |
Hans de Goede | 5541008 | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 512 | config VIDEO_LCD_PANEL_I2C |
| 513 | bool "LCD panel needs to be configured via i2c" |
| 514 | depends on VIDEO |
Hans de Goede | 1fc4201 | 2015-03-07 12:00:02 +0100 | [diff] [blame] | 515 | default n |
Hans de Goede | 5541008 | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 516 | ---help--- |
| 517 | Say y here if the LCD panel needs to be configured via i2c. This |
| 518 | will add a bitbang i2c controller using gpios to talk to the LCD. |
| 519 | |
| 520 | config VIDEO_LCD_PANEL_I2C_SDA |
| 521 | string "LCD panel i2c interface SDA pin" |
| 522 | depends on VIDEO_LCD_PANEL_I2C |
| 523 | default "PG12" |
| 524 | ---help--- |
| 525 | Set the SDA pin for the LCD i2c interface. This takes a string in the |
| 526 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 527 | |
| 528 | config VIDEO_LCD_PANEL_I2C_SCL |
| 529 | string "LCD panel i2c interface SCL pin" |
| 530 | depends on VIDEO_LCD_PANEL_I2C |
| 531 | default "PG10" |
| 532 | ---help--- |
| 533 | Set the SCL pin for the LCD i2c interface. This takes a string in the |
| 534 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 535 | |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 536 | |
| 537 | # Note only one of these may be selected at a time! But hidden choices are |
| 538 | # not supported by Kconfig |
| 539 | config VIDEO_LCD_IF_PARALLEL |
| 540 | bool |
| 541 | |
| 542 | config VIDEO_LCD_IF_LVDS |
| 543 | bool |
| 544 | |
| 545 | |
| 546 | choice |
| 547 | prompt "LCD panel support" |
| 548 | depends on VIDEO |
| 549 | ---help--- |
| 550 | Select which type of LCD panel to support. |
| 551 | |
| 552 | config VIDEO_LCD_PANEL_PARALLEL |
| 553 | bool "Generic parallel interface LCD panel" |
| 554 | select VIDEO_LCD_IF_PARALLEL |
| 555 | |
| 556 | config VIDEO_LCD_PANEL_LVDS |
| 557 | bool "Generic lvds interface LCD panel" |
| 558 | select VIDEO_LCD_IF_LVDS |
| 559 | |
Siarhei Siamashka | 97ece83 | 2015-01-19 05:23:33 +0200 | [diff] [blame] | 560 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
| 561 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" |
| 562 | select VIDEO_LCD_SSD2828 |
| 563 | select VIDEO_LCD_IF_PARALLEL |
| 564 | ---help--- |
Hans de Goede | c1cfd51 | 2015-08-08 16:13:53 +0200 | [diff] [blame] | 565 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
| 566 | |
| 567 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 |
| 568 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" |
| 569 | select VIDEO_LCD_ANX9804 |
| 570 | select VIDEO_LCD_IF_PARALLEL |
| 571 | select VIDEO_LCD_PANEL_I2C |
| 572 | ---help--- |
| 573 | Select this for eDP LCD panels with 4 lanes running at 1.62G, |
| 574 | connected via an ANX9804 bridge chip. |
Siarhei Siamashka | 97ece83 | 2015-01-19 05:23:33 +0200 | [diff] [blame] | 575 | |
Hans de Goede | 27515b2 | 2015-01-20 09:23:36 +0100 | [diff] [blame] | 576 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
| 577 | bool "Hitachi tx18d42vm LCD panel" |
| 578 | select VIDEO_LCD_HITACHI_TX18D42VM |
| 579 | select VIDEO_LCD_IF_LVDS |
| 580 | ---help--- |
| 581 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support |
| 582 | |
Hans de Goede | aad2ac2 | 2015-02-16 17:49:47 +0100 | [diff] [blame] | 583 | config VIDEO_LCD_TL059WV5C0 |
| 584 | bool "tl059wv5c0 LCD panel" |
| 585 | select VIDEO_LCD_PANEL_I2C |
| 586 | select VIDEO_LCD_IF_PARALLEL |
| 587 | ---help--- |
| 588 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and |
| 589 | Aigo M60/M608/M606 tablets. |
| 590 | |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 591 | endchoice |
| 592 | |
| 593 | |
Hans de Goede | c13f60d | 2015-01-25 12:10:48 +0100 | [diff] [blame] | 594 | config GMAC_TX_DELAY |
| 595 | int "GMAC Transmit Clock Delay Chain" |
| 596 | default 0 |
| 597 | ---help--- |
| 598 | Set the GMAC Transmit Clock Delay Chain value. |
| 599 | |
Hans de Goede | ff42d10 | 2015-09-13 13:02:48 +0200 | [diff] [blame] | 600 | config SPL_STACK_R_ADDR |
| 601 | default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I |
| 602 | default 0x2fe00000 if MACH_SUN9I |
| 603 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 604 | endif |