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wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Galaa09b9b62010-12-30 12:09:53 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Ed Swarthout29372ff2007-07-27 01:50:47 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#include <common.h>
14#include <watchdog.h>
15#include <asm/processor.h>
16#include <ioports.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050017#include <sata.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050018#include <fm_eth.h>
wdenk42d1f032003-10-15 23:53:47 +000019#include <asm/io.h>
Kumar Galafd3c9be2010-05-05 22:35:27 -050020#include <asm/cache.h>
Kumar Gala87163182008-01-16 22:38:34 -060021#include <asm/mmu.h>
Kumar Gala83d40df2008-01-16 01:13:58 -060022#include <asm/fsl_law.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050023#include <asm/fsl_serdes.h>
Liu Gang5ffa88e2012-03-08 00:33:17 +000024#include <asm/fsl_srio.h>
ramneek mehresh9dee2052013-08-05 16:00:16 +053025#include <fsl_usb.h>
York Sun57125f22012-08-08 18:04:53 +000026#include <hwconfig.h>
Timur Tabifbc20aa2011-11-21 17:10:23 -060027#include <linux/compiler.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060028#include "mp.h"
Timur Tabif2717b42011-11-22 09:21:25 -060029#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -050030#include <nand.h>
31#include <errno.h>
32#endif
wdenk42d1f032003-10-15 23:53:47 +000033
Timur Tabifbc20aa2011-11-21 17:10:23 -060034#include "../../../../drivers/block/fsl_sata.h"
35
Wolfgang Denkd87080b2006-03-31 18:32:53 +020036DECLARE_GLOBAL_DATA_PTR;
37
Andy Flemingda9d4612007-08-14 00:14:25 -050038#ifdef CONFIG_QE
39extern qe_iop_conf_t qe_iop_conf_tab[];
40extern void qe_config_iopin(u8 port, u8 pin, int dir,
41 int open_drain, int assign);
42extern void qe_init(uint qe_base);
43extern void qe_reset(void);
44
45static void config_qe_ioports(void)
46{
47 u8 port, pin;
48 int dir, open_drain, assign;
49 int i;
50
51 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
52 port = qe_iop_conf_tab[i].port;
53 pin = qe_iop_conf_tab[i].pin;
54 dir = qe_iop_conf_tab[i].dir;
55 open_drain = qe_iop_conf_tab[i].open_drain;
56 assign = qe_iop_conf_tab[i].assign;
57 qe_config_iopin(port, pin, dir, open_drain, assign);
58 }
59}
60#endif
Matthew McClintock40d5fa32006-06-28 10:43:36 -050061
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050062#ifdef CONFIG_CPM2
Kumar Galaaafeefb2007-11-28 00:36:33 -060063void config_8560_ioports (volatile ccsr_cpm_t * cpm)
wdenk42d1f032003-10-15 23:53:47 +000064{
65 int portnum;
66
67 for (portnum = 0; portnum < 4; portnum++) {
68 uint pmsk = 0,
69 ppar = 0,
70 psor = 0,
71 pdir = 0,
72 podr = 0,
73 pdat = 0;
74 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
75 iop_conf_t *eiopc = iopc + 32;
76 uint msk = 1;
77
78 /*
79 * NOTE:
80 * index 0 refers to pin 31,
81 * index 31 refers to pin 0
82 */
83 while (iopc < eiopc) {
84 if (iopc->conf) {
85 pmsk |= msk;
86 if (iopc->ppar)
87 ppar |= msk;
88 if (iopc->psor)
89 psor |= msk;
90 if (iopc->pdir)
91 pdir |= msk;
92 if (iopc->podr)
93 podr |= msk;
94 if (iopc->pdat)
95 pdat |= msk;
96 }
97
98 msk <<= 1;
99 iopc++;
100 }
101
102 if (pmsk != 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600103 volatile ioport_t *iop = ioport_addr (cpm, portnum);
wdenk42d1f032003-10-15 23:53:47 +0000104 uint tpmsk = ~pmsk;
105
106 /*
107 * the (somewhat confused) paragraph at the
108 * bottom of page 35-5 warns that there might
109 * be "unknown behaviour" when programming
110 * PSORx and PDIRx, if PPARx = 1, so I
111 * decided this meant I had to disable the
112 * dedicated function first, and enable it
113 * last.
114 */
115 iop->ppar &= tpmsk;
116 iop->psor = (iop->psor & tpmsk) | psor;
117 iop->podr = (iop->podr & tpmsk) | podr;
118 iop->pdat = (iop->pdat & tpmsk) | pdat;
119 iop->pdir = (iop->pdir & tpmsk) | pdir;
120 iop->ppar |= ppar;
121 }
122 }
123}
124#endif
125
Kumar Gala6aba33e2009-03-19 03:40:08 -0500126#ifdef CONFIG_SYS_FSL_CPC
127static void enable_cpc(void)
128{
129 int i;
130 u32 size = 0;
131
132 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
133
134 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
135 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
136 size += CPC_CFG0_SZ_K(cpccfg0);
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800137#ifdef CONFIG_RAMBOOT_PBL
138 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
139 /* find and disable LAW of SRAM */
140 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
141
142 if (law.index == -1) {
143 printf("\nFatal error happened\n");
144 return;
145 }
146 disable_law(law.index);
147
148 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
149 out_be32(&cpc->cpccsr0, 0);
150 out_be32(&cpc->cpcsrcr0, 0);
151 }
152#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500153
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600154#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
155 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
156#endif
Kumar Gala868da592011-01-13 01:56:18 -0600157#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
158 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
159#endif
Scott Wood82125192013-05-15 17:50:13 -0500160#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
161 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
162#endif
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600163
Kumar Gala6aba33e2009-03-19 03:40:08 -0500164 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
165 /* Read back to sync write */
166 in_be32(&cpc->cpccsr0);
167
168 }
169
170 printf("Corenet Platform Cache: %d KB enabled\n", size);
171}
172
Kim Phillipse56143e2012-10-29 13:34:38 +0000173static void invalidate_cpc(void)
Kumar Gala6aba33e2009-03-19 03:40:08 -0500174{
175 int i;
176 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
177
178 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800179 /* skip CPC when it used as all SRAM */
180 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
181 continue;
Kumar Gala6aba33e2009-03-19 03:40:08 -0500182 /* Flash invalidate the CPC and clear all the locks */
183 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
184 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
185 ;
186 }
187}
188#else
189#define enable_cpc()
190#define invalidate_cpc()
191#endif /* CONFIG_SYS_FSL_CPC */
192
wdenk42d1f032003-10-15 23:53:47 +0000193/*
194 * Breathe some life into the CPU...
195 *
196 * Set up the memory map
197 * initialize a bunch of registers
198 */
199
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500200#ifdef CONFIG_FSL_CORENET
201static void corenet_tb_init(void)
202{
203 volatile ccsr_rcpm_t *rcpm =
204 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
205 volatile ccsr_pic_t *pic =
Kim Phillips680c6132010-08-09 18:39:57 -0500206 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500207 u32 whoami = in_be32(&pic->whoami);
208
209 /* Enable the timebase register for this core */
210 out_be32(&rcpm->ctbenrl, (1 << whoami));
211}
212#endif
213
wdenk42d1f032003-10-15 23:53:47 +0000214void cpu_init_f (void)
215{
wdenk42d1f032003-10-15 23:53:47 +0000216 extern void m8560_cpm_reset (void);
Stephen Georgef110fe92011-07-20 09:47:26 -0500217#ifdef CONFIG_SYS_DCSRBAR_PHYS
218 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
219#endif
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000220#if defined(CONFIG_SECURE_BOOT)
221 struct law_entry law;
222#endif
Peter Tysera2cd50e2008-11-11 10:17:10 -0600223#ifdef CONFIG_MPC8548
224 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
225 uint svr = get_svr();
226
227 /*
228 * CPU2 errata workaround: A core hang possible while executing
229 * a msync instruction and a snoopable transaction from an I/O
230 * master tagged to make quick forward progress is present.
231 * Fixed in silicon rev 2.1.
232 */
233 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
234 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
235#endif
wdenk42d1f032003-10-15 23:53:47 +0000236
Kumar Gala87163182008-01-16 22:38:34 -0600237 disable_tlb(14);
238 disable_tlb(15);
239
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000240#if defined(CONFIG_SECURE_BOOT)
241 /* Disable the LAW created for NOR flash by the PBI commands */
242 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
243 if (law.index != -1)
244 disable_law(law.index);
245#endif
246
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500247#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000249#endif
250
Becky Brucef51cdaf2010-06-17 11:37:20 -0500251 init_early_memctl_regs();
wdenk42d1f032003-10-15 23:53:47 +0000252
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500253#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000254 m8560_cpm_reset();
255#endif
Andy Flemingda9d4612007-08-14 00:14:25 -0500256#ifdef CONFIG_QE
257 /* Config QE ioports */
258 config_qe_ioports();
259#endif
Peter Tyser79f43332009-06-30 17:15:47 -0500260#if defined(CONFIG_FSL_DMA)
261 dma_init();
262#endif
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500263#ifdef CONFIG_FSL_CORENET
264 corenet_tb_init();
265#endif
Kumar Gala94e94112009-11-12 10:26:16 -0600266 init_used_tlb_cams();
Kumar Gala6aba33e2009-03-19 03:40:08 -0500267
268 /* Invalidate the CPC before DDR gets enabled */
269 invalidate_cpc();
Stephen Georgef110fe92011-07-20 09:47:26 -0500270
271 #ifdef CONFIG_SYS_DCSRBAR_PHYS
272 /* set DCSRCR so that DCSR space is 1G */
273 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
274 in_be32(&gur->dcsrcr);
275#endif
276
wdenk42d1f032003-10-15 23:53:47 +0000277}
278
Kumar Gala35079aa2010-12-15 03:50:47 -0600279/* Implement a dummy function for those platforms w/o SERDES */
280static void __fsl_serdes__init(void)
281{
282 return ;
283}
284__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500285
York Sun6d2b9da2012-10-08 07:44:08 +0000286#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
287int enable_cluster_l2(void)
288{
289 int i = 0;
290 u32 cluster;
291 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
292 struct ccsr_cluster_l2 __iomem *l2cache;
293
294 cluster = in_be32(&gur->tp_cluster[i].lower);
295 if (cluster & TP_CLUSTER_EOC)
296 return 0;
297
298 /* The first cache has already been set up, so skip it */
299 i++;
300
301 /* Look through the remaining clusters, and set up their caches */
302 do {
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000303 int j, cluster_valid = 0;
304
York Sun6d2b9da2012-10-08 07:44:08 +0000305 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000306
York Sun6d2b9da2012-10-08 07:44:08 +0000307 cluster = in_be32(&gur->tp_cluster[i].lower);
308
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000309 /* check that at least one core/accel is enabled in cluster */
310 for (j = 0; j < 4; j++) {
311 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
312 u32 type = in_be32(&gur->tp_ityp[idx]);
York Sun6d2b9da2012-10-08 07:44:08 +0000313
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000314 if (type & TP_ITYP_AV)
315 cluster_valid = 1;
316 }
York Sun6d2b9da2012-10-08 07:44:08 +0000317
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000318 if (cluster_valid) {
319 /* set stash ID to (cluster) * 2 + 32 + 1 */
320 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
321
322 printf("enable l2 for cluster %d %p\n", i, l2cache);
323
324 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
325 while ((in_be32(&l2cache->l2csr0)
326 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
327 ;
James Yang9cd95ac2013-03-25 07:40:03 +0000328 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
Prabhakar Kushwahadb9a8072012-12-23 19:25:18 +0000329 }
York Sun6d2b9da2012-10-08 07:44:08 +0000330 i++;
331 } while (!(cluster & TP_CLUSTER_EOC));
332
333 return 0;
334}
335#endif
336
wdenk42d1f032003-10-15 23:53:47 +0000337/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500338 * Initialize L2 as cache.
339 *
340 * The newer 8548, etc, parts have twice as much cache, but
341 * use the same bit-encoding as the older 8555, etc, parts.
342 *
wdenk42d1f032003-10-15 23:53:47 +0000343 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500344int cpu_init_r(void)
wdenk42d1f032003-10-15 23:53:47 +0000345{
Timur Tabifbc20aa2011-11-21 17:10:23 -0600346 __maybe_unused u32 svr = get_svr();
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500347#ifdef CONFIG_SYS_LBC_LCRR
York Sun6d2b9da2012-10-08 07:44:08 +0000348 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
349#endif
350#ifdef CONFIG_L2_CACHE
351 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
352#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
353 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500354#endif
York Sunafbfdf52012-11-08 12:33:39 +0000355#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000356 extern int spin_table_compat;
357 const char *spin;
358#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500359
York Sun5e23ab02012-05-07 07:26:47 +0000360#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
361 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
362 /*
York Sun57125f22012-08-08 18:04:53 +0000363 * CPU22 and NMG_CPU_A011 share the same workaround.
York Sun5e23ab02012-05-07 07:26:47 +0000364 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
365 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
York Sun57125f22012-08-08 18:04:53 +0000366 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
367 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
368 * be disabled by hwconfig with syntax:
369 *
370 * fsl_cpu_a011:disable
York Sun5e23ab02012-05-07 07:26:47 +0000371 */
York Sun57125f22012-08-08 18:04:53 +0000372 extern int enable_cpu_a011_workaround;
373#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
374 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
375#else
376 char buffer[HWCONFIG_BUFFER_SIZE];
377 char *buf = NULL;
378 int n, res;
379
380 n = getenv_f("hwconfig", buffer, sizeof(buffer));
381 if (n > 0)
382 buf = buffer;
383
384 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
385 if (res > 0)
386 enable_cpu_a011_workaround = 0;
387 else {
388 if (n >= HWCONFIG_BUFFER_SIZE) {
389 printf("fsl_cpu_a011 was not found. hwconfig variable "
390 "may be too long\n");
391 }
392 enable_cpu_a011_workaround =
393 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
394 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
395 }
396#endif
397 if (enable_cpu_a011_workaround) {
York Sun1e9ea852012-05-07 07:26:45 +0000398 flush_dcache();
399 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
400 sync();
401 }
Kumar Galafd3c9be2010-05-05 22:35:27 -0500402#endif
York Sund217a9a2013-06-25 11:37:49 -0700403#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
404 /*
405 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
406 * in write shadow mode. Checking DCWS before setting SPR 976.
407 */
408 if (mfspr(L1CSR2) & L1CSR2_DCWS)
409 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
410#endif
Kumar Galafd3c9be2010-05-05 22:35:27 -0500411
York Sunafbfdf52012-11-08 12:33:39 +0000412#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
York Sun2a5fcb82012-10-28 08:12:54 +0000413 spin = getenv("spin_table_compat");
414 if (spin && (*spin == 'n'))
415 spin_table_compat = 0;
416 else
417 spin_table_compat = 1;
418#endif
419
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200420 puts ("L2: ");
421
wdenk42d1f032003-10-15 23:53:47 +0000422#if defined(CONFIG_L2_CACHE)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500423 volatile uint cache_ctl;
Timur Tabifbc20aa2011-11-21 17:10:23 -0600424 uint ver;
Kumar Gala73f15a02008-07-14 14:07:00 -0500425 u32 l2siz_field;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500426
Kumar Galaf3e04bd2008-04-08 10:45:50 -0500427 ver = SVR_SOC_VER(svr);
wdenk42d1f032003-10-15 23:53:47 +0000428
429 asm("msync;isync");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500430 cache_ctl = l2cache->l2ctl;
Mingkai Hu7da53352009-09-11 14:19:10 +0800431
432#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
433 if (cache_ctl & MPC85xx_L2CTL_L2E) {
434 /* Clear L2 SRAM memory-mapped base address */
435 out_be32(&l2cache->l2srbar0, 0x0);
436 out_be32(&l2cache->l2srbar1, 0x0);
437
438 /* set MBECCDIS=0, SBECCDIS=0 */
439 clrbits_be32(&l2cache->l2errdis,
440 (MPC85xx_L2ERRDIS_MBECC |
441 MPC85xx_L2ERRDIS_SBECC));
442
443 /* set L2E=0, L2SRAM=0 */
444 clrbits_be32(&l2cache->l2ctl,
445 (MPC85xx_L2CTL_L2E |
446 MPC85xx_L2CTL_L2SRAM_ENTIRE));
447 }
448#endif
449
Kumar Gala73f15a02008-07-14 14:07:00 -0500450 l2siz_field = (cache_ctl >> 28) & 0x3;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500451
Kumar Gala73f15a02008-07-14 14:07:00 -0500452 switch (l2siz_field) {
453 case 0x0:
454 printf(" unknown size (0x%08x)\n", cache_ctl);
455 return -1;
456 break;
457 case 0x1:
458 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500459 ver == SVR_8541 || ver == SVR_8555) {
Kumar Gala73f15a02008-07-14 14:07:00 -0500460 puts("128 KB ");
461 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
462 cache_ctl = 0xc4000000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500463 } else {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200464 puts("256 KB ");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500465 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
466 }
467 break;
Kumar Gala73f15a02008-07-14 14:07:00 -0500468 case 0x2:
469 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500470 ver == SVR_8541 || ver == SVR_8555) {
Kumar Gala73f15a02008-07-14 14:07:00 -0500471 puts("256 KB ");
472 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
473 cache_ctl = 0xc8000000;
474 } else {
475 puts ("512 KB ");
476 /* set L2E=1, L2I=1, & L2SRAM=0 */
477 cache_ctl = 0xc0000000;
478 }
479 break;
480 case 0x3:
481 puts("1024 KB ");
482 /* set L2E=1, L2I=1, & L2SRAM=0 */
483 cache_ctl = 0xc0000000;
484 break;
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500485 }
486
Mingkai Hu76b474e2009-08-18 15:37:15 +0800487 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200488 puts("already enabled");
Haiying Wang888279b2010-12-01 10:35:30 -0500489#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
Kumar Galae4c9a352011-11-09 09:56:41 -0600490 u32 l2srbar = l2cache->l2srbar0;
Mingkai Hu76b474e2009-08-18 15:37:15 +0800491 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
492 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
Ed Swarthout29372ff2007-07-27 01:50:47 -0500494 l2cache->l2srbar0 = l2srbar;
Scott Wood9a511bd2012-10-29 19:00:41 -0500495 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
Ed Swarthout29372ff2007-07-27 01:50:47 -0500496 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#endif /* CONFIG_SYS_INIT_L2_ADDR */
Ed Swarthout29372ff2007-07-27 01:50:47 -0500498 puts("\n");
499 } else {
500 asm("msync;isync");
501 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
502 asm("msync;isync");
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200503 puts("enabled\n");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500504 }
Kumar Gala1b3e4042009-03-19 09:16:10 -0500505#elif defined(CONFIG_BACKSIDE_L2_CACHE)
York Sun48f6a5c2012-07-06 17:10:33 -0500506 if (SVR_SOC_VER(svr) == SVR_P2040) {
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500507 puts("N/A\n");
508 goto skip_l2;
509 }
510
Kumar Gala1b3e4042009-03-19 09:16:10 -0500511 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
512
513 /* invalidate the L2 cache */
Kumar Gala25bacf72009-09-22 15:45:44 -0500514 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
515 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
Kumar Gala1b3e4042009-03-19 09:16:10 -0500516 ;
517
Kumar Gala82fd1f82009-03-19 02:53:01 -0500518#ifdef CONFIG_SYS_CACHE_STASHING
519 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
520 mtspr(SPRN_L2CSR1, (32 + 1));
521#endif
522
Kumar Gala1b3e4042009-03-19 09:16:10 -0500523 /* enable the cache */
524 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
525
Dave Liu654ea1f2009-10-22 00:10:23 -0500526 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
527 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
528 ;
Kumar Gala1b3e4042009-03-19 09:16:10 -0500529 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
Dave Liu654ea1f2009-10-22 00:10:23 -0500530 }
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500531
532skip_l2:
York Sun6d2b9da2012-10-08 07:44:08 +0000533#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
534 if (l2cache->l2csr0 & L2CSR0_L2E)
535 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
536
537 enable_cluster_l2();
wdenk42d1f032003-10-15 23:53:47 +0000538#else
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200539 puts("disabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000540#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500541
542 enable_cpc();
543
York Suncb930712013-06-25 11:37:41 -0700544#ifndef CONFIG_SYS_FSL_NO_SERDES
Kumar Galaaf025062010-05-22 13:21:39 -0500545 /* needs to be in ram since code uses global static vars */
546 fsl_serdes_init();
York Suncb930712013-06-25 11:37:41 -0700547#endif
Kumar Galaaf025062010-05-22 13:21:39 -0500548
Shengzhou Liu72bd83c2013-01-23 19:56:23 +0000549#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
550 if (IS_SVR_REV(svr, 1, 0)) {
551 int i;
552 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
553
554 for (i = 0; i < 12; i++) {
555 p += i + (i > 5 ? 11 : 0);
556 out_be32(p, 0x2);
557 }
558 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
559 out_be32(p, 0x34);
560 }
561#endif
562
Kumar Galaa09b9b62010-12-30 12:09:53 -0600563#ifdef CONFIG_SYS_SRIO
564 srio_init();
Liu Gangc8b28152013-05-07 16:30:46 +0800565#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
Liu Gangff65f122012-08-09 05:09:59 +0000566 char *s = getenv("bootmaster");
567 if (s) {
568 if (!strcmp(s, "SRIO1")) {
569 srio_boot_master(1);
570 srio_boot_master_release_slave(1);
571 }
572 if (!strcmp(s, "SRIO2")) {
573 srio_boot_master(2);
574 srio_boot_master_release_slave(2);
575 }
576 }
Liu Gang5ffa88e2012-03-08 00:33:17 +0000577#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600578#endif
579
Kumar Galaec2b74f2008-01-17 16:48:33 -0600580#if defined(CONFIG_MP)
581 setup_mp();
582#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500583
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000584#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
Roy Zangae026ff2011-01-07 00:24:27 -0600585 {
Zang Roy-R619114e0be342012-09-18 09:50:08 +0000586 if (SVR_MAJ(svr) < 3) {
587 void *p;
588 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
589 setbits_be32(p, 1 << (31 - 14));
590 }
Roy Zangae026ff2011-01-07 00:24:27 -0600591 }
592#endif
593
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500594#ifdef CONFIG_SYS_LBC_LCRR
595 /*
596 * Modify the CLKDIV field of LCRR register to improve the writing
597 * speed for NOR flash.
598 */
599 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
600 __raw_readl(&lbc->lcrr);
601 isync();
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500602#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
603 udelay(100);
604#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500605#endif
606
Roy Zang86221f02011-04-13 00:08:51 -0500607#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
608 {
ramneek mehresh9dee2052013-08-05 16:00:16 +0530609 struct ccsr_usb_phy __iomem *usb_phy1 =
Roy Zang86221f02011-04-13 00:08:51 -0500610 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
611 out_be32(&usb_phy1->usb_enable_override,
612 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
613 }
614#endif
615#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
616 {
ramneek mehresh9dee2052013-08-05 16:00:16 +0530617 struct ccsr_usb_phy __iomem *usb_phy2 =
Roy Zang86221f02011-04-13 00:08:51 -0500618 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
619 out_be32(&usb_phy2->usb_enable_override,
620 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
621 }
622#endif
623
Xulei99d7b0a2013-03-11 17:56:34 +0000624#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
625 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
626 * multi-bit ECC errors which has impact on performance, so software
627 * should disable all ECC reporting from USB1 and USB2.
628 */
629 if (IS_SVR_REV(get_svr(), 1, 0)) {
630 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
631 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
632 setbits_be32(&dcfg->ecccr1,
633 (DCSR_DCFG_ECC_DISABLE_USB1 |
634 DCSR_DCFG_ECC_DISABLE_USB2));
635 }
636#endif
637
Roy Zang3fa75c82013-03-25 07:39:33 +0000638#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
ramneek mehresh9dee2052013-08-05 16:00:16 +0530639 struct ccsr_usb_phy __iomem *usb_phy =
Roy Zang3fa75c82013-03-25 07:39:33 +0000640 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
641 setbits_be32(&usb_phy->pllprg[1],
642 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
643 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
644 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
645 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
646 setbits_be32(&usb_phy->port1.ctrl,
647 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
648 setbits_be32(&usb_phy->port1.drvvbuscfg,
649 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
650 setbits_be32(&usb_phy->port1.pwrfltcfg,
651 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
652 setbits_be32(&usb_phy->port2.ctrl,
653 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
654 setbits_be32(&usb_phy->port2.drvvbuscfg,
655 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
656 setbits_be32(&usb_phy->port2.pwrfltcfg,
657 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
658#endif
659
Kumar Galac916d7c2011-04-13 08:37:44 -0500660#ifdef CONFIG_FMAN_ENET
661 fman_enet_init();
662#endif
663
Timur Tabifbc20aa2011-11-21 17:10:23 -0600664#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
665 /*
666 * For P1022/1013 Rev1.0 silicon, after power on SATA host
667 * controller is configured in legacy mode instead of the
668 * expected enterprise mode. Software needs to clear bit[28]
669 * of HControl register to change to enterprise mode from
670 * legacy mode. We assume that the controller is offline.
671 */
672 if (IS_SVR_REV(svr, 1, 0) &&
673 ((SVR_SOC_VER(svr) == SVR_P1022) ||
York Sun48f6a5c2012-07-06 17:10:33 -0500674 (SVR_SOC_VER(svr) == SVR_P1013))) {
Timur Tabifbc20aa2011-11-21 17:10:23 -0600675 fsl_sata_reg_t *reg;
676
677 /* first SATA controller */
678 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
679 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
680
681 /* second SATA controller */
682 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
683 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
684 }
685#endif
686
687
wdenk42d1f032003-10-15 23:53:47 +0000688 return 0;
689}
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500690
691extern void setup_ivors(void);
692
693void arch_preboot_os(void)
694{
Kumar Gala15fba322009-09-11 15:28:41 -0500695 u32 msr;
696
697 /*
698 * We are changing interrupt offsets and are about to boot the OS so
699 * we need to make sure we disable all async interrupts. EE is already
700 * disabled by the time we get called.
701 */
702 msr = mfmsr();
Prabhakar Kushwaha5344f7a2012-04-29 23:56:30 +0000703 msr &= ~(MSR_ME|MSR_CE);
Kumar Gala15fba322009-09-11 15:28:41 -0500704 mtmsr(msr);
705
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500706 setup_ivors();
707}
Kumar Galaf54fe872010-04-20 10:21:25 -0500708
709#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
710int sata_initialize(void)
711{
712 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
713 return __sata_initialize();
714
715 return 1;
716}
717#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600718
719void cpu_secondary_init_r(void)
720{
721#ifdef CONFIG_QE
722 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
Timur Tabif2717b42011-11-22 09:21:25 -0600723#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500724 int ret;
Timur Tabif2717b42011-11-22 09:21:25 -0600725 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500726
727 /* load QE firmware from NAND flash to DDR first */
Timur Tabif2717b42011-11-22 09:21:25 -0600728 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
729 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500730
731 if (ret && ret == -EUCLEAN) {
732 printf ("NAND read for QE firmware at offset %x failed %d\n",
Timur Tabif2717b42011-11-22 09:21:25 -0600733 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500734 }
735#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600736 qe_init(qe_base);
737 qe_reset();
738#endif
739}