blob: 4683286d7a0af9040b097bbc6d49dde1cf5bb487 [file] [log] [blame]
wdenkd4ca31c2004-01-02 14:00:00 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc178d3d2004-01-24 20:25:54 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkd4ca31c2004-01-02 14:00:00 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
38
wdenk66ca92a2004-09-28 17:59:53 +000039#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
40#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
41#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
42#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
wdenkc178d3d2004-01-24 20:25:54 +000043 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
wdenkd4ca31c2004-01-02 14:00:00 +000045
wdenk75d1ea72004-01-31 20:06:54 +000046#undef CFG_MEASURE_CPUCLK /* Measure real cpu clock */
47 /* (function measure_gclk() */
48 /* will be called) */
49#ifdef CFG_MEASURE_CPUCLK
50#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
51#endif
52
wdenkc178d3d2004-01-24 20:25:54 +000053#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenkd4ca31c2004-01-02 14:00:00 +000054
55#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56
wdenkc178d3d2004-01-24 20:25:54 +000057#define CONFIG_BOOTCOUNT_LIMIT
wdenkd4ca31c2004-01-02 14:00:00 +000058
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61#define CONFIG_BOARD_TYPES 1 /* support board types */
62
wdenkc178d3d2004-01-24 20:25:54 +000063#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010064 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +000065 "echo"
66
67#undef CONFIG_BOOTARGS
68
wdenkc178d3d2004-01-24 20:25:54 +000069#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkd4ca31c2004-01-02 14:00:00 +000070 "netdev=eth0\0" \
71 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010072 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000073 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010074 "addip=setenv bootargs ${bootargs} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
76 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000077 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010078 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000079 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010080 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000082 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020083 "hostname=TQM866M\0" \
84 "bootfile=TQM866M/uImage\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020085 "fdt_addr=400C0000\0" \
86 "kernel_addr=40100000\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020087 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020088 "u-boot=TQM866M/u-image.bin\0" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020089 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020090 "update=prot off 40000000 +${filesize};" \
91 "era 40000000 +${filesize};" \
Martin Krause9ef57bb2007-09-26 17:55:55 +020092 "cp.b 200000 40000000 ${filesize};" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020093 "sete filesize;save\0" \
wdenkd4ca31c2004-01-02 14:00:00 +000094 ""
95#define CONFIG_BOOTCOMMAND "run flash_self"
96
97#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
98#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
99
100#undef CONFIG_WATCHDOG /* watchdog disabled */
101
wdenkc178d3d2004-01-24 20:25:54 +0000102#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenkd4ca31c2004-01-02 14:00:00 +0000103
104#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
105
106/* enable I2C and select the hardware/software driver */
107#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenkc178d3d2004-01-24 20:25:54 +0000108#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenkd4ca31c2004-01-02 14:00:00 +0000109
110#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
111#define CFG_I2C_SLAVE 0xFE
112
113#ifdef CONFIG_SOFT_I2C
114/*
115 * Software (bit-bang) I2C driver configuration
116 */
117#define PB_SCL 0x00000020 /* PB 26 */
118#define PB_SDA 0x00000010 /* PB 27 */
119
120#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
121#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
122#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
123#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
124#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc178d3d2004-01-24 20:25:54 +0000125 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenkd4ca31c2004-01-02 14:00:00 +0000126#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc178d3d2004-01-24 20:25:54 +0000127 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenkd4ca31c2004-01-02 14:00:00 +0000128#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
129#endif /* CONFIG_SOFT_I2C */
130
131#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
wdenkc178d3d2004-01-24 20:25:54 +0000132#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenkd4ca31c2004-01-02 14:00:00 +0000133#define CFG_EEPROM_PAGE_WRITE_BITS 4
134#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
135
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500136/*
137 * BOOTP options
138 */
139#define CONFIG_BOOTP_SUBNETMASK
140#define CONFIG_BOOTP_GATEWAY
141#define CONFIG_BOOTP_HOSTNAME
142#define CONFIG_BOOTP_BOOTPATH
143#define CONFIG_BOOTP_BOOTFILESIZE
144
wdenkd4ca31c2004-01-02 14:00:00 +0000145
146#define CONFIG_MAC_PARTITION
147#define CONFIG_DOS_PARTITION
148
wdenka6cccae2004-02-06 21:48:22 +0000149#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
150
151#define CONFIG_TIMESTAMP /* but print image timestmps */
wdenkd4ca31c2004-01-02 14:00:00 +0000152
wdenkd4ca31c2004-01-02 14:00:00 +0000153
Jon Loeliger26946902007-07-04 22:30:50 -0500154/*
155 * Command line configuration.
156 */
157#include <config_cmd_default.h>
158
159#define CONFIG_CMD_ASKENV
160#define CONFIG_CMD_DHCP
161#define CONFIG_CMD_EEPROM
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200162#define CONFIG_CMD_ELF
Jon Loeliger26946902007-07-04 22:30:50 -0500163#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200164#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500165#define CONFIG_CMD_NFS
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200166#define CONFIG_CMD_SNTP
167
168
169#define CONFIG_NETCONSOLE
Jon Loeliger26946902007-07-04 22:30:50 -0500170
wdenkd4ca31c2004-01-02 14:00:00 +0000171
172/*
173 * Miscellaneous configurable options
174 */
wdenkc178d3d2004-01-24 20:25:54 +0000175#define CFG_LONGHELP /* undef to save memory */
176#define CFG_PROMPT "=> " /* Monitor Command Prompt */
wdenkd4ca31c2004-01-02 14:00:00 +0000177
Wolfgang Denk2751a952006-10-28 02:29:14 +0200178#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
179#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkd4ca31c2004-01-02 14:00:00 +0000180#ifdef CFG_HUSH_PARSER
Wolfgang Denk2751a952006-10-28 02:29:14 +0200181#define CFG_PROMPT_HUSH_PS2 "> "
wdenkd4ca31c2004-01-02 14:00:00 +0000182#endif
183
Jon Loeliger26946902007-07-04 22:30:50 -0500184#if defined(CONFIG_CMD_KGDB)
wdenkc178d3d2004-01-24 20:25:54 +0000185#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000186#else
wdenkc178d3d2004-01-24 20:25:54 +0000187#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd4ca31c2004-01-02 14:00:00 +0000188#endif
wdenkc178d3d2004-01-24 20:25:54 +0000189#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
190#define CFG_MAXARGS 16 /* max number of command args */
wdenkd4ca31c2004-01-02 14:00:00 +0000191#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
192
193#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
194#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
195
wdenkc178d3d2004-01-24 20:25:54 +0000196#define CFG_LOAD_ADDR 0x100000 /* default load address */
wdenkd4ca31c2004-01-02 14:00:00 +0000197
wdenkc178d3d2004-01-24 20:25:54 +0000198#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkd4ca31c2004-01-02 14:00:00 +0000199
200#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
201
202/*
203 * Low Level Configuration Settings
204 * (address mappings, register initial values, etc.)
205 * You should know what you are doing if you make changes here.
206 */
207/*-----------------------------------------------------------------------
208 * Internal Memory Mapped Register
209 */
210#define CFG_IMMR 0xFFF00000
211
212/*-----------------------------------------------------------------------
213 * Definitions for initial stack pointer and data area (in DPRAM)
214 */
215#define CFG_INIT_RAM_ADDR CFG_IMMR
wdenkc178d3d2004-01-24 20:25:54 +0000216#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
217#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
wdenkd4ca31c2004-01-02 14:00:00 +0000218#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc178d3d2004-01-24 20:25:54 +0000219#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkd4ca31c2004-01-02 14:00:00 +0000220
221/*-----------------------------------------------------------------------
222 * Start addresses for the final memory configuration
223 * (Set up by the startup code)
224 * Please note that CFG_SDRAM_BASE _must_ start at 0
225 */
wdenkc178d3d2004-01-24 20:25:54 +0000226#define CFG_SDRAM_BASE 0x00000000
wdenkd4ca31c2004-01-02 14:00:00 +0000227#define CFG_FLASH_BASE 0x40000000
wdenkc178d3d2004-01-24 20:25:54 +0000228#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenkd4ca31c2004-01-02 14:00:00 +0000229#define CFG_MONITOR_BASE CFG_FLASH_BASE
Martin Krause9ef57bb2007-09-26 17:55:55 +0200230#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
wdenkd4ca31c2004-01-02 14:00:00 +0000231
232/*
233 * For booting Linux, the board info and command line data
234 * have to be in the first 8 MB of memory, since this is
235 * the maximum mapped by the Linux kernel during initialization.
236 */
wdenkc178d3d2004-01-24 20:25:54 +0000237#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd4ca31c2004-01-02 14:00:00 +0000238
239/*-----------------------------------------------------------------------
240 * FLASH organization
241 */
Martin Krausee318d9e2007-09-27 11:10:08 +0200242/* use CFI flash driver */
243#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200244#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Martin Krausee318d9e2007-09-27 11:10:08 +0200245#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
246#define CFG_FLASH_EMPTY_INFO
247#define CFG_FLASH_USE_BUFFER_WRITE 1
248#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
249#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkd4ca31c2004-01-02 14:00:00 +0000250
wdenkc178d3d2004-01-24 20:25:54 +0000251#define CFG_ENV_IS_IN_FLASH 1
252#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
253#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
Martin Krause9ef57bb2007-09-26 17:55:55 +0200254#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkd4ca31c2004-01-02 14:00:00 +0000255
256/* Address and size of Redundant Environment Sector */
257#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
258#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
259
Wolfgang Denk67c31032007-09-16 17:10:04 +0200260#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
261
wdenkd4ca31c2004-01-02 14:00:00 +0000262/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200263 * Dynamic MTD partition support
264 */
265#define CONFIG_JFFS2_CMDLINE
266#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
267
268#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
269 "128k(dtb)," \
270 "1920k(kernel)," \
271 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200272 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200273
274/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000275 * Hardware Information Block
276 */
277#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
wdenkc178d3d2004-01-24 20:25:54 +0000278#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
wdenkd4ca31c2004-01-02 14:00:00 +0000279#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
280
281/*-----------------------------------------------------------------------
282 * Cache Configuration
283 */
284#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500285#if defined(CONFIG_CMD_KGDB)
wdenkd4ca31c2004-01-02 14:00:00 +0000286#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
287#endif
288
289/*-----------------------------------------------------------------------
290 * SYPCR - System Protection Control 11-9
291 * SYPCR can only be written once after reset!
292 *-----------------------------------------------------------------------
293 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
294 */
295#if defined(CONFIG_WATCHDOG)
296#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
297 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
298#else
299#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
300#endif
301
302/*-----------------------------------------------------------------------
303 * SIUMCR - SIU Module Configuration 11-6
304 *-----------------------------------------------------------------------
305 * PCMCIA config., multi-function pin tri-state
306 */
wdenkc178d3d2004-01-24 20:25:54 +0000307#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000308#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
309#else /* we must activate GPL5 in the SIUMCR for CAN */
310#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
311#endif /* CONFIG_CAN_DRIVER */
312
313/*-----------------------------------------------------------------------
314 * TBSCR - Time Base Status and Control 11-26
315 *-----------------------------------------------------------------------
316 * Clear Reference Interrupt Status, Timebase freezing enabled
317 */
318#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
319
320/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000321 * PISCR - Periodic Interrupt Status and Control 11-31
322 *-----------------------------------------------------------------------
323 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
324 */
325#define CFG_PISCR (PISCR_PS | PISCR_PITF)
326
327/*-----------------------------------------------------------------------
wdenkd4ca31c2004-01-02 14:00:00 +0000328 * SCCR - System Clock and reset Control Register 15-27
329 *-----------------------------------------------------------------------
330 * Set clock output, timebase and RTC source and divider,
331 * power management and some other internal clocks
332 */
333#define SCCR_MASK SCCR_EBDF11
wdenkc178d3d2004-01-24 20:25:54 +0000334#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd4ca31c2004-01-02 14:00:00 +0000335 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
336 SCCR_DFALCD00)
wdenkd4ca31c2004-01-02 14:00:00 +0000337
338/*-----------------------------------------------------------------------
339 * PCMCIA stuff
340 *-----------------------------------------------------------------------
341 *
342 */
343#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
344#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
345#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
346#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
347#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
348#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
349#define CFG_PCMCIA_IO_ADDR (0xEC000000)
350#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
351
352/*-----------------------------------------------------------------------
353 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
354 *-----------------------------------------------------------------------
355 */
356
wdenkc178d3d2004-01-24 20:25:54 +0000357#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenkd4ca31c2004-01-02 14:00:00 +0000358
wdenkc178d3d2004-01-24 20:25:54 +0000359#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
360#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkd4ca31c2004-01-02 14:00:00 +0000361#undef CONFIG_IDE_RESET /* reset for ide not supported */
362
363#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
364#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
365
366#define CFG_ATA_IDE0_OFFSET 0x0000
367
368#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
369
370/* Offset for data I/O */
371#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
372
373/* Offset for normal register accesses */
374#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
375
376/* Offset for alternate registers */
377#define CFG_ATA_ALT_OFFSET 0x0100
378
379/*-----------------------------------------------------------------------
380 *
381 *-----------------------------------------------------------------------
382 *
383 */
wdenkc178d3d2004-01-24 20:25:54 +0000384#define CFG_DER 0
wdenkd4ca31c2004-01-02 14:00:00 +0000385
386/*
387 * Init Memory Controller:
388 *
389 * BR0/1 and OR0/1 (FLASH)
390 */
391
392#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
393#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
394
395/* used to re-map FLASH both when starting from SRAM or FLASH:
396 * restrict access enough to keep SRAM working (if any)
397 * but not too much to meddle with FLASH accesses
398 */
399#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
400#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
401
402/*
wdenkc178d3d2004-01-24 20:25:54 +0000403 * FLASH timing: Default value of OR0 after reset
wdenkd4ca31c2004-01-02 14:00:00 +0000404 */
wdenkc178d3d2004-01-24 20:25:54 +0000405#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
406 OR_SCY_15_CLK | OR_TRLX)
wdenkd4ca31c2004-01-02 14:00:00 +0000407
408#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
409#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
410#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
411
412#define CFG_OR1_REMAP CFG_OR0_REMAP
413#define CFG_OR1_PRELIM CFG_OR0_PRELIM
414#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
415
416/*
417 * BR2/3 and OR2/3 (SDRAM)
418 *
419 */
420#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
421#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenkc178d3d2004-01-24 20:25:54 +0000422#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
wdenkd4ca31c2004-01-02 14:00:00 +0000423
424/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
425#define CFG_OR_TIMING_SDRAM 0x00000A00
426
427#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
428#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
429
wdenkc178d3d2004-01-24 20:25:54 +0000430#ifndef CONFIG_CAN_DRIVER
431#define CFG_OR3_PRELIM CFG_OR2_PRELIM
wdenkd4ca31c2004-01-02 14:00:00 +0000432#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
433#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
wdenkc178d3d2004-01-24 20:25:54 +0000434#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
wdenkd4ca31c2004-01-02 14:00:00 +0000435#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
436#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
437#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
438 BR_PS_8 | BR_MS_UPMB | BR_V )
439#endif /* CONFIG_CAN_DRIVER */
440
441/*
wdenkc178d3d2004-01-24 20:25:54 +0000442 * 4096 Rows from SDRAM example configuration
443 * 1000 factor s -> ms
444 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
445 * 4 Number of refresh cycles per period
446 * 64 Refresh cycle in ms per number of rows
wdenkd4ca31c2004-01-02 14:00:00 +0000447 */
wdenk66ca92a2004-09-28 17:59:53 +0000448#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
wdenkc178d3d2004-01-24 20:25:54 +0000449
450/*
Martin Kraused43e4892007-09-27 14:54:36 +0200451 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
452 *
453 * CPUclock(MHz) * 31.2
454 * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
455 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
456 *
457 * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
458 * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
459 * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
460 * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
461 *
462 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
463 * be met also in the default configuration, i.e. if environment variable
464 * 'cpuclk' is not set.
wdenkc178d3d2004-01-24 20:25:54 +0000465 */
Martin Kraused43e4892007-09-27 14:54:36 +0200466#define CFG_MAMR_PTA 97
wdenkd4ca31c2004-01-02 14:00:00 +0000467
468/*
Martin Kraused43e4892007-09-27 14:54:36 +0200469 * Memory Periodic Timer Prescaler Register (MPTPR) values.
wdenkd4ca31c2004-01-02 14:00:00 +0000470 */
Martin Kraused43e4892007-09-27 14:54:36 +0200471/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
472#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
473/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
474#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
wdenkd4ca31c2004-01-02 14:00:00 +0000475
476/*
477 * MAMR settings for SDRAM
478 */
479
480/* 8 column SDRAM */
481#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
482 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
483 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
484/* 9 column SDRAM */
485#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
486 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
487 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkc178d3d2004-01-24 20:25:54 +0000488/* 10 column SDRAM */
489#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
490 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
491 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
wdenkd4ca31c2004-01-02 14:00:00 +0000492
493/*
494 * Internal Definitions
495 *
496 * Boot Flags
497 */
wdenkc178d3d2004-01-24 20:25:54 +0000498#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenkd4ca31c2004-01-02 14:00:00 +0000499#define BOOTFLAG_WARM 0x02 /* Software reboot */
500
501#define CONFIG_SCC1_ENET
502#define CONFIG_FEC_ENET
503#define CONFIG_ETHPRIME "SCC ETHERNET"
504
505#endif /* __CONFIG_H */