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Sascha Hauercdace062008-03-26 20:40:49 +01001/*
Marek Vasutdb841402011-09-22 09:22:12 +00002 * i2c driver for Freescale i.MX series
Sascha Hauercdace062008-03-26 20:40:49 +01003 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Marek Vasutdb841402011-09-22 09:22:12 +00005 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
12 *
Sascha Hauercdace062008-03-26 20:40:49 +010013 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Sascha Hauercdace062008-03-26 20:40:49 +010015 */
16
17#include <common.h>
Liu Hui-R64343127cec12011-01-03 22:27:39 +000018#include <asm/arch/clock.h>
Stefano Babic86271112011-03-14 15:43:56 +010019#include <asm/arch/imx-regs.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090020#include <linux/errno.h>
Peng Fan71204e92015-05-15 07:29:12 +080021#include <asm/imx-common/mxc_i2c.h>
Troy Kisky24cd7382012-07-19 08:18:03 +000022#include <asm/io.h>
Marek Vasutbf0783d2011-10-26 00:05:44 +000023#include <i2c.h>
Troy Kisky7aa57a02012-07-19 08:18:09 +000024#include <watchdog.h>
Peng Fan71204e92015-05-15 07:29:12 +080025#include <dm.h>
Peng Fane1bed802016-03-11 16:47:50 +080026#include <dm/pinctrl.h>
Peng Fan71204e92015-05-15 07:29:12 +080027#include <fdtdec.h>
Sascha Hauercdace062008-03-26 20:40:49 +010028
York Sundec18612014-02-10 14:02:52 -080029DECLARE_GLOBAL_DATA_PTR;
30
Peng Fan71204e92015-05-15 07:29:12 +080031#define I2C_QUIRK_FLAG (1 << 0)
32
33#define IMX_I2C_REGSHIFT 2
34#define VF610_I2C_REGSHIFT 0
Yuan Yao9d10c2d2016-06-08 18:24:51 +080035
36#define I2C_EARLY_INIT_INDEX 0
37#ifdef CONFIG_SYS_I2C_IFDR_DIV
38#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
39#else
40#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
41#endif
42
Peng Fan71204e92015-05-15 07:29:12 +080043/* Register index */
44#define IADR 0
45#define IFDR 1
46#define I2CR 2
47#define I2SR 3
48#define I2DR 4
Sascha Hauercdace062008-03-26 20:40:49 +010049
Sascha Hauercdace062008-03-26 20:40:49 +010050#define I2CR_IIEN (1 << 6)
51#define I2CR_MSTA (1 << 5)
52#define I2CR_MTX (1 << 4)
53#define I2CR_TX_NO_AK (1 << 3)
54#define I2CR_RSTA (1 << 2)
55
56#define I2SR_ICF (1 << 7)
57#define I2SR_IBB (1 << 5)
Troy Kiskyd5383a62012-07-19 08:18:15 +000058#define I2SR_IAL (1 << 4)
Sascha Hauercdace062008-03-26 20:40:49 +010059#define I2SR_IIF (1 << 1)
60#define I2SR_RX_NO_AK (1 << 0)
61
Alison Wang30ea41a2013-06-17 15:30:39 +080062#ifdef I2C_QUIRK_REG
63#define I2CR_IEN (0 << 7)
64#define I2CR_IDIS (1 << 7)
65#define I2SR_IIF_CLEAR (1 << 1)
66#else
67#define I2CR_IEN (1 << 7)
68#define I2CR_IDIS (0 << 7)
69#define I2SR_IIF_CLEAR (0 << 1)
70#endif
71
Troy Kiskye4ff5252012-07-19 08:18:18 +000072#if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
Troy Kiskyde6f6042012-04-24 17:33:25 +000073#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
Sascha Hauercdace062008-03-26 20:40:49 +010074#endif
75
Alison Wang30ea41a2013-06-17 15:30:39 +080076#ifdef I2C_QUIRK_REG
77static u16 i2c_clk_div[60][2] = {
78 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
79 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
80 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
81 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
82 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
83 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
84 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
85 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
86 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
87 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
88 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
89 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
90 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
91 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
92 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
93};
94#else
Marek Vasutdb841402011-09-22 09:22:12 +000095static u16 i2c_clk_div[50][2] = {
96 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
97 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
98 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
99 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
100 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
101 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
102 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
103 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
104 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
105 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
106 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
107 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
108 { 3072, 0x1E }, { 3840, 0x1F }
109};
Alison Wang30ea41a2013-06-17 15:30:39 +0800110#endif
Sascha Hauercdace062008-03-26 20:40:49 +0100111
tremfac96402013-09-21 18:13:35 +0200112#ifndef CONFIG_SYS_MXC_I2C1_SPEED
113#define CONFIG_SYS_MXC_I2C1_SPEED 100000
114#endif
115#ifndef CONFIG_SYS_MXC_I2C2_SPEED
116#define CONFIG_SYS_MXC_I2C2_SPEED 100000
117#endif
118#ifndef CONFIG_SYS_MXC_I2C3_SPEED
119#define CONFIG_SYS_MXC_I2C3_SPEED 100000
120#endif
York Sunf8cb1012015-03-20 10:20:40 -0700121#ifndef CONFIG_SYS_MXC_I2C4_SPEED
122#define CONFIG_SYS_MXC_I2C4_SPEED 100000
123#endif
tremfac96402013-09-21 18:13:35 +0200124
125#ifndef CONFIG_SYS_MXC_I2C1_SLAVE
126#define CONFIG_SYS_MXC_I2C1_SLAVE 0
127#endif
128#ifndef CONFIG_SYS_MXC_I2C2_SLAVE
129#define CONFIG_SYS_MXC_I2C2_SLAVE 0
130#endif
131#ifndef CONFIG_SYS_MXC_I2C3_SLAVE
132#define CONFIG_SYS_MXC_I2C3_SLAVE 0
133#endif
York Sunf8cb1012015-03-20 10:20:40 -0700134#ifndef CONFIG_SYS_MXC_I2C4_SLAVE
135#define CONFIG_SYS_MXC_I2C4_SLAVE 0
136#endif
tremfac96402013-09-21 18:13:35 +0200137
Marek Vasutdb841402011-09-22 09:22:12 +0000138/*
139 * Calculate and set proper clock divider
140 */
Peng Fan71204e92015-05-15 07:29:12 +0800141static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000142{
Marek Vasutdb841402011-09-22 09:22:12 +0000143 unsigned int i2c_clk_rate;
144 unsigned int div;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000145 u8 clk_div;
Sascha Hauercdace062008-03-26 20:40:49 +0100146
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000147#if defined(CONFIG_MX31)
Stefano Babic1d549ad2011-01-20 07:50:44 +0000148 struct clock_control_regs *sc_regs =
149 (struct clock_control_regs *)CCM_BASE;
Marek Vasutdb841402011-09-22 09:22:12 +0000150
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100151 /* start the required I2C clock */
Troy Kiskyde6f6042012-04-24 17:33:25 +0000152 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
Stefano Babic1d549ad2011-01-20 07:50:44 +0000153 &sc_regs->cgr0);
Liu Hui-R64343127cec12011-01-03 22:27:39 +0000154#endif
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +0100155
Marek Vasutdb841402011-09-22 09:22:12 +0000156 /* Divider value calculation */
Matthias Weissere7bed5c2012-09-24 02:46:53 +0000157 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
Marek Vasutdb841402011-09-22 09:22:12 +0000158 div = (i2c_clk_rate + rate - 1) / rate;
159 if (div < i2c_clk_div[0][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000160 clk_div = 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000161 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
Marek Vasutb567b8f2011-09-27 06:34:11 +0000162 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
Marek Vasutdb841402011-09-22 09:22:12 +0000163 else
Marek Vasutb567b8f2011-09-27 06:34:11 +0000164 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
Marek Vasutdb841402011-09-22 09:22:12 +0000165 ;
Sascha Hauercdace062008-03-26 20:40:49 +0100166
Marek Vasutdb841402011-09-22 09:22:12 +0000167 /* Store divider value */
Marek Vasutbf0783d2011-10-26 00:05:44 +0000168 return clk_div;
Marek Vasutdb841402011-09-22 09:22:12 +0000169}
Sascha Hauercdace062008-03-26 20:40:49 +0100170
Marek Vasutdb841402011-09-22 09:22:12 +0000171/*
Troy Kiskye4ff5252012-07-19 08:18:18 +0000172 * Set I2C Bus speed
Marek Vasutdb841402011-09-22 09:22:12 +0000173 */
Peng Fan71204e92015-05-15 07:29:12 +0800174static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
Marek Vasutdb841402011-09-22 09:22:12 +0000175{
Peng Fan71204e92015-05-15 07:29:12 +0800176 ulong base = i2c_bus->base;
177 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
178 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
Marek Vasutbf0783d2011-10-26 00:05:44 +0000179 u8 idx = i2c_clk_div[clk_idx][1];
Peng Fan71204e92015-05-15 07:29:12 +0800180 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Marek Vasutbf0783d2011-10-26 00:05:44 +0000181
Heiko Schochere6c8b712015-05-18 10:58:12 +0200182 if (!base)
183 return -ENODEV;
184
Marek Vasutbf0783d2011-10-26 00:05:44 +0000185 /* Store divider value */
Peng Fan71204e92015-05-15 07:29:12 +0800186 writeb(idx, base + (IFDR << reg_shift));
Marek Vasutbf0783d2011-10-26 00:05:44 +0000187
Troy Kisky83a1a192012-07-19 08:18:12 +0000188 /* Reset module */
Peng Fan71204e92015-05-15 07:29:12 +0800189 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
190 writeb(0, base + (I2SR << reg_shift));
Marek Vasutb567b8f2011-09-27 06:34:11 +0000191 return 0;
192}
193
Troy Kisky7aa57a02012-07-19 08:18:09 +0000194#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
195#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
196#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
197
Peng Fan71204e92015-05-15 07:29:12 +0800198static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
Stefano Babic81687212011-01-20 07:51:31 +0000199{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000200 unsigned sr;
201 ulong elapsed;
Peng Fan71204e92015-05-15 07:29:12 +0800202 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
203 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
204 ulong base = i2c_bus->base;
Troy Kisky7aa57a02012-07-19 08:18:09 +0000205 ulong start_time = get_timer(0);
206 for (;;) {
Peng Fan71204e92015-05-15 07:29:12 +0800207 sr = readb(base + (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000208 if (sr & I2SR_IAL) {
Peng Fan71204e92015-05-15 07:29:12 +0800209 if (quirk)
210 writeb(sr | I2SR_IAL, base +
211 (I2SR << reg_shift));
212 else
213 writeb(sr & ~I2SR_IAL, base +
214 (I2SR << reg_shift));
Troy Kiskyd5383a62012-07-19 08:18:15 +0000215 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
Peng Fan71204e92015-05-15 07:29:12 +0800216 __func__, sr, readb(base + (I2CR << reg_shift)),
217 state);
Troy Kiskyd5383a62012-07-19 08:18:15 +0000218 return -ERESTART;
219 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000220 if ((sr & (state >> 8)) == (unsigned char)state)
221 return sr;
222 WATCHDOG_RESET();
223 elapsed = get_timer(start_time);
224 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
225 break;
Stefano Babic81687212011-01-20 07:51:31 +0000226 }
Troy Kisky7aa57a02012-07-19 08:18:09 +0000227 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
Peng Fan71204e92015-05-15 07:29:12 +0800228 sr, readb(base + (I2CR << reg_shift)), state);
Troy Kiskycea60b02012-07-19 08:18:04 +0000229 return -ETIMEDOUT;
Stefano Babic81687212011-01-20 07:51:31 +0000230}
231
Peng Fan71204e92015-05-15 07:29:12 +0800232static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
Sascha Hauercdace062008-03-26 20:40:49 +0100233{
Troy Kiskycea60b02012-07-19 08:18:04 +0000234 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800235 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
236 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
237 ulong base = i2c_bus->base;
Sascha Hauercdace062008-03-26 20:40:49 +0100238
Peng Fan71204e92015-05-15 07:29:12 +0800239 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
240 writeb(byte, base + (I2DR << reg_shift));
241
242 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kiskycea60b02012-07-19 08:18:04 +0000243 if (ret < 0)
244 return ret;
Troy Kiskycea60b02012-07-19 08:18:04 +0000245 if (ret & I2SR_RX_NO_AK)
246 return -ENODEV;
247 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000248}
249
250/*
Peng Fan71204e92015-05-15 07:29:12 +0800251 * Stub implementations for outer i2c slave operations.
252 */
253void __i2c_force_reset_slave(void)
254{
255}
256void i2c_force_reset_slave(void)
257 __attribute__((weak, alias("__i2c_force_reset_slave")));
258
259/*
Troy Kisky90a5b702012-07-19 08:18:13 +0000260 * Stop I2C transaction
Marek Vasutdb841402011-09-22 09:22:12 +0000261 */
Peng Fan71204e92015-05-15 07:29:12 +0800262static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
Sascha Hauercdace062008-03-26 20:40:49 +0100263{
Troy Kisky7aa57a02012-07-19 08:18:09 +0000264 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800265 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
266 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
267 ulong base = i2c_bus->base;
268 unsigned int temp = readb(base + (I2CR << reg_shift));
Sascha Hauercdace062008-03-26 20:40:49 +0100269
Troy Kisky1c076db2012-07-19 08:18:02 +0000270 temp &= ~(I2CR_MSTA | I2CR_MTX);
Peng Fan71204e92015-05-15 07:29:12 +0800271 writeb(temp, base + (I2CR << reg_shift));
272 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000273 if (ret < 0)
274 printf("%s:trigger stop failed\n", __func__);
Sascha Hauercdace062008-03-26 20:40:49 +0100275}
276
Marek Vasutdb841402011-09-22 09:22:12 +0000277/*
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000278 * Send start signal, chip address and
279 * write register address
Marek Vasutdb841402011-09-22 09:22:12 +0000280 */
Peng Fan71204e92015-05-15 07:29:12 +0800281static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
282 u32 addr, int alen)
Sascha Hauercdace062008-03-26 20:40:49 +0100283{
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000284 unsigned int temp;
285 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800286 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
287 ulong base = i2c_bus->base;
288 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
289
290 /* Reset i2c slave */
291 i2c_force_reset_slave();
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000292
293 /* Enable I2C controller */
Peng Fan71204e92015-05-15 07:29:12 +0800294 if (quirk)
295 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
296 else
297 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
298
299 if (ret) {
300 writeb(I2CR_IEN, base + (I2CR << reg_shift));
Troy Kisky90a5b702012-07-19 08:18:13 +0000301 /* Wait for controller to be stable */
302 udelay(50);
303 }
Peng Fan71204e92015-05-15 07:29:12 +0800304
305 if (readb(base + (IADR << reg_shift)) == (chip << 1))
306 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
307 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
308 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kisky90a5b702012-07-19 08:18:13 +0000309 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000310 return ret;
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000311
312 /* Start I2C transaction */
Peng Fan71204e92015-05-15 07:29:12 +0800313 temp = readb(base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000314 temp |= I2CR_MSTA;
Peng Fan71204e92015-05-15 07:29:12 +0800315 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000316
Peng Fan71204e92015-05-15 07:29:12 +0800317 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000318 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000319 return ret;
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000320
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000321 temp |= I2CR_MTX | I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800322 writeb(temp, base + (I2CR << reg_shift));
Troy Kisky71e9f3c2012-07-19 08:18:11 +0000323
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000324 /* write slave address */
Peng Fan71204e92015-05-15 07:29:12 +0800325 ret = tx_byte(i2c_bus, chip << 1);
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000326 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000327 return ret;
Marek Vasutdb841402011-09-22 09:22:12 +0000328
Marek Vasutbf0783d2011-10-26 00:05:44 +0000329 while (alen--) {
Peng Fan71204e92015-05-15 07:29:12 +0800330 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
Troy Kiskycea60b02012-07-19 08:18:04 +0000331 if (ret < 0)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000332 return ret;
Stefano Babic81687212011-01-20 07:51:31 +0000333 }
Troy Kiskyb230ddc2012-07-19 08:18:06 +0000334 return 0;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000335}
336
Peng Fan71204e92015-05-15 07:29:12 +0800337#ifndef CONFIG_DM_I2C
338int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
339{
340 if (i2c_bus && i2c_bus->idle_bus_fn)
341 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
342 return 0;
343}
344#else
345/*
Peng Fane1bed802016-03-11 16:47:50 +0800346 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
347 * "
348 * scl-gpios: specify the gpio related to SCL pin
349 * sda-gpios: specify the gpio related to SDA pin
350 * add pinctrl to configure i2c pins to gpio function for i2c
351 * bus recovery, call it "gpio" state
352 * "
353 *
354 * The i2c_idle_bus is an implementation following Linux Kernel.
Peng Fan71204e92015-05-15 07:29:12 +0800355 */
Peng Fan71204e92015-05-15 07:29:12 +0800356int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
Peng Fane1bed802016-03-11 16:47:50 +0800357{
358 struct udevice *bus = i2c_bus->bus;
359 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
360 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
361 int sda, scl;
362 int i, ret = 0;
363 ulong elapsed, start_time;
364
365 if (pinctrl_select_state(bus, "gpio")) {
366 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
367 /*
368 * GPIO pinctrl for i2c force idle is not a must,
369 * but it is strongly recommended to be used.
370 * Because it can help you to recover from bad
371 * i2c bus state. Do not return failure, because
372 * it is not a must.
373 */
374 return 0;
375 }
376
377 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
378 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
379 scl = dm_gpio_get_value(scl_gpio);
380 sda = dm_gpio_get_value(sda_gpio);
381
382 if ((sda & scl) == 1)
383 goto exit; /* Bus is idle already */
384
385 /* Send high and low on the SCL line */
386 for (i = 0; i < 9; i++) {
387 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
388 dm_gpio_set_value(scl_gpio, 0);
389 udelay(50);
390 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
391 udelay(50);
392 }
393 start_time = get_timer(0);
394 for (;;) {
395 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
396 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
397 scl = dm_gpio_get_value(scl_gpio);
398 sda = dm_gpio_get_value(sda_gpio);
399 if ((sda & scl) == 1)
400 break;
401 WATCHDOG_RESET();
402 elapsed = get_timer(start_time);
403 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
404 ret = -EBUSY;
405 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
406 break;
407 }
408 }
409
410exit:
411 pinctrl_select_state(bus, "default");
412 return ret;
413}
Peng Fan71204e92015-05-15 07:29:12 +0800414#endif
415
416static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
417 u32 addr, int alen)
Troy Kiskya7f1a002012-07-19 08:18:16 +0000418{
419 int retry;
420 int ret;
Peng Fan71204e92015-05-15 07:29:12 +0800421 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
422 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Heiko Schochere6c8b712015-05-18 10:58:12 +0200423
424 if (!i2c_bus->base)
425 return -ENODEV;
426
Troy Kiskya7f1a002012-07-19 08:18:16 +0000427 for (retry = 0; retry < 3; retry++) {
Peng Fan71204e92015-05-15 07:29:12 +0800428 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000429 if (ret >= 0)
430 return 0;
Peng Fan71204e92015-05-15 07:29:12 +0800431 i2c_imx_stop(i2c_bus);
Troy Kiskya7f1a002012-07-19 08:18:16 +0000432 if (ret == -ENODEV)
433 return ret;
434
435 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
436 retry);
437 if (ret != -ERESTART)
Alison Wang30ea41a2013-06-17 15:30:39 +0800438 /* Disable controller */
Peng Fan71204e92015-05-15 07:29:12 +0800439 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
Troy Kiskya7f1a002012-07-19 08:18:16 +0000440 udelay(100);
Peng Fan71204e92015-05-15 07:29:12 +0800441 if (i2c_idle_bus(i2c_bus) < 0)
Troy Kisky96c19bd2012-07-19 08:18:19 +0000442 break;
Troy Kiskya7f1a002012-07-19 08:18:16 +0000443 }
Peng Fan71204e92015-05-15 07:29:12 +0800444 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
Marek Vasutdb841402011-09-22 09:22:12 +0000445 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100446}
447
Peng Fan71204e92015-05-15 07:29:12 +0800448
449static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
450 int len)
451{
452 int i, ret = 0;
453
454 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
455 debug("write_data: ");
456 /* use rc for counter */
457 for (i = 0; i < len; ++i)
458 debug(" 0x%02x", buf[i]);
459 debug("\n");
460
461 for (i = 0; i < len; i++) {
462 ret = tx_byte(i2c_bus, buf[i]);
463 if (ret < 0) {
464 debug("i2c_write_data(): rc=%d\n", ret);
465 break;
466 }
467 }
468
469 return ret;
470}
471
472static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
473 int len)
Marek Vasutdb841402011-09-22 09:22:12 +0000474{
Marek Vasutdb841402011-09-22 09:22:12 +0000475 int ret;
476 unsigned int temp;
477 int i;
Peng Fan71204e92015-05-15 07:29:12 +0800478 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
479 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
480 ulong base = i2c_bus->base;
Marek Vasutdb841402011-09-22 09:22:12 +0000481
Peng Fan71204e92015-05-15 07:29:12 +0800482 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
Marek Vasutdb841402011-09-22 09:22:12 +0000483
484 /* setup bus to read data */
Peng Fan71204e92015-05-15 07:29:12 +0800485 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000486 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
487 if (len == 1)
488 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800489 writeb(temp, base + (I2CR << reg_shift));
490 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
491 /* dummy read to clear ICF */
492 readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000493
494 /* read data */
495 for (i = 0; i < len; i++) {
Peng Fan71204e92015-05-15 07:29:12 +0800496 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000497 if (ret < 0) {
Peng Fan71204e92015-05-15 07:29:12 +0800498 debug("i2c_read_data(): ret=%d\n", ret);
499 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000500 return ret;
Troy Kiskyc4330d22012-07-19 08:18:07 +0000501 }
Marek Vasutdb841402011-09-22 09:22:12 +0000502
503 /*
504 * It must generate STOP before read I2DR to prevent
505 * controller from generating another clock cycle
506 */
507 if (i == (len - 1)) {
Peng Fan71204e92015-05-15 07:29:12 +0800508 i2c_imx_stop(i2c_bus);
Marek Vasutdb841402011-09-22 09:22:12 +0000509 } else if (i == (len - 2)) {
Peng Fan71204e92015-05-15 07:29:12 +0800510 temp = readb(base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000511 temp |= I2CR_TX_NO_AK;
Peng Fan71204e92015-05-15 07:29:12 +0800512 writeb(temp, base + (I2CR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000513 }
Peng Fan71204e92015-05-15 07:29:12 +0800514 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
515 buf[i] = readb(base + (I2DR << reg_shift));
Marek Vasutdb841402011-09-22 09:22:12 +0000516 }
Peng Fan71204e92015-05-15 07:29:12 +0800517
518 /* reuse ret for counter*/
519 for (ret = 0; ret < len; ++ret)
520 debug(" 0x%02x", buf[ret]);
521 debug("\n");
522
523 i2c_imx_stop(i2c_bus);
Troy Kisky7aa57a02012-07-19 08:18:09 +0000524 return 0;
Marek Vasutdb841402011-09-22 09:22:12 +0000525}
526
Peng Fan71204e92015-05-15 07:29:12 +0800527#ifndef CONFIG_DM_I2C
528/*
529 * Read data from I2C device
530 */
531static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
532 int alen, u8 *buf, int len)
533{
534 int ret = 0;
535 u32 temp;
536 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
537 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
538 ulong base = i2c_bus->base;
539
540 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
541 if (ret < 0)
542 return ret;
543
544 temp = readb(base + (I2CR << reg_shift));
545 temp |= I2CR_RSTA;
546 writeb(temp, base + (I2CR << reg_shift));
547
548 ret = tx_byte(i2c_bus, (chip << 1) | 1);
549 if (ret < 0) {
550 i2c_imx_stop(i2c_bus);
551 return ret;
552 }
553
554 ret = i2c_read_data(i2c_bus, chip, buf, len);
555
556 i2c_imx_stop(i2c_bus);
557 return ret;
558}
559
Marek Vasutdb841402011-09-22 09:22:12 +0000560/*
561 * Write data to I2C device
562 */
Peng Fan71204e92015-05-15 07:29:12 +0800563static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
564 int alen, const u8 *buf, int len)
Sascha Hauercdace062008-03-26 20:40:49 +0100565{
Peng Fan71204e92015-05-15 07:29:12 +0800566 int ret = 0;
Sascha Hauercdace062008-03-26 20:40:49 +0100567
Peng Fan71204e92015-05-15 07:29:12 +0800568 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
Troy Kiskycea60b02012-07-19 08:18:04 +0000569 if (ret < 0)
Marek Vasutdb841402011-09-22 09:22:12 +0000570 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100571
Peng Fan71204e92015-05-15 07:29:12 +0800572 ret = i2c_write_data(i2c_bus, chip, buf, len);
573
574 i2c_imx_stop(i2c_bus);
575
Marek Vasutdb841402011-09-22 09:22:12 +0000576 return ret;
Sascha Hauercdace062008-03-26 20:40:49 +0100577}
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000578
Heiko Schochere6c8b712015-05-18 10:58:12 +0200579#if !defined(I2C2_BASE_ADDR)
580#define I2C2_BASE_ADDR 0
Heiko Schocher21a26942015-05-18 10:56:24 +0200581#endif
Heiko Schochere6c8b712015-05-18 10:58:12 +0200582
583#if !defined(I2C3_BASE_ADDR)
584#define I2C3_BASE_ADDR 0
585#endif
586
587#if !defined(I2C4_BASE_ADDR)
588#define I2C4_BASE_ADDR 0
589#endif
590
591static struct mxc_i2c_bus mxc_i2c_buses[] = {
Mingkai Hu9f3183d2015-10-26 19:47:50 +0800592#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
593 defined(CONFIG_FSL_LAYERSCAPE)
Peng Fan71204e92015-05-15 07:29:12 +0800594 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
595 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
596 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
597 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
Troy Kiskye4ff5252012-07-19 08:18:18 +0000598#else
Heiko Schochere6c8b712015-05-18 10:58:12 +0200599 { 0, I2C1_BASE_ADDR, 0 },
600 { 1, I2C2_BASE_ADDR, 0 },
601 { 2, I2C3_BASE_ADDR, 0 },
602 { 3, I2C4_BASE_ADDR, 0 },
Troy Kiskye4ff5252012-07-19 08:18:18 +0000603#endif
tremfac96402013-09-21 18:13:35 +0200604};
605
Peng Fan71204e92015-05-15 07:29:12 +0800606struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
tremfac96402013-09-21 18:13:35 +0200607{
Peng Fan71204e92015-05-15 07:29:12 +0800608 return &mxc_i2c_buses[adap->hwadapnr];
Troy Kisky96c19bd2012-07-19 08:18:19 +0000609}
610
tremfac96402013-09-21 18:13:35 +0200611static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
612 uint addr, int alen, uint8_t *buffer,
613 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000614{
tremfac96402013-09-21 18:13:35 +0200615 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kisky98153262012-07-19 08:18:20 +0000616}
617
tremfac96402013-09-21 18:13:35 +0200618static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
619 uint addr, int alen, uint8_t *buffer,
620 int len)
Troy Kisky98153262012-07-19 08:18:20 +0000621{
tremfac96402013-09-21 18:13:35 +0200622 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000623}
624
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000625/*
626 * Test if a chip at a given address responds (probe the chip)
627 */
tremfac96402013-09-21 18:13:35 +0200628static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Troy Kiskycfbb88d2012-07-19 08:18:08 +0000629{
tremfac96402013-09-21 18:13:35 +0200630 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000631}
632
Peng Fan71204e92015-05-15 07:29:12 +0800633int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000634{
Peng Fan71204e92015-05-15 07:29:12 +0800635 return 1;
636}
637int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
638 __attribute__((weak, alias("__enable_i2c_clk")));
639
640void bus_i2c_init(int index, int speed, int unused,
641 int (*idle_bus_fn)(void *p), void *idle_bus_data)
642{
643 int ret;
644
645 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
646 debug("Error i2c index\n");
Troy Kiskye4ff5252012-07-19 08:18:18 +0000647 return;
Troy Kiskye4ff5252012-07-19 08:18:18 +0000648 }
Peng Fan71204e92015-05-15 07:29:12 +0800649
Gong Qianyuaee3fdd2015-12-18 17:38:01 +0800650 /*
651 * Warning: Be careful to allow the assignment to a static
652 * variable here. This function could be called while U-Boot is
653 * still running in flash memory. So such assignment is equal
654 * to write data to flash without erasing.
655 */
656 if (idle_bus_fn)
657 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
658 if (idle_bus_data)
659 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
Peng Fan71204e92015-05-15 07:29:12 +0800660
661 ret = enable_i2c_clk(1, index);
662 if (ret < 0) {
663 debug("I2C-%d clk fail to enable.\n", index);
664 return;
665 }
666
667 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000668}
669
670/*
Yuan Yao9d10c2d2016-06-08 18:24:51 +0800671 * Early init I2C for prepare read the clk through I2C.
672 */
673void i2c_early_init_f(void)
674{
675 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
676 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
677 & I2C_QUIRK_FLAG ? true : false;
678 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
679
680 /* Set I2C divider value */
681 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
682 /* Reset module */
683 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
684 writeb(0, base + (I2SR << reg_shift));
685 /* Enable I2C */
686 writeb(I2CR_IEN, base + (I2CR << reg_shift));
687}
688
689/*
Troy Kiskye4ff5252012-07-19 08:18:18 +0000690 * Init I2C Bus
691 */
tremfac96402013-09-21 18:13:35 +0200692static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000693{
Peng Fan71204e92015-05-15 07:29:12 +0800694 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000695}
696
697/*
698 * Set I2C Speed
699 */
Peng Fan71204e92015-05-15 07:29:12 +0800700static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
Troy Kiskye4ff5252012-07-19 08:18:18 +0000701{
tremfac96402013-09-21 18:13:35 +0200702 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
Troy Kiskye4ff5252012-07-19 08:18:18 +0000703}
704
705/*
tremfac96402013-09-21 18:13:35 +0200706 * Register mxc i2c adapters
Troy Kiskye4ff5252012-07-19 08:18:18 +0000707 */
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200708#ifdef CONFIG_SYS_I2C_MXC_I2C1
tremfac96402013-09-21 18:13:35 +0200709U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
710 mxc_i2c_read, mxc_i2c_write,
711 mxc_i2c_set_bus_speed,
712 CONFIG_SYS_MXC_I2C1_SPEED,
713 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200714#endif
715
716#ifdef CONFIG_SYS_I2C_MXC_I2C2
tremfac96402013-09-21 18:13:35 +0200717U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
718 mxc_i2c_read, mxc_i2c_write,
719 mxc_i2c_set_bus_speed,
720 CONFIG_SYS_MXC_I2C2_SPEED,
721 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200722#endif
723
York Sunf8cb1012015-03-20 10:20:40 -0700724#ifdef CONFIG_SYS_I2C_MXC_I2C3
tremfac96402013-09-21 18:13:35 +0200725U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
726 mxc_i2c_read, mxc_i2c_write,
727 mxc_i2c_set_bus_speed,
728 CONFIG_SYS_MXC_I2C3_SPEED,
729 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
730#endif
Peng Fan71204e92015-05-15 07:29:12 +0800731
York Sunf8cb1012015-03-20 10:20:40 -0700732#ifdef CONFIG_SYS_I2C_MXC_I2C4
733U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
734 mxc_i2c_read, mxc_i2c_write,
735 mxc_i2c_set_bus_speed,
736 CONFIG_SYS_MXC_I2C4_SPEED,
737 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
738#endif
Peng Fan71204e92015-05-15 07:29:12 +0800739
740#else
741
742static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
743{
744 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
745
746 return bus_i2c_set_bus_speed(i2c_bus, speed);
747}
748
749static int mxc_i2c_probe(struct udevice *bus)
750{
751 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
Peng Fane1bed802016-03-11 16:47:50 +0800752 const void *fdt = gd->fdt_blob;
753 int node = bus->of_offset;
Peng Fan71204e92015-05-15 07:29:12 +0800754 fdt_addr_t addr;
Peng Fane1bed802016-03-11 16:47:50 +0800755 int ret, ret2;
Peng Fan71204e92015-05-15 07:29:12 +0800756
757 i2c_bus->driver_data = dev_get_driver_data(bus);
758
759 addr = dev_get_addr(bus);
760 if (addr == FDT_ADDR_T_NONE)
761 return -ENODEV;
762
763 i2c_bus->base = addr;
764 i2c_bus->index = bus->seq;
Peng Fane1bed802016-03-11 16:47:50 +0800765 i2c_bus->bus = bus;
Peng Fan71204e92015-05-15 07:29:12 +0800766
767 /* Enable clk */
768 ret = enable_i2c_clk(1, bus->seq);
769 if (ret < 0)
770 return ret;
771
Peng Fane1bed802016-03-11 16:47:50 +0800772 /*
773 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
774 * Use gpio to force bus idle when necessary.
775 */
776 ret = fdt_find_string(fdt, node, "pinctrl-names", "gpio");
777 if (ret < 0) {
778 dev_info(dev, "i2c bus %d at %lu, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
779 } else {
780 ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios",
781 0, &i2c_bus->scl_gpio,
782 GPIOD_IS_OUT);
783 ret2 = gpio_request_by_name_nodev(fdt, node, "sda-gpios",
784 0, &i2c_bus->sda_gpio,
785 GPIOD_IS_OUT);
786 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) |
787 !dm_gpio_is_valid(&i2c_bus->scl_gpio) |
788 ret | ret2) {
789 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
790 return -ENODEV;
791 }
792 }
793
Peng Fan71204e92015-05-15 07:29:12 +0800794 ret = i2c_idle_bus(i2c_bus);
795 if (ret < 0) {
796 /* Disable clk */
797 enable_i2c_clk(0, bus->seq);
798 return ret;
799 }
800
801 /*
802 * Pinmux settings are in board file now, until pinmux is supported,
803 * we can set pinmux here in probe function.
804 */
805
806 debug("i2c : controller bus %d at %lu , speed %d: ",
807 bus->seq, i2c_bus->base,
808 i2c_bus->speed);
809
810 return 0;
811}
812
813static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
814 u32 chip_flags)
815{
816 int ret;
817 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
818
819 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
820 if (ret < 0) {
821 debug("%s failed, ret = %d\n", __func__, ret);
822 return ret;
823 }
824
825 i2c_imx_stop(i2c_bus);
826
827 return 0;
828}
829
830static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
831{
832 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
833 int ret = 0;
834 ulong base = i2c_bus->base;
835 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
836 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
837
838 /*
839 * Here the 3rd parameter addr and the 4th one alen are set to 0,
840 * because here we only want to send out chip address. The register
841 * address is wrapped in msg.
842 */
843 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0);
844 if (ret < 0) {
845 debug("i2c_init_transfer error: %d\n", ret);
846 return ret;
847 }
848
849 for (; nmsgs > 0; nmsgs--, msg++) {
850 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
851 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
852 if (msg->flags & I2C_M_RD)
853 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
854 msg->len);
855 else {
856 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
857 msg->len);
858 if (ret)
859 break;
860 if (next_is_read) {
861 /* Reuse ret */
862 ret = readb(base + (I2CR << reg_shift));
863 ret |= I2CR_RSTA;
864 writeb(ret, base + (I2CR << reg_shift));
865
866 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1);
867 if (ret < 0) {
868 i2c_imx_stop(i2c_bus);
869 break;
870 }
871 }
872 }
873 }
874
875 if (ret)
876 debug("i2c_write: error sending\n");
877
878 i2c_imx_stop(i2c_bus);
879
880 return ret;
881}
882
883static const struct dm_i2c_ops mxc_i2c_ops = {
884 .xfer = mxc_i2c_xfer,
885 .probe_chip = mxc_i2c_probe_chip,
886 .set_bus_speed = mxc_i2c_set_bus_speed,
887};
888
889static const struct udevice_id mxc_i2c_ids[] = {
890 { .compatible = "fsl,imx21-i2c", },
891 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
892 {}
893};
894
895U_BOOT_DRIVER(i2c_mxc) = {
896 .name = "i2c_mxc",
897 .id = UCLASS_I2C,
898 .of_match = mxc_i2c_ids,
899 .probe = mxc_i2c_probe,
900 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
901 .ops = &mxc_i2c_ops,
902};
903#endif