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Michal Simek78d19a32009-09-07 09:08:02 +02001/*
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
Michal Simek89c53892008-03-28 12:41:56 +01004 *
Michal Simek89c53892008-03-28 12:41:56 +01005 * Michal SIMEK <monstr@monstr.eu>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Michal Simek78d19a32009-09-07 09:08:02 +02008 */
Michal Simek89c53892008-03-28 12:41:56 +01009
10#include <common.h>
11#include <net.h>
12#include <config.h>
Michal Simek042272a2010-10-11 11:41:47 +100013#include <malloc.h>
Michal Simek89c53892008-03-28 12:41:56 +010014#include <asm/io.h>
Michal Simek7fd70822012-06-28 21:37:57 +000015#include <fdtdec.h>
16
17DECLARE_GLOBAL_DATA_PTR;
Michal Simek89c53892008-03-28 12:41:56 +010018
19#undef DEBUG
20
Michal Simek89c53892008-03-28 12:41:56 +010021#define ENET_ADDR_LENGTH 6
22
23/* EmacLite constants */
24#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
25#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
26#define XEL_TSR_OFFSET 0x07FC /* Tx status */
27#define XEL_RSR_OFFSET 0x17FC /* Rx status */
28#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
29
30/* Xmit complete */
31#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
32/* Xmit interrupt enable bit */
33#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
34/* Buffer is active, SW bit only */
35#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
36/* Program the MAC address */
37#define XEL_TSR_PROGRAM_MASK 0x00000002UL
38/* define for programming the MAC address into the EMAC Lite */
39#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
40
41/* Transmit packet length upper byte */
42#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
43/* Transmit packet length lower byte */
44#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
45
46/* Recv complete */
47#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
48/* Recv interrupt enable bit */
49#define XEL_RSR_RECV_IE_MASK 0x00000008UL
50
Michal Simek773cfa82011-08-25 12:47:56 +020051struct xemaclite {
Michal Simek042272a2010-10-11 11:41:47 +100052 u32 nexttxbuffertouse; /* Next TX buffer to write to */
53 u32 nextrxbuffertouse; /* Next RX buffer to read from */
Michal Simek947324b2011-09-12 21:10:01 +000054 u32 txpp; /* TX ping pong buffer */
55 u32 rxpp; /* RX ping pong buffer */
Michal Simek773cfa82011-08-25 12:47:56 +020056};
Michal Simek89c53892008-03-28 12:41:56 +010057
Clive Stubbingsf2a7806f2008-10-27 15:05:00 +000058static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
Michal Simek89c53892008-03-28 12:41:56 +010059
Michal Simek5ac83802011-09-12 21:10:05 +000060static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +010061{
Michal Simek042272a2010-10-11 11:41:47 +100062 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +010063 u32 alignbuffer;
64 u32 *to32ptr;
65 u32 *from32ptr;
66 u8 *to8ptr;
67 u8 *from8ptr;
68
69 from32ptr = (u32 *) srcptr;
70
71 /* Word aligned buffer, no correction needed. */
72 to32ptr = (u32 *) destptr;
73 while (bytecount > 3) {
74 *to32ptr++ = *from32ptr++;
75 bytecount -= 4;
76 }
77 to8ptr = (u8 *) to32ptr;
78
79 alignbuffer = *from32ptr++;
Michal Simek5ac83802011-09-12 21:10:05 +000080 from8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +010081
Michal Simek5ac83802011-09-12 21:10:05 +000082 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +010083 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +010084}
85
Michal Simek5ac83802011-09-12 21:10:05 +000086static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +010087{
Michal Simek042272a2010-10-11 11:41:47 +100088 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +010089 u32 alignbuffer;
90 u32 *to32ptr = (u32 *) destptr;
91 u32 *from32ptr;
92 u8 *to8ptr;
93 u8 *from8ptr;
94
95 from32ptr = (u32 *) srcptr;
96 while (bytecount > 3) {
97
98 *to32ptr++ = *from32ptr++;
99 bytecount -= 4;
100 }
101
102 alignbuffer = 0;
Michal Simek5ac83802011-09-12 21:10:05 +0000103 to8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +0100104 from8ptr = (u8 *) from32ptr;
105
Michal Simek5ac83802011-09-12 21:10:05 +0000106 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +0100107 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +0100108
109 *to32ptr++ = alignbuffer;
110}
111
Michal Simek042272a2010-10-11 11:41:47 +1000112static void emaclite_halt(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100113{
Michal Simek5ac83802011-09-12 21:10:05 +0000114 debug("eth_halt\n");
Michal Simek89c53892008-03-28 12:41:56 +0100115}
116
Michal Simek042272a2010-10-11 11:41:47 +1000117static int emaclite_init(struct eth_device *dev, bd_t *bis)
Michal Simek89c53892008-03-28 12:41:56 +0100118{
Michal Simek947324b2011-09-12 21:10:01 +0000119 struct xemaclite *emaclite = dev->priv;
Michal Simek5ac83802011-09-12 21:10:05 +0000120 debug("EmacLite Initialization Started\n");
Michal Simek89c53892008-03-28 12:41:56 +0100121
122/*
123 * TX - TX_PING & TX_PONG initialization
124 */
125 /* Restart PING TX */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200126 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simek89c53892008-03-28 12:41:56 +0100127 /* Copy MAC address */
Michal Simek5ac83802011-09-12 21:10:05 +0000128 xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100129 /* Set the length */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200130 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100131 /* Update the MAC address in the EMAC Lite */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200132 out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
Michal Simek89c53892008-03-28 12:41:56 +0100133 /* Wait for EMAC Lite to finish with the MAC address update */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200134 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
135 XEL_TSR_PROG_MAC_ADDR) != 0)
136 ;
Michal Simek89c53892008-03-28 12:41:56 +0100137
Michal Simek947324b2011-09-12 21:10:01 +0000138 if (emaclite->txpp) {
139 /* The same operation with PONG TX */
140 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
141 xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
142 XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
143 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
144 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
145 XEL_TSR_PROG_MAC_ADDR);
146 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
147 XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
148 ;
149 }
Michal Simek89c53892008-03-28 12:41:56 +0100150
151/*
152 * RX - RX_PING & RX_PONG initialization
153 */
154 /* Write out the value to flush the RX buffer */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200155 out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
Michal Simek947324b2011-09-12 21:10:01 +0000156
157 if (emaclite->rxpp)
158 out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
159 XEL_RSR_RECV_IE_MASK);
Michal Simek89c53892008-03-28 12:41:56 +0100160
Michal Simek5ac83802011-09-12 21:10:05 +0000161 debug("EmacLite Initialization complete\n");
Michal Simek89c53892008-03-28 12:41:56 +0100162 return 0;
163}
164
Michal Simek773cfa82011-08-25 12:47:56 +0200165static int xemaclite_txbufferavailable(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100166{
167 u32 reg;
168 u32 txpingbusy;
169 u32 txpongbusy;
Michal Simek773cfa82011-08-25 12:47:56 +0200170 struct xemaclite *emaclite = dev->priv;
171
Michal Simek89c53892008-03-28 12:41:56 +0100172 /*
173 * Read the other buffer register
174 * and determine if the other buffer is available
175 */
Michal Simek773cfa82011-08-25 12:47:56 +0200176 reg = in_be32 (dev->iobase +
177 emaclite->nexttxbuffertouse + 0);
Michal Simek89c53892008-03-28 12:41:56 +0100178 txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
179 XEL_TSR_XMIT_BUSY_MASK);
180
Michal Simek773cfa82011-08-25 12:47:56 +0200181 reg = in_be32 (dev->iobase +
182 (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
Michal Simek89c53892008-03-28 12:41:56 +0100183 txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
184 XEL_TSR_XMIT_BUSY_MASK);
185
Michal Simek5ac83802011-09-12 21:10:05 +0000186 return !(txpingbusy && txpongbusy);
Michal Simek89c53892008-03-28 12:41:56 +0100187}
188
Stephan Linz1ae6b9c2012-05-22 12:18:10 +0000189static int emaclite_send(struct eth_device *dev, void *ptr, int len)
Michal Simek042272a2010-10-11 11:41:47 +1000190{
191 u32 reg;
192 u32 baseaddress;
Michal Simek773cfa82011-08-25 12:47:56 +0200193 struct xemaclite *emaclite = dev->priv;
Michal Simek89c53892008-03-28 12:41:56 +0100194
Michal Simek042272a2010-10-11 11:41:47 +1000195 u32 maxtry = 1000;
Michal Simek89c53892008-03-28 12:41:56 +0100196
Michal Simek80439252011-09-12 21:10:04 +0000197 if (len > PKTSIZE)
198 len = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100199
Michal Simek773cfa82011-08-25 12:47:56 +0200200 while (!xemaclite_txbufferavailable(dev) && maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000201 udelay(10);
Michal Simek89c53892008-03-28 12:41:56 +0100202 maxtry--;
203 }
204
205 if (!maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000206 printf("Error: Timeout waiting for ethernet TX buffer\n");
Michal Simek89c53892008-03-28 12:41:56 +0100207 /* Restart PING TX */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200208 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simek947324b2011-09-12 21:10:01 +0000209 if (emaclite->txpp) {
210 out_be32 (dev->iobase + XEL_TSR_OFFSET +
211 XEL_BUFFER_OFFSET, 0);
212 }
Michal Simek95efa792011-03-08 04:25:53 +0000213 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100214 }
215
216 /* Determine the expected TX buffer address */
Michal Simek773cfa82011-08-25 12:47:56 +0200217 baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
Michal Simek89c53892008-03-28 12:41:56 +0100218
219 /* Determine if the expected buffer address is empty */
220 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
221 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
222 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
223 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
224
Michal Simek947324b2011-09-12 21:10:01 +0000225 if (emaclite->txpp)
226 emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
227
Michal Simek5ac83802011-09-12 21:10:05 +0000228 debug("Send packet from 0x%x\n", baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100229 /* Write the frame to the buffer */
Stephan Linz1ae6b9c2012-05-22 12:18:10 +0000230 xemaclite_alignedwrite(ptr, baseaddress, len);
Michal Simek89c53892008-03-28 12:41:56 +0100231 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
232 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
233 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
234 reg |= XEL_TSR_XMIT_BUSY_MASK;
Michal Simek5ac83802011-09-12 21:10:05 +0000235 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
Michal Simek89c53892008-03-28 12:41:56 +0100236 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
Michal Simek89c53892008-03-28 12:41:56 +0100237 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
Michal Simek95efa792011-03-08 04:25:53 +0000238 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100239 }
Michal Simek947324b2011-09-12 21:10:01 +0000240
241 if (emaclite->txpp) {
242 /* Switch to second buffer */
243 baseaddress ^= XEL_BUFFER_OFFSET;
244 /* Determine if the expected buffer address is empty */
Michal Simek89c53892008-03-28 12:41:56 +0100245 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
Michal Simek947324b2011-09-12 21:10:01 +0000246 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
247 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
248 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
249 debug("Send packet from 0x%x\n", baseaddress);
250 /* Write the frame to the buffer */
Stephan Linz1ae6b9c2012-05-22 12:18:10 +0000251 xemaclite_alignedwrite(ptr, baseaddress, len);
Michal Simek947324b2011-09-12 21:10:01 +0000252 out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
253 (XEL_TPLR_LENGTH_MASK_HI |
254 XEL_TPLR_LENGTH_MASK_LO)));
255 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
256 reg |= XEL_TSR_XMIT_BUSY_MASK;
257 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
258 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
259 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
260 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100261 }
Michal Simek89c53892008-03-28 12:41:56 +0100262 }
Michal Simek947324b2011-09-12 21:10:01 +0000263
Michal Simek5ac83802011-09-12 21:10:05 +0000264 puts("Error while sending frame\n");
Michal Simek95efa792011-03-08 04:25:53 +0000265 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100266}
267
Michal Simek042272a2010-10-11 11:41:47 +1000268static int emaclite_recv(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100269{
Michal Simek042272a2010-10-11 11:41:47 +1000270 u32 length;
271 u32 reg;
272 u32 baseaddress;
Michal Simek773cfa82011-08-25 12:47:56 +0200273 struct xemaclite *emaclite = dev->priv;
Michal Simek89c53892008-03-28 12:41:56 +0100274
Michal Simek773cfa82011-08-25 12:47:56 +0200275 baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
Michal Simek89c53892008-03-28 12:41:56 +0100276 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
Michal Simek5ac83802011-09-12 21:10:05 +0000277 debug("Testing data at address 0x%x\n", baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100278 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
Michal Simek947324b2011-09-12 21:10:01 +0000279 if (emaclite->rxpp)
280 emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
Michal Simek89c53892008-03-28 12:41:56 +0100281 } else {
Michal Simek947324b2011-09-12 21:10:01 +0000282
283 if (!emaclite->rxpp) {
Michal Simek5ac83802011-09-12 21:10:05 +0000284 debug("No data was available - address 0x%x\n",
Michal Simek947324b2011-09-12 21:10:01 +0000285 baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100286 return 0;
Michal Simek947324b2011-09-12 21:10:01 +0000287 } else {
288 baseaddress ^= XEL_BUFFER_OFFSET;
289 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
290 if ((reg & XEL_RSR_RECV_DONE_MASK) !=
291 XEL_RSR_RECV_DONE_MASK) {
292 debug("No data was available - address 0x%x\n",
293 baseaddress);
294 return 0;
295 }
Michal Simek89c53892008-03-28 12:41:56 +0100296 }
Michal Simek89c53892008-03-28 12:41:56 +0100297 }
298 /* Get the length of the frame that arrived */
Michal Simek3f91ec02010-10-11 11:41:46 +1000299 switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
Michal Simek89c53892008-03-28 12:41:56 +0100300 0xFFFF0000 ) >> 16) {
301 case 0x806:
302 length = 42 + 20; /* FIXME size of ARP */
Michal Simek5ac83802011-09-12 21:10:05 +0000303 debug("ARP Packet\n");
Michal Simek89c53892008-03-28 12:41:56 +0100304 break;
305 case 0x800:
306 length = 14 + 14 +
Michal Simek5ac83802011-09-12 21:10:05 +0000307 (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
308 0x10))) & 0xFFFF0000) >> 16);
309 /* FIXME size of IP packet */
Michal Simek89c53892008-03-28 12:41:56 +0100310 debug ("IP Packet\n");
311 break;
312 default:
Michal Simek80439252011-09-12 21:10:04 +0000313 debug("Other Packet\n");
314 length = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100315 break;
316 }
317
Michal Simek5ac83802011-09-12 21:10:05 +0000318 xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
Michal Simek89c53892008-03-28 12:41:56 +0100319 etherrxbuff, length);
320
321 /* Acknowledge the frame */
322 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
323 reg &= ~XEL_RSR_RECV_DONE_MASK;
324 out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
325
Michal Simek5ac83802011-09-12 21:10:05 +0000326 debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
327 NetReceive((uchar *) etherrxbuff, length);
Michal Simek95efa792011-03-08 04:25:53 +0000328 return length;
Michal Simek89c53892008-03-28 12:41:56 +0100329
330}
Michal Simek042272a2010-10-11 11:41:47 +1000331
Michal Simekc1044a12011-10-12 23:23:22 +0000332int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
333 int txpp, int rxpp)
Michal Simek042272a2010-10-11 11:41:47 +1000334{
335 struct eth_device *dev;
Michal Simek773cfa82011-08-25 12:47:56 +0200336 struct xemaclite *emaclite;
Michal Simek042272a2010-10-11 11:41:47 +1000337
Michal Simek28ae02e2011-08-25 12:28:47 +0200338 dev = calloc(1, sizeof(*dev));
Michal Simek042272a2010-10-11 11:41:47 +1000339 if (dev == NULL)
Michal Simek95efa792011-03-08 04:25:53 +0000340 return -1;
Michal Simek042272a2010-10-11 11:41:47 +1000341
Michal Simek773cfa82011-08-25 12:47:56 +0200342 emaclite = calloc(1, sizeof(struct xemaclite));
343 if (emaclite == NULL) {
344 free(dev);
345 return -1;
346 }
347
348 dev->priv = emaclite;
349
Michal Simekc1044a12011-10-12 23:23:22 +0000350 emaclite->txpp = txpp;
351 emaclite->rxpp = rxpp;
Michal Simek947324b2011-09-12 21:10:01 +0000352
Michal Simek9b947552011-10-12 23:23:21 +0000353 sprintf(dev->name, "Xelite.%lx", base_addr);
Michal Simek042272a2010-10-11 11:41:47 +1000354
355 dev->iobase = base_addr;
Michal Simek042272a2010-10-11 11:41:47 +1000356 dev->init = emaclite_init;
357 dev->halt = emaclite_halt;
358 dev->send = emaclite_send;
359 dev->recv = emaclite_recv;
360
361 eth_register(dev);
362
Michal Simek95efa792011-03-08 04:25:53 +0000363 return 1;
Michal Simek042272a2010-10-11 11:41:47 +1000364}
Michal Simek7fd70822012-06-28 21:37:57 +0000365
366#ifdef CONFIG_OF_CONTROL
367int xilinx_emaclite_init(bd_t *bis)
368{
369 int offset = 0;
370 u32 ret = 0;
371 u32 reg;
372
373 do {
374 offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
375 "xlnx,xps-ethernetlite-1.00.a");
376 if (offset != -1) {
377 reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg");
378 if (reg != FDT_ADDR_T_NONE) {
379 u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset,
380 "xlnx,rx-ping-pong", 0);
381 u32 txpp = fdtdec_get_int(gd->fdt_blob, offset,
382 "xlnx,tx-ping-pong", 0);
383 ret |= xilinx_emaclite_initialize(bis, reg,
384 txpp, rxpp);
385 }
386 }
387 } while (offset != -1);
388
389 return ret;
390}
391#endif