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Michal Simek78d19a32009-09-07 09:08:02 +02001/*
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
Michal Simek89c53892008-03-28 12:41:56 +01004 *
Michal Simek89c53892008-03-28 12:41:56 +01005 * Michal SIMEK <monstr@monstr.eu>
6 *
Michal Simek78d19a32009-09-07 09:08:02 +02007 * See file CREDITS for list of people who contributed to this
8 * project.
Michal Simek89c53892008-03-28 12:41:56 +01009 *
Michal Simek78d19a32009-09-07 09:08:02 +020010 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
Michal Simek89c53892008-03-28 12:41:56 +010025
26#include <common.h>
27#include <net.h>
28#include <config.h>
Michal Simek042272a2010-10-11 11:41:47 +100029#include <malloc.h>
Michal Simek89c53892008-03-28 12:41:56 +010030#include <asm/io.h>
31
32#undef DEBUG
33
Michal Simek89c53892008-03-28 12:41:56 +010034#define ENET_ADDR_LENGTH 6
35
36/* EmacLite constants */
37#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
38#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
39#define XEL_TSR_OFFSET 0x07FC /* Tx status */
40#define XEL_RSR_OFFSET 0x17FC /* Rx status */
41#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
42
43/* Xmit complete */
44#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
45/* Xmit interrupt enable bit */
46#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
47/* Buffer is active, SW bit only */
48#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
49/* Program the MAC address */
50#define XEL_TSR_PROGRAM_MASK 0x00000002UL
51/* define for programming the MAC address into the EMAC Lite */
52#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
53
54/* Transmit packet length upper byte */
55#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
56/* Transmit packet length lower byte */
57#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
58
59/* Recv complete */
60#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
61/* Recv interrupt enable bit */
62#define XEL_RSR_RECV_IE_MASK 0x00000008UL
63
Michal Simek773cfa82011-08-25 12:47:56 +020064struct xemaclite {
Michal Simek042272a2010-10-11 11:41:47 +100065 u32 nexttxbuffertouse; /* Next TX buffer to write to */
66 u32 nextrxbuffertouse; /* Next RX buffer to read from */
Michal Simek947324b2011-09-12 21:10:01 +000067 u32 txpp; /* TX ping pong buffer */
68 u32 rxpp; /* RX ping pong buffer */
Michal Simek773cfa82011-08-25 12:47:56 +020069};
Michal Simek89c53892008-03-28 12:41:56 +010070
Clive Stubbingsf2a7806f2008-10-27 15:05:00 +000071static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
Michal Simek89c53892008-03-28 12:41:56 +010072
Michal Simek5ac83802011-09-12 21:10:05 +000073static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +010074{
Michal Simek042272a2010-10-11 11:41:47 +100075 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +010076 u32 alignbuffer;
77 u32 *to32ptr;
78 u32 *from32ptr;
79 u8 *to8ptr;
80 u8 *from8ptr;
81
82 from32ptr = (u32 *) srcptr;
83
84 /* Word aligned buffer, no correction needed. */
85 to32ptr = (u32 *) destptr;
86 while (bytecount > 3) {
87 *to32ptr++ = *from32ptr++;
88 bytecount -= 4;
89 }
90 to8ptr = (u8 *) to32ptr;
91
92 alignbuffer = *from32ptr++;
Michal Simek5ac83802011-09-12 21:10:05 +000093 from8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +010094
Michal Simek5ac83802011-09-12 21:10:05 +000095 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +010096 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +010097}
98
Michal Simek5ac83802011-09-12 21:10:05 +000099static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +0100100{
Michal Simek042272a2010-10-11 11:41:47 +1000101 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +0100102 u32 alignbuffer;
103 u32 *to32ptr = (u32 *) destptr;
104 u32 *from32ptr;
105 u8 *to8ptr;
106 u8 *from8ptr;
107
108 from32ptr = (u32 *) srcptr;
109 while (bytecount > 3) {
110
111 *to32ptr++ = *from32ptr++;
112 bytecount -= 4;
113 }
114
115 alignbuffer = 0;
Michal Simek5ac83802011-09-12 21:10:05 +0000116 to8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +0100117 from8ptr = (u8 *) from32ptr;
118
Michal Simek5ac83802011-09-12 21:10:05 +0000119 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +0100120 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +0100121
122 *to32ptr++ = alignbuffer;
123}
124
Michal Simek042272a2010-10-11 11:41:47 +1000125static void emaclite_halt(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100126{
Michal Simek5ac83802011-09-12 21:10:05 +0000127 debug("eth_halt\n");
Michal Simek89c53892008-03-28 12:41:56 +0100128}
129
Michal Simek042272a2010-10-11 11:41:47 +1000130static int emaclite_init(struct eth_device *dev, bd_t *bis)
Michal Simek89c53892008-03-28 12:41:56 +0100131{
Michal Simek947324b2011-09-12 21:10:01 +0000132 struct xemaclite *emaclite = dev->priv;
Michal Simek5ac83802011-09-12 21:10:05 +0000133 debug("EmacLite Initialization Started\n");
Michal Simek89c53892008-03-28 12:41:56 +0100134
135/*
136 * TX - TX_PING & TX_PONG initialization
137 */
138 /* Restart PING TX */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200139 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simek89c53892008-03-28 12:41:56 +0100140 /* Copy MAC address */
Michal Simek5ac83802011-09-12 21:10:05 +0000141 xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100142 /* Set the length */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200143 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100144 /* Update the MAC address in the EMAC Lite */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200145 out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
Michal Simek89c53892008-03-28 12:41:56 +0100146 /* Wait for EMAC Lite to finish with the MAC address update */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200147 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
148 XEL_TSR_PROG_MAC_ADDR) != 0)
149 ;
Michal Simek89c53892008-03-28 12:41:56 +0100150
Michal Simek947324b2011-09-12 21:10:01 +0000151 if (emaclite->txpp) {
152 /* The same operation with PONG TX */
153 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
154 xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
155 XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
156 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
157 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
158 XEL_TSR_PROG_MAC_ADDR);
159 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
160 XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
161 ;
162 }
Michal Simek89c53892008-03-28 12:41:56 +0100163
164/*
165 * RX - RX_PING & RX_PONG initialization
166 */
167 /* Write out the value to flush the RX buffer */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200168 out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
Michal Simek947324b2011-09-12 21:10:01 +0000169
170 if (emaclite->rxpp)
171 out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
172 XEL_RSR_RECV_IE_MASK);
Michal Simek89c53892008-03-28 12:41:56 +0100173
Michal Simek5ac83802011-09-12 21:10:05 +0000174 debug("EmacLite Initialization complete\n");
Michal Simek89c53892008-03-28 12:41:56 +0100175 return 0;
176}
177
Michal Simek773cfa82011-08-25 12:47:56 +0200178static int xemaclite_txbufferavailable(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100179{
180 u32 reg;
181 u32 txpingbusy;
182 u32 txpongbusy;
Michal Simek773cfa82011-08-25 12:47:56 +0200183 struct xemaclite *emaclite = dev->priv;
184
Michal Simek89c53892008-03-28 12:41:56 +0100185 /*
186 * Read the other buffer register
187 * and determine if the other buffer is available
188 */
Michal Simek773cfa82011-08-25 12:47:56 +0200189 reg = in_be32 (dev->iobase +
190 emaclite->nexttxbuffertouse + 0);
Michal Simek89c53892008-03-28 12:41:56 +0100191 txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
192 XEL_TSR_XMIT_BUSY_MASK);
193
Michal Simek773cfa82011-08-25 12:47:56 +0200194 reg = in_be32 (dev->iobase +
195 (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
Michal Simek89c53892008-03-28 12:41:56 +0100196 txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
197 XEL_TSR_XMIT_BUSY_MASK);
198
Michal Simek5ac83802011-09-12 21:10:05 +0000199 return !(txpingbusy && txpongbusy);
Michal Simek89c53892008-03-28 12:41:56 +0100200}
201
Michal Simek5ac83802011-09-12 21:10:05 +0000202static int emaclite_send(struct eth_device *dev, volatile void *ptr, int len)
Michal Simek042272a2010-10-11 11:41:47 +1000203{
204 u32 reg;
205 u32 baseaddress;
Michal Simek773cfa82011-08-25 12:47:56 +0200206 struct xemaclite *emaclite = dev->priv;
Michal Simek89c53892008-03-28 12:41:56 +0100207
Michal Simek042272a2010-10-11 11:41:47 +1000208 u32 maxtry = 1000;
Michal Simek89c53892008-03-28 12:41:56 +0100209
Michal Simek80439252011-09-12 21:10:04 +0000210 if (len > PKTSIZE)
211 len = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100212
Michal Simek773cfa82011-08-25 12:47:56 +0200213 while (!xemaclite_txbufferavailable(dev) && maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000214 udelay(10);
Michal Simek89c53892008-03-28 12:41:56 +0100215 maxtry--;
216 }
217
218 if (!maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000219 printf("Error: Timeout waiting for ethernet TX buffer\n");
Michal Simek89c53892008-03-28 12:41:56 +0100220 /* Restart PING TX */
Michal Simek8d95ddb2011-08-25 12:36:39 +0200221 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
Michal Simek947324b2011-09-12 21:10:01 +0000222 if (emaclite->txpp) {
223 out_be32 (dev->iobase + XEL_TSR_OFFSET +
224 XEL_BUFFER_OFFSET, 0);
225 }
Michal Simek95efa792011-03-08 04:25:53 +0000226 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100227 }
228
229 /* Determine the expected TX buffer address */
Michal Simek773cfa82011-08-25 12:47:56 +0200230 baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
Michal Simek89c53892008-03-28 12:41:56 +0100231
232 /* Determine if the expected buffer address is empty */
233 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
234 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
235 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
236 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
237
Michal Simek947324b2011-09-12 21:10:01 +0000238 if (emaclite->txpp)
239 emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
240
Michal Simek5ac83802011-09-12 21:10:05 +0000241 debug("Send packet from 0x%x\n", baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100242 /* Write the frame to the buffer */
Michal Simek5ac83802011-09-12 21:10:05 +0000243 xemaclite_alignedwrite((void *) ptr, baseaddress, len);
Michal Simek89c53892008-03-28 12:41:56 +0100244 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
245 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
246 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
247 reg |= XEL_TSR_XMIT_BUSY_MASK;
Michal Simek5ac83802011-09-12 21:10:05 +0000248 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
Michal Simek89c53892008-03-28 12:41:56 +0100249 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
Michal Simek89c53892008-03-28 12:41:56 +0100250 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
Michal Simek95efa792011-03-08 04:25:53 +0000251 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100252 }
Michal Simek947324b2011-09-12 21:10:01 +0000253
254 if (emaclite->txpp) {
255 /* Switch to second buffer */
256 baseaddress ^= XEL_BUFFER_OFFSET;
257 /* Determine if the expected buffer address is empty */
Michal Simek89c53892008-03-28 12:41:56 +0100258 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
Michal Simek947324b2011-09-12 21:10:01 +0000259 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
260 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
261 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
262 debug("Send packet from 0x%x\n", baseaddress);
263 /* Write the frame to the buffer */
264 xemaclite_alignedwrite((void *) ptr, baseaddress, len);
265 out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
266 (XEL_TPLR_LENGTH_MASK_HI |
267 XEL_TPLR_LENGTH_MASK_LO)));
268 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
269 reg |= XEL_TSR_XMIT_BUSY_MASK;
270 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
271 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
272 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
273 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100274 }
Michal Simek89c53892008-03-28 12:41:56 +0100275 }
Michal Simek947324b2011-09-12 21:10:01 +0000276
Michal Simek5ac83802011-09-12 21:10:05 +0000277 puts("Error while sending frame\n");
Michal Simek95efa792011-03-08 04:25:53 +0000278 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100279}
280
Michal Simek042272a2010-10-11 11:41:47 +1000281static int emaclite_recv(struct eth_device *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100282{
Michal Simek042272a2010-10-11 11:41:47 +1000283 u32 length;
284 u32 reg;
285 u32 baseaddress;
Michal Simek773cfa82011-08-25 12:47:56 +0200286 struct xemaclite *emaclite = dev->priv;
Michal Simek89c53892008-03-28 12:41:56 +0100287
Michal Simek773cfa82011-08-25 12:47:56 +0200288 baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
Michal Simek89c53892008-03-28 12:41:56 +0100289 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
Michal Simek5ac83802011-09-12 21:10:05 +0000290 debug("Testing data at address 0x%x\n", baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100291 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
Michal Simek947324b2011-09-12 21:10:01 +0000292 if (emaclite->rxpp)
293 emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
Michal Simek89c53892008-03-28 12:41:56 +0100294 } else {
Michal Simek947324b2011-09-12 21:10:01 +0000295
296 if (!emaclite->rxpp) {
Michal Simek5ac83802011-09-12 21:10:05 +0000297 debug("No data was available - address 0x%x\n",
Michal Simek947324b2011-09-12 21:10:01 +0000298 baseaddress);
Michal Simek89c53892008-03-28 12:41:56 +0100299 return 0;
Michal Simek947324b2011-09-12 21:10:01 +0000300 } else {
301 baseaddress ^= XEL_BUFFER_OFFSET;
302 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
303 if ((reg & XEL_RSR_RECV_DONE_MASK) !=
304 XEL_RSR_RECV_DONE_MASK) {
305 debug("No data was available - address 0x%x\n",
306 baseaddress);
307 return 0;
308 }
Michal Simek89c53892008-03-28 12:41:56 +0100309 }
Michal Simek89c53892008-03-28 12:41:56 +0100310 }
311 /* Get the length of the frame that arrived */
Michal Simek3f91ec02010-10-11 11:41:46 +1000312 switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
Michal Simek89c53892008-03-28 12:41:56 +0100313 0xFFFF0000 ) >> 16) {
314 case 0x806:
315 length = 42 + 20; /* FIXME size of ARP */
Michal Simek5ac83802011-09-12 21:10:05 +0000316 debug("ARP Packet\n");
Michal Simek89c53892008-03-28 12:41:56 +0100317 break;
318 case 0x800:
319 length = 14 + 14 +
Michal Simek5ac83802011-09-12 21:10:05 +0000320 (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
321 0x10))) & 0xFFFF0000) >> 16);
322 /* FIXME size of IP packet */
Michal Simek89c53892008-03-28 12:41:56 +0100323 debug ("IP Packet\n");
324 break;
325 default:
Michal Simek80439252011-09-12 21:10:04 +0000326 debug("Other Packet\n");
327 length = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100328 break;
329 }
330
Michal Simek5ac83802011-09-12 21:10:05 +0000331 xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
Michal Simek89c53892008-03-28 12:41:56 +0100332 etherrxbuff, length);
333
334 /* Acknowledge the frame */
335 reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
336 reg &= ~XEL_RSR_RECV_DONE_MASK;
337 out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
338
Michal Simek5ac83802011-09-12 21:10:05 +0000339 debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
340 NetReceive((uchar *) etherrxbuff, length);
Michal Simek95efa792011-03-08 04:25:53 +0000341 return length;
Michal Simek89c53892008-03-28 12:41:56 +0100342
343}
Michal Simek042272a2010-10-11 11:41:47 +1000344
Michal Simek9b947552011-10-12 23:23:21 +0000345int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr)
Michal Simek042272a2010-10-11 11:41:47 +1000346{
347 struct eth_device *dev;
Michal Simek773cfa82011-08-25 12:47:56 +0200348 struct xemaclite *emaclite;
Michal Simek042272a2010-10-11 11:41:47 +1000349
Michal Simek28ae02e2011-08-25 12:28:47 +0200350 dev = calloc(1, sizeof(*dev));
Michal Simek042272a2010-10-11 11:41:47 +1000351 if (dev == NULL)
Michal Simek95efa792011-03-08 04:25:53 +0000352 return -1;
Michal Simek042272a2010-10-11 11:41:47 +1000353
Michal Simek773cfa82011-08-25 12:47:56 +0200354 emaclite = calloc(1, sizeof(struct xemaclite));
355 if (emaclite == NULL) {
356 free(dev);
357 return -1;
358 }
359
360 dev->priv = emaclite;
361
Michal Simek947324b2011-09-12 21:10:01 +0000362#ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
363 emaclite->txpp = 1;
364#endif
365#ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
366 emaclite->rxpp = 1;
367#endif
368
Michal Simek9b947552011-10-12 23:23:21 +0000369 sprintf(dev->name, "Xelite.%lx", base_addr);
Michal Simek042272a2010-10-11 11:41:47 +1000370
371 dev->iobase = base_addr;
Michal Simek042272a2010-10-11 11:41:47 +1000372 dev->init = emaclite_init;
373 dev->halt = emaclite_halt;
374 dev->send = emaclite_send;
375 dev->recv = emaclite_recv;
376
377 eth_register(dev);
378
Michal Simek95efa792011-03-08 04:25:53 +0000379 return 1;
Michal Simek042272a2010-10-11 11:41:47 +1000380}