| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Specialty padding for the Altera SoCFPGA preloader image |
| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __BOOT0_H |
| 7 | #define __BOOT0_H |
| 8 | |
| Philipp Tomsich | a002077 | 2017-10-10 16:21:07 +0200 | [diff] [blame] | 9 | _start: |
| 10 | ARM_VECTORS |
| 11 | |
| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 12 | #ifdef CONFIG_SPL_BUILD |
| Chee, Tien Fong | 4c0f3e7 | 2017-03-29 11:49:16 +0800 | [diff] [blame] | 13 | .balignl 64,0xf33db33f; |
| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 14 | |
| Chee, Tien Fong | 4c0f3e7 | 2017-03-29 11:49:16 +0800 | [diff] [blame] | 15 | .word 0x1337c0d3; /* SoCFPGA preloader validation word */ |
| 16 | .word 0xc01df00d; /* Version, flags, length */ |
| 17 | .word 0xcafec0d3; /* Checksum, zero-pad */ |
| 18 | nop; |
| 19 | |
| Marek Vasut | 34fc2a6 | 2018-04-15 13:15:33 +0200 | [diff] [blame] | 20 | b reset; /* SoCFPGA Gen5 jumps here */ |
| 21 | b reset; /* SoCFPGA Gen10 trampoline */ |
| Chee, Tien Fong | 4c0f3e7 | 2017-03-29 11:49:16 +0800 | [diff] [blame] | 22 | nop; |
| 23 | nop; |
| 24 | #endif |
| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 25 | |
| 26 | #endif /* __BOOT0_H */ |