| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Specialty padding for the Altera SoCFPGA preloader image |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef __BOOT0_H |
| 8 | #define __BOOT0_H |
| 9 | |
| 10 | #ifdef CONFIG_SPL_BUILD |
| Chee, Tien Fong | 4c0f3e7 | 2017-03-29 11:49:16 +0800 | [diff] [blame^] | 11 | .balignl 64,0xf33db33f; |
| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 12 | |
| Chee, Tien Fong | 4c0f3e7 | 2017-03-29 11:49:16 +0800 | [diff] [blame^] | 13 | .word 0x1337c0d3; /* SoCFPGA preloader validation word */ |
| 14 | .word 0xc01df00d; /* Version, flags, length */ |
| 15 | .word 0xcafec0d3; /* Checksum, zero-pad */ |
| 16 | nop; |
| 17 | |
| 18 | b reset; /* SoCFPGA jumps here */ |
| 19 | nop; |
| 20 | nop; |
| 21 | nop; |
| 22 | #endif |
| Marek Vasut | beee6a3 | 2016-11-16 17:20:23 +0100 | [diff] [blame] | 23 | |
| 24 | #endif /* __BOOT0_H */ |