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TsiChungLiew8ae158c2007-08-16 15:05:11 -05001/*
2 * Configuation settings for the Freescale MCF54455 EVB board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew8ae158c2007-08-16 15:05:11 -05008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
TsiChungLiewe8ee8f32007-10-25 17:16:22 -050014#ifndef _M54455EVB_H
15#define _M54455EVB_H
TsiChungLiew8ae158c2007-08-16 15:05:11 -050016
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21#define CONFIG_MCF5445x /* define processor family */
22#define CONFIG_M54455 /* define processor type */
23#define CONFIG_M54455EVB /* M54455EVB board */
24
Alison Wang1313db42015-02-12 18:33:15 +080025#define CONFIG_DISPLAY_BOARDINFO
26
TsiChungLiew8ae158c2007-08-16 15:05:11 -050027#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew8ae158c2007-08-16 15:05:11 -050029#define CONFIG_BAUDRATE 115200
TsiChungLiew8ae158c2007-08-16 15:05:11 -050030
31#undef CONFIG_WATCHDOG
32
33#define CONFIG_TIMESTAMP /* Print image info with timestamp */
34
35/*
36 * BOOTP options
37 */
38#define CONFIG_BOOTP_BOOTFILESIZE
39#define CONFIG_BOOTP_BOOTPATH
40#define CONFIG_BOOTP_GATEWAY
41#define CONFIG_BOOTP_HOSTNAME
42
43/* Command line configuration */
44#include <config_cmd_default.h>
45
46#define CONFIG_CMD_BOOTD
47#define CONFIG_CMD_CACHE
48#define CONFIG_CMD_DATE
49#define CONFIG_CMD_DHCP
50#define CONFIG_CMD_ELF
51#define CONFIG_CMD_EXT2
52#define CONFIG_CMD_FAT
53#define CONFIG_CMD_FLASH
54#define CONFIG_CMD_I2C
55#define CONFIG_CMD_IDE
56#define CONFIG_CMD_JFFS2
57#define CONFIG_CMD_MEMORY
58#define CONFIG_CMD_MISC
59#define CONFIG_CMD_MII
60#define CONFIG_CMD_NET
TsiChungLiewe8ee8f32007-10-25 17:16:22 -050061#undef CONFIG_CMD_PCI
TsiChungLiew8ae158c2007-08-16 15:05:11 -050062#define CONFIG_CMD_PING
63#define CONFIG_CMD_REGINFO
TsiChung Liewa7323bb2008-07-23 17:53:36 -050064#define CONFIG_CMD_SPI
TsiChung Liew922cd752008-08-06 19:14:08 -050065#define CONFIG_CMD_SF
TsiChungLiew8ae158c2007-08-16 15:05:11 -050066
67#undef CONFIG_CMD_LOADB
68#undef CONFIG_CMD_LOADS
69
70/* Network configuration */
71#define CONFIG_MCFFEC
72#ifdef CONFIG_MCFFEC
TsiChungLiew8ae158c2007-08-16 15:05:11 -050073# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050074# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075# define CONFIG_SYS_DISCOVER_PHY
76# define CONFIG_SYS_RX_ETH_BUFFER 8
77# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8ae158c2007-08-16 15:05:11 -050078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079# define CONFIG_SYS_FEC0_PINMUX 0
80# define CONFIG_SYS_FEC1_PINMUX 0
81# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
82# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChungLiew8ae158c2007-08-16 15:05:11 -050083# define MCFFEC_TOUT_LOOP 50000
84# define CONFIG_HAS_ETH1
85
86# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
87# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
88# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
89# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
90# define CONFIG_ETHPRIME "FEC0"
91# define CONFIG_IPADDR 192.162.1.2
92# define CONFIG_NETMASK 255.255.255.0
93# define CONFIG_SERVERIP 192.162.1.1
94# define CONFIG_GATEWAYIP 192.162.1.1
95# define CONFIG_OVERWRITE_ETHADDR_ONCE
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
98# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew8ae158c2007-08-16 15:05:11 -050099# define FECDUPLEX FULL
100# define FECSPEED _100BASET
101# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
103# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500104# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500106#endif
107
108#define CONFIG_HOSTNAME M54455EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liew9f751552008-07-23 20:38:53 -0500110/* ST Micro serial flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_LOAD_ADDR2 0x40010013
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500112#define CONFIG_EXTRA_ENV_SETTINGS \
113 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200114 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew9f751552008-07-23 20:38:53 -0500115 "loadaddr=0x40010000\0" \
116 "sbfhdr=sbfhdr.bin\0" \
117 "uboot=u-boot.bin\0" \
118 "load=tftp ${loadaddr} ${sbfhdr};" \
Marek Vasut5368c552012-09-23 17:41:24 +0200119 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500120 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +0800121 "prog=sf probe 0:1 1000000 3;" \
TsiChung Liew9f751552008-07-23 20:38:53 -0500122 "sf erase 0 30000;" \
123 "sf write ${loadaddr} 0 0x30000;" \
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500124 "save\0" \
125 ""
TsiChung Liew9f751552008-07-23 20:38:53 -0500126#else
127/* Atmel and Intel */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#ifdef CONFIG_SYS_ATMEL_BOOT
129# define CONFIG_SYS_UBOOT_END 0x0403FFFF
130#elif defined(CONFIG_SYS_INTEL_BOOT)
131# define CONFIG_SYS_UBOOT_END 0x3FFFF
TsiChung Liew9f751552008-07-23 20:38:53 -0500132#endif
133#define CONFIG_EXTRA_ENV_SETTINGS \
134 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200135 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew9f751552008-07-23 20:38:53 -0500136 "loadaddr=0x40010000\0" \
137 "uboot=u-boot.bin\0" \
138 "load=tftp ${loadaddr} ${uboot}\0" \
139 "upd=run load; run prog\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200140 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
141 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
142 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
143 __stringify(CONFIG_SYS_UBOOT_END) ";" \
144 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
TsiChung Liew9f751552008-07-23 20:38:53 -0500145 " ${filesize}; save\0" \
146 ""
147#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500148
149/* ATA configuration */
150#define CONFIG_ISO_PARTITION
151#define CONFIG_DOS_PARTITION
152#define CONFIG_IDE_RESET 1
153#define CONFIG_IDE_PREINIT 1
154#define CONFIG_ATAPI
155#undef CONFIG_LBA48
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_IDE_MAXBUS 1
158#define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
161#define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
164#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
165#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
166#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500167
168/* Realtime clock */
169#define CONFIG_MCFRTC
170#undef RTC_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500172
173/* Timer */
174#define CONFIG_MCFTMR
175#undef CONFIG_MCFPIT
176
177/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200178#define CONFIG_SYS_I2C
179#define CONFIG_SYS_I2C_FSL
180#define CONFIG_SYS_FSL_I2C_SPEED 80000
181#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
jason6af3a0e2013-11-06 22:59:08 +0800182#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500184
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500185/* DSPI and Serial Flash */
TsiChung Liewee0a8462009-06-30 14:18:29 +0000186#define CONFIG_CF_SPI
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500187#define CONFIG_CF_DSPI
TsiChung Liewa7323bb2008-07-23 17:53:36 -0500188#define CONFIG_HARD_SPI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_SBFHDR_SIZE 0x13
TsiChung Liewa7323bb2008-07-23 17:53:36 -0500190#ifdef CONFIG_CMD_SPI
TsiChung Liew922cd752008-08-06 19:14:08 -0500191# define CONFIG_SPI_FLASH
192# define CONFIG_SPI_FLASH_STMICRO
193
TsiChung Liewee0a8462009-06-30 14:18:29 +0000194# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
195 DSPI_CTAR_PCSSCK_1CLK | \
196 DSPI_CTAR_PASC(0) | \
197 DSPI_CTAR_PDT(0) | \
198 DSPI_CTAR_CSSCK(0) | \
199 DSPI_CTAR_ASC(0) | \
200 DSPI_CTAR_DT(1))
TsiChung Liewa7323bb2008-07-23 17:53:36 -0500201#endif
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500202
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500203/* PCI */
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500204#ifdef CONFIG_CMD_PCI
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500205#define CONFIG_PCI 1
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600206#define CONFIG_PCI_PNP 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500207#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
212#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
213#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
216#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
217#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
220#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
221#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500222#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500223
224/* FPGA - Spartan 2 */
225/* experiment
Michal Simekb03b25c2013-05-01 18:05:56 +0200226#define CONFIG_FPGA
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500227#define CONFIG_FPGA_COUNT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_FPGA_PROG_FEEDBACK
229#define CONFIG_SYS_FPGA_CHECK_CTRLC
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500230*/
231
232/* Input, PCI, Flexbus, and VCO */
233#define CONFIG_EXTRA_CLOCK
234
TsiChung Liew9f751552008-07-23 20:38:53 -0500235#define CONFIG_PRAM 2048 /* 2048 KB */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_PROMPT "-> "
238#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500239
240#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500242#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500244#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
246#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
247#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500252
253/*
254 * Low Level Configuration Settings
255 * (address mappings, register initial values, etc.)
256 * You should know what you are doing if you make changes here.
257 */
258
259/*-----------------------------------------------------------------------
260 * Definitions for initial stack pointer and data area (in DPRAM)
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200263#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200265#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk553f0982010-10-26 13:32:32 +0200267#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500268
269/*-----------------------------------------------------------------------
270 * Start addresses for the final memory configuration
271 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_SDRAM_BASE 0x40000000
275#define CONFIG_SYS_SDRAM_BASE1 0x48000000
276#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
277#define CONFIG_SYS_SDRAM_CFG1 0x65311610
278#define CONFIG_SYS_SDRAM_CFG2 0x59670000
279#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
280#define CONFIG_SYS_SDRAM_EMOD 0x40010000
281#define CONFIG_SYS_SDRAM_MODE 0x00010033
282#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
285#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500286
TsiChung Liew9f751552008-07-23 20:38:53 -0500287#ifdef CONFIG_CF_SBF
Jason Jin09933fb2011-08-19 10:10:40 +0800288# define CONFIG_SERIAL_BOOT
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200289# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
TsiChung Liew9f751552008-07-23 20:38:53 -0500290#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew9f751552008-07-23 20:38:53 -0500292#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
294#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Jason Jin09933fb2011-08-19 10:10:40 +0800295
296/* Reserve 256 kB for malloc() */
297#define CONFIG_SYS_MALLOC_LEN (256 << 10)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500298
299/*
300 * For booting Linux, the board info and command line data
301 * have to be in the first 8 MB of memory, since this is
302 * the maximum mapped by the Linux kernel during initialization ??
303 */
304/* Initial Memory map for Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500306
TsiChung Liew9f751552008-07-23 20:38:53 -0500307/*
308 * Configuration for environment
Jason Jin09933fb2011-08-19 10:10:40 +0800309 * Environment is not embedded in u-boot. First time runing may have env
310 * crc error warning if there is no correct environment on the flash.
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500311 */
TsiChung Liew9f751552008-07-23 20:38:53 -0500312#ifdef CONFIG_CF_SBF
Jean-Christophe PLAGNIOL-VILLARD0b5099a2008-09-10 22:48:00 +0200313# define CONFIG_ENV_IS_IN_SPI_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200314# define CONFIG_ENV_SPI_CS 1
TsiChung Liew9f751552008-07-23 20:38:53 -0500315#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200316# define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew9f751552008-07-23 20:38:53 -0500317#endif
318#undef CONFIG_ENV_OVERWRITE
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500319
320/*-----------------------------------------------------------------------
321 * FLASH organization
322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liewee0a8462009-06-30 14:18:29 +0000324# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
325# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200326# define CONFIG_ENV_OFFSET 0x30000
327# define CONFIG_ENV_SIZE 0x2000
328# define CONFIG_ENV_SECT_SIZE 0x10000
TsiChung Liew9f751552008-07-23 20:38:53 -0500329#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#ifdef CONFIG_SYS_ATMEL_BOOT
331# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
332# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
333# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
Jason Jin09933fb2011-08-19 10:10:40 +0800334# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
335# define CONFIG_ENV_SIZE 0x2000
336# define CONFIG_ENV_SECT_SIZE 0x10000
TsiChung Liew9f751552008-07-23 20:38:53 -0500337#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#ifdef CONFIG_SYS_INTEL_BOOT
339# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
340# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
341# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
342# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200343# define CONFIG_ENV_SIZE 0x2000
344# define CONFIG_ENV_SECT_SIZE 0x20000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500345#endif
346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_FLASH_CFI
348#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500349
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200350# define CONFIG_FLASH_CFI_DRIVER 1
TsiChung Liewbbf6bbf2009-06-11 12:50:05 +0000351# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
353# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
354# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
355# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
356# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
357# define CONFIG_SYS_FLASH_CHECKSUM
358# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
TsiChung Liewb2d022d2008-07-23 17:37:10 -0500359# define CONFIG_FLASH_CFI_LEGACY
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500360
TsiChung Liewb2d022d2008-07-23 17:37:10 -0500361#ifdef CONFIG_FLASH_CFI_LEGACY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362# define CONFIG_SYS_ATMEL_REGION 4
363# define CONFIG_SYS_ATMEL_TOTALSECT 11
364# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
365# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
TsiChung Liewb2d022d2008-07-23 17:37:10 -0500366#endif
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500367#endif
368
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500369/*
370 * This is setting for JFFS2 support in u-boot.
371 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
372 */
TsiChung Liew9f751552008-07-23 20:38:53 -0500373#ifdef CONFIG_CMD_JFFS2
374#ifdef CF_STMICRO_BOOT
375# define CONFIG_JFFS2_DEV "nor1"
376# define CONFIG_JFFS2_PART_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
TsiChung Liew9f751552008-07-23 20:38:53 -0500378#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#ifdef CONFIG_SYS_ATMEL_BOOT
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500380# define CONFIG_JFFS2_DEV "nor1"
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500381# define CONFIG_JFFS2_PART_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
TsiChung Liew9f751552008-07-23 20:38:53 -0500383#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#ifdef CONFIG_SYS_INTEL_BOOT
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500385# define CONFIG_JFFS2_DEV "nor0"
386# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500388#endif
TsiChung Liew9f751552008-07-23 20:38:53 -0500389#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500390
391/*-----------------------------------------------------------------------
392 * Cache Configuration
393 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500395
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600396#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200397 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600398#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200399 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600400#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
401#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
402#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
403 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
404 CF_ACR_EN | CF_ACR_SM_ALL)
405#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
406 CF_CACR_ICINVA | CF_CACR_EUSP)
407#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
408 CF_CACR_DEC | CF_CACR_DDCM_P | \
409 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
410
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500411/*-----------------------------------------------------------------------
412 * Memory bank definitions
413 */
414/*
415 * CS0 - NOR Flash 1, 2, 4, or 8MB
416 * CS1 - CompactFlash and registers
417 * CS2 - CPLD
418 * CS3 - FPGA
419 * CS4 - Available
420 * CS5 - Available
421 */
422
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500424 /* Atmel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_CS0_BASE 0x04000000
426#define CONFIG_SYS_CS0_MASK 0x00070001
427#define CONFIG_SYS_CS0_CTRL 0x00001140
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500428/* Intel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_CS1_BASE 0x00000000
430#define CONFIG_SYS_CS1_MASK 0x01FF0001
431#define CONFIG_SYS_CS1_CTRL 0x00000D60
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500434#else
435/* Intel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_CS0_BASE 0x00000000
437#define CONFIG_SYS_CS0_MASK 0x01FF0001
438#define CONFIG_SYS_CS0_CTRL 0x00000D60
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500439 /* Atmel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_CS1_BASE 0x04000000
441#define CONFIG_SYS_CS1_MASK 0x00070001
442#define CONFIG_SYS_CS1_CTRL 0x00001140
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500443
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500445#endif
446
447/* CPLD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_CS2_BASE 0x08000000
449#define CONFIG_SYS_CS2_MASK 0x00070001
450#define CONFIG_SYS_CS2_CTRL 0x003f1140
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500451
452/* FPGA */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_CS3_BASE 0x09000000
454#define CONFIG_SYS_CS3_MASK 0x00070001
455#define CONFIG_SYS_CS3_CTRL 0x00000020
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500456
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500457#endif /* _M54455EVB_H */