blob: f8484221fa1da21e814e39b9139f12b815dc7a56 [file] [log] [blame]
Vitaly Andrianovef509b92014-04-04 13:16:53 -04001/*
2 * Keystone2: DDR3 initialization
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
Hao Zhangb1babef2014-07-09 23:44:49 +030011#include "ddr3_cfg.h"
Khoronzhuk, Ivan0b868582014-07-09 19:48:40 +030012#include <asm/arch/ddr3.h>
Vitaly Andrianovef509b92014-04-04 13:16:53 -040013#include <asm/arch/hardware.h>
Vitaly Andrianovef509b92014-04-04 13:16:53 -040014
15struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040016struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040017
Vitaly Andrianov66c98a02015-02-11 14:07:58 -050018u32 ddr3_init(void)
Vitaly Andrianovef509b92014-04-04 13:16:53 -040019{
Vitaly Andrianov66c98a02015-02-11 14:07:58 -050020 u32 ddr3_size;
Vitaly Andrianovd9a76e72016-03-04 10:36:42 -060021 struct ddr3_spd_cb spd_cb;
Vitaly Andrianovef509b92014-04-04 13:16:53 -040022
Vitaly Andrianovd9a76e72016-03-04 10:36:42 -060023 if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
24 printf("Sorry, I don't know how to configure DDR3A.\n"
25 "Bye :(\n");
26 for (;;)
Vitaly Andrianovef509b92014-04-04 13:16:53 -040027 ;
28 }
Murali Karicheri6c343822014-09-10 15:54:59 +030029
Vitaly Andrianovd9a76e72016-03-04 10:36:42 -060030 printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
31
32 if ((cpu_revision() > 1) ||
33 (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
34 printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
35 if (spd_cb.ddrspdclock == 1600)
36 init_pll(&ddr3a_400);
37 else
38 init_pll(&ddr3a_333);
39 }
40
41 if (cpu_revision() > 0) {
42 if (cpu_revision() > 1) {
43 /* PG 2.0 */
44 /* Reset DDR3A PHY after PLL enabled */
45 ddr3_reset_ddrphy();
46 spd_cb.phy_cfg.zq0cr1 |= 0x10000;
47 spd_cb.phy_cfg.zq1cr1 |= 0x10000;
48 spd_cb.phy_cfg.zq2cr1 |= 0x10000;
49 }
50 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
51
52 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
53
54 ddr3_size = spd_cb.ddr_size_gbyte;
55 } else {
56 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
57 spd_cb.emif_cfg.sdcfg |= 0x1000;
58 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
59 ddr3_size = spd_cb.ddr_size_gbyte / 2;
60 }
61 printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
62
Murali Karicheri6c343822014-09-10 15:54:59 +030063 /* Apply the workaround for PG 1.0 and 1.1 Silicons */
64 if (cpu_revision() <= 1)
65 ddr3_err_reset_workaround();
Vitaly Andrianov89f44bb2014-10-22 17:47:58 +030066
Vitaly Andrianov89f44bb2014-10-22 17:47:58 +030067 return ddr3_size;
68}