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Vitaly Andrianovef509b92014-04-04 13:16:53 -04001/*
2 * Keystone2: DDR3 initialization
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
Hao Zhangb1babef2014-07-09 23:44:49 +030011#include "ddr3_cfg.h"
Khoronzhuk, Ivan0b868582014-07-09 19:48:40 +030012#include <asm/arch/ddr3.h>
Vitaly Andrianovef509b92014-04-04 13:16:53 -040013#include <asm/arch/hardware.h>
Vitaly Andrianovef509b92014-04-04 13:16:53 -040014
15struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040016struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040017
Khoronzhuk, Ivan0b868582014-07-09 19:48:40 +030018void ddr3_init(void)
Vitaly Andrianovef509b92014-04-04 13:16:53 -040019{
20 char dimm_name[32];
21
Hao Zhangb1babef2014-07-09 23:44:49 +030022 ddr3_get_dimm_params(dimm_name);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040023
24 printf("Detected SO-DIMM [%s]\n", dimm_name);
25
26 if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
27 init_pll(&ddr3a_400);
28 if (cpu_revision() > 0) {
Hao Zhang101eec52014-07-09 19:48:41 +030029 if (cpu_revision() > 1) {
30 /* PG 2.0 */
31 /* Reset DDR3A PHY after PLL enabled */
32 ddr3_reset_ddrphy();
Hao Zhangb1babef2014-07-09 23:44:49 +030033 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
34 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
35 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030036 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
Hao Zhangb1babef2014-07-09 23:44:49 +030037 &ddr3phy_1600_8g);
Hao Zhang101eec52014-07-09 19:48:41 +030038 } else {
39 /* PG 1.1 */
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030040 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
Hao Zhangb1babef2014-07-09 23:44:49 +030041 &ddr3phy_1600_8g);
Hao Zhang101eec52014-07-09 19:48:41 +030042 }
43
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030044 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
Hao Zhangb1babef2014-07-09 23:44:49 +030045 &ddr3_1600_8g);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040046 printf("DRAM: Capacity 8 GiB (includes reported below)\n");
47 } else {
Hao Zhangb1babef2014-07-09 23:44:49 +030048 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
49 ddr3_1600_8g.sdcfg |= 0x1000;
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030050 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
Hao Zhangb1babef2014-07-09 23:44:49 +030051 &ddr3_1600_8g);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040052 printf("DRAM: Capacity 4 GiB (includes reported below)\n");
53 }
54 } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
55 init_pll(&ddr3a_333);
56 if (cpu_revision() > 0) {
Hao Zhang101eec52014-07-09 19:48:41 +030057 if (cpu_revision() > 1) {
58 /* PG 2.0 */
59 /* Reset DDR3A PHY after PLL enabled */
60 ddr3_reset_ddrphy();
Hao Zhangb1babef2014-07-09 23:44:49 +030061 ddr3phy_1333_2g.zq0cr1 |= 0x10000;
62 ddr3phy_1333_2g.zq1cr1 |= 0x10000;
63 ddr3phy_1333_2g.zq2cr1 |= 0x10000;
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030064 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
Hao Zhangb1babef2014-07-09 23:44:49 +030065 &ddr3phy_1333_2g);
Hao Zhang101eec52014-07-09 19:48:41 +030066 } else {
67 /* PG 1.1 */
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030068 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
Hao Zhangb1babef2014-07-09 23:44:49 +030069 &ddr3phy_1333_2g);
Hao Zhang101eec52014-07-09 19:48:41 +030070 }
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030071 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
Hao Zhangb1babef2014-07-09 23:44:49 +030072 &ddr3_1333_2g);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040073 } else {
Hao Zhangb1babef2014-07-09 23:44:49 +030074 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
75 ddr3_1333_2g.sdcfg |= 0x1000;
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +030076 ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
Hao Zhangb1babef2014-07-09 23:44:49 +030077 &ddr3_1333_2g);
Vitaly Andrianovef509b92014-04-04 13:16:53 -040078 }
79 } else {
80 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
81 while (1)
82 ;
83 }
Murali Karicheri6c343822014-09-10 15:54:59 +030084
85 /* Apply the workaround for PG 1.0 and 1.1 Silicons */
86 if (cpu_revision() <= 1)
87 ddr3_err_reset_workaround();
Vitaly Andrianovef509b92014-04-04 13:16:53 -040088}