Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * NAND driver for TI DaVinci based boards. |
| 3 | * |
| 4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
| 5 | * |
| 6 | * Based on Linux DaVinci NAND driver by TI. Original copyright follows: |
| 7 | */ |
| 8 | |
| 9 | /* |
| 10 | * |
| 11 | * linux/drivers/mtd/nand/nand_davinci.c |
| 12 | * |
| 13 | * NAND Flash Driver |
| 14 | * |
| 15 | * Copyright (C) 2006 Texas Instruments. |
| 16 | * |
| 17 | * ---------------------------------------------------------------------------- |
| 18 | * |
| 19 | * This program is free software; you can redistribute it and/or modify |
| 20 | * it under the terms of the GNU General Public License as published by |
| 21 | * the Free Software Foundation; either version 2 of the License, or |
| 22 | * (at your option) any later version. |
| 23 | * |
| 24 | * This program is distributed in the hope that it will be useful, |
| 25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 27 | * GNU General Public License for more details. |
| 28 | * |
| 29 | * You should have received a copy of the GNU General Public License |
| 30 | * along with this program; if not, write to the Free Software |
| 31 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 32 | * ---------------------------------------------------------------------------- |
| 33 | * |
| 34 | * Overview: |
| 35 | * This is a device driver for the NAND flash device found on the |
| 36 | * DaVinci board which utilizes the Samsung k9k2g08 part. |
| 37 | * |
| 38 | Modifications: |
| 39 | ver. 1.0: Feb 2005, Vinod/Sudhakar |
| 40 | - |
| 41 | * |
| 42 | */ |
| 43 | |
| 44 | #include <common.h> |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 45 | #include <asm/io.h> |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 46 | #include <nand.h> |
| 47 | #include <asm/arch/nand_defs.h> |
| 48 | #include <asm/arch/emif_defs.h> |
| 49 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 50 | extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 51 | |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 52 | static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; |
| 53 | |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 54 | static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 55 | { |
| 56 | struct nand_chip *this = mtd->priv; |
| 57 | u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; |
| 58 | |
| 59 | IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
| 60 | |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 61 | if (ctrl & NAND_CTRL_CHANGE) { |
| 62 | if ( ctrl & NAND_CLE ) |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 63 | IO_ADDR_W |= MASK_CLE; |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 64 | if ( ctrl & NAND_ALE ) |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 65 | IO_ADDR_W |= MASK_ALE; |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 66 | this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 67 | } |
| 68 | |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 69 | if (cmd != NAND_CMD_NONE) |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 70 | writeb(cmd, this->IO_ADDR_W); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | /* Set WP on deselect, write enable on select */ |
| 74 | static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) |
| 75 | { |
| 76 | #define GPIO_SET_DATA01 0x01c67018 |
| 77 | #define GPIO_CLR_DATA01 0x01c6701c |
| 78 | #define GPIO_NAND_WP (1 << 4) |
| 79 | #ifdef SONATA_BOARD_GPIOWP |
| 80 | if (chip < 0) { |
| 81 | REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP; |
| 82 | } else { |
| 83 | REG(GPIO_SET_DATA01) |= GPIO_NAND_WP; |
| 84 | } |
| 85 | #endif |
| 86 | } |
| 87 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #ifdef CONFIG_SYS_NAND_HW_ECC |
| 89 | #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 90 | /* Linux-compatible ECC uses MTD defaults. */ |
| 91 | /* These layouts are not compatible with Linux or RBL/UBL. */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #ifdef CONFIG_SYS_NAND_LARGEPAGE |
Sergey Kubushyn | fe56a27 | 2008-01-09 15:36:20 +0100 | [diff] [blame] | 93 | static struct nand_ecclayout davinci_nand_ecclayout = { |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 94 | .eccbytes = 12, |
| 95 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, |
Sergey Kubushyn | fe56a27 | 2008-01-09 15:36:20 +0100 | [diff] [blame] | 96 | .oobfree = { |
| 97 | {.offset = 2, .length = 6}, |
| 98 | {.offset = 12, .length = 12}, |
| 99 | {.offset = 28, .length = 12}, |
| 100 | {.offset = 44, .length = 12}, |
| 101 | {.offset = 60, .length = 4} |
| 102 | } |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 103 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 104 | #elif defined(CONFIG_SYS_NAND_SMALLPAGE) |
Sergey Kubushyn | fe56a27 | 2008-01-09 15:36:20 +0100 | [diff] [blame] | 105 | static struct nand_ecclayout davinci_nand_ecclayout = { |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 106 | .eccbytes = 3, |
| 107 | .eccpos = {0, 1, 2}, |
Sergey Kubushyn | fe56a27 | 2008-01-09 15:36:20 +0100 | [diff] [blame] | 108 | .oobfree = { |
| 109 | {.offset = 6, .length = 2}, |
| 110 | {.offset = 8, .length = 8} |
| 111 | } |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 112 | }; |
| 113 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!" |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 115 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 117 | |
| 118 | static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) |
| 119 | { |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 120 | int dummy; |
| 121 | |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 122 | dummy = emif_regs->NANDF1ECC; |
| 123 | #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC |
| 124 | dummy = emif_regs->NANDF2ECC; |
| 125 | dummy = emif_regs->NANDF3ECC; |
| 126 | dummy = emif_regs->NANDF4ECC; |
| 127 | #endif |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 128 | |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 129 | /* FIXME: only chipselect 0 is supported for now */ |
| 130 | emif_regs->NANDFCR |= 1 << 8; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) |
| 134 | { |
| 135 | u_int32_t ecc = 0; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 136 | |
| 137 | if (region == 1) |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 138 | ecc = emif_regs->NANDF1ECC; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 139 | else if (region == 2) |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 140 | ecc = emif_regs->NANDF2ECC; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 141 | else if (region == 3) |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 142 | ecc = emif_regs->NANDF3ECC; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 143 | else if (region == 4) |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 144 | ecc = emif_regs->NANDF4ECC; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 145 | |
| 146 | return(ecc); |
| 147 | } |
| 148 | |
| 149 | static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) |
| 150 | { |
| 151 | u_int32_t tmp; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 153 | /* |
| 154 | * This is not how you should read ECCs on large page Davinci devices. |
| 155 | * The region parameter gets you ECCs for flash chips on different chip |
| 156 | * selects, not the 4x512 byte pages in a 2048 byte page. |
| 157 | * |
| 158 | * Preserved for backwards compatibility though. |
| 159 | */ |
| 160 | |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 161 | int region, n; |
| 162 | struct nand_chip *this = mtd->priv; |
| 163 | |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 164 | n = (this->ecc.size/512); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 165 | |
Wolfgang Denk | 950a392 | 2008-04-11 15:11:26 +0200 | [diff] [blame] | 166 | region = 1; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 167 | while (n--) { |
| 168 | tmp = nand_davinci_readecc(mtd, region); |
| 169 | *ecc_code++ = tmp; |
| 170 | *ecc_code++ = tmp >> 16; |
| 171 | *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0); |
| 172 | region++; |
| 173 | } |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 174 | #else |
| 175 | const int region = 1; |
| 176 | |
| 177 | tmp = nand_davinci_readecc(mtd, region); |
| 178 | |
| 179 | /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits |
| 180 | * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */ |
| 181 | tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4); |
| 182 | |
| 183 | /* Invert so that erased block ECC is correct */ |
| 184 | tmp = ~tmp; |
| 185 | |
| 186 | *ecc_code++ = tmp; |
| 187 | *ecc_code++ = tmp >> 8; |
| 188 | *ecc_code++ = tmp >> 16; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 190 | return(0); |
| 191 | } |
| 192 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 194 | static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf) |
| 195 | { |
| 196 | u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8); |
| 197 | |
| 198 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); |
| 199 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); |
| 200 | ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); |
| 201 | } |
| 202 | |
| 203 | static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data) |
| 204 | { |
| 205 | u_int32_t i; |
| 206 | u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; |
| 207 | u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8]; |
| 208 | u_int8_t ecc_bit[24]; |
| 209 | u_int8_t ecc_sum = 0; |
| 210 | u_int8_t find_bit = 0; |
| 211 | u_int32_t find_byte = 0; |
| 212 | int is_ecc_ff; |
| 213 | |
| 214 | is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff)); |
| 215 | |
| 216 | nand_davinci_gen_true_ecc(ecc_nand); |
| 217 | nand_davinci_gen_true_ecc(ecc_calc); |
| 218 | |
| 219 | for (i = 0; i <= 2; i++) { |
| 220 | *(ecc_nand + i) = ~(*(ecc_nand + i)); |
| 221 | *(ecc_calc + i) = ~(*(ecc_calc + i)); |
| 222 | } |
| 223 | |
| 224 | for (i = 0; i < 8; i++) { |
| 225 | tmp0_bit[i] = *ecc_nand % 2; |
| 226 | *ecc_nand = *ecc_nand / 2; |
| 227 | } |
| 228 | |
| 229 | for (i = 0; i < 8; i++) { |
| 230 | tmp1_bit[i] = *(ecc_nand + 1) % 2; |
| 231 | *(ecc_nand + 1) = *(ecc_nand + 1) / 2; |
| 232 | } |
| 233 | |
| 234 | for (i = 0; i < 8; i++) { |
| 235 | tmp2_bit[i] = *(ecc_nand + 2) % 2; |
| 236 | *(ecc_nand + 2) = *(ecc_nand + 2) / 2; |
| 237 | } |
| 238 | |
| 239 | for (i = 0; i < 8; i++) { |
| 240 | comp0_bit[i] = *ecc_calc % 2; |
| 241 | *ecc_calc = *ecc_calc / 2; |
| 242 | } |
| 243 | |
| 244 | for (i = 0; i < 8; i++) { |
| 245 | comp1_bit[i] = *(ecc_calc + 1) % 2; |
| 246 | *(ecc_calc + 1) = *(ecc_calc + 1) / 2; |
| 247 | } |
| 248 | |
| 249 | for (i = 0; i < 8; i++) { |
| 250 | comp2_bit[i] = *(ecc_calc + 2) % 2; |
| 251 | *(ecc_calc + 2) = *(ecc_calc + 2) / 2; |
| 252 | } |
| 253 | |
| 254 | for (i = 0; i< 6; i++) |
| 255 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; |
| 256 | |
| 257 | for (i = 0; i < 8; i++) |
| 258 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; |
| 259 | |
| 260 | for (i = 0; i < 8; i++) |
| 261 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; |
| 262 | |
| 263 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; |
| 264 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; |
| 265 | |
| 266 | for (i = 0; i < 24; i++) |
| 267 | ecc_sum += ecc_bit[i]; |
| 268 | |
| 269 | switch (ecc_sum) { |
| 270 | case 0: |
| 271 | /* Not reached because this function is not called if |
| 272 | ECC values are equal */ |
| 273 | return 0; |
| 274 | case 1: |
| 275 | /* Uncorrectable error */ |
Scott Wood | 3167c53 | 2008-06-20 12:38:57 -0500 | [diff] [blame] | 276 | MTDDEBUG (MTD_DEBUG_LEVEL0, |
| 277 | "ECC UNCORRECTED_ERROR 1\n"); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 278 | return(-1); |
| 279 | case 12: |
| 280 | /* Correctable error */ |
| 281 | find_byte = (ecc_bit[23] << 8) + |
| 282 | (ecc_bit[21] << 7) + |
| 283 | (ecc_bit[19] << 6) + |
| 284 | (ecc_bit[17] << 5) + |
| 285 | (ecc_bit[15] << 4) + |
| 286 | (ecc_bit[13] << 3) + |
| 287 | (ecc_bit[11] << 2) + |
| 288 | (ecc_bit[9] << 1) + |
| 289 | ecc_bit[7]; |
| 290 | |
| 291 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; |
| 292 | |
Scott Wood | 3167c53 | 2008-06-20 12:38:57 -0500 | [diff] [blame] | 293 | MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC " |
| 294 | "error at offset: %d, bit: %d\n", |
| 295 | find_byte, find_bit); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 296 | |
| 297 | page_data[find_byte] ^= (1 << find_bit); |
| 298 | |
| 299 | return(0); |
| 300 | default: |
| 301 | if (is_ecc_ff) { |
| 302 | if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) |
| 303 | return(0); |
| 304 | } |
Scott Wood | 3167c53 | 2008-06-20 12:38:57 -0500 | [diff] [blame] | 305 | MTDDEBUG (MTD_DEBUG_LEVEL0, |
| 306 | "UNCORRECTED_ERROR default\n"); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 307 | return(-1); |
| 308 | } |
| 309 | } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 310 | #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 311 | |
| 312 | static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) |
| 313 | { |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 314 | struct nand_chip *this = mtd->priv; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 316 | int block_count = 0, i, rc; |
| 317 | |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 318 | block_count = (this->ecc.size/512); |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 319 | for (i = 0; i < block_count; i++) { |
| 320 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { |
| 321 | rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat); |
| 322 | if (rc < 0) { |
| 323 | return(rc); |
| 324 | } |
| 325 | } |
| 326 | read_ecc += 3; |
| 327 | calc_ecc += 3; |
| 328 | dat += 512; |
| 329 | } |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 330 | #else |
| 331 | u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | |
| 332 | (read_ecc[2] << 16); |
| 333 | u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | |
| 334 | (calc_ecc[2] << 16); |
| 335 | u_int32_t diff = ecc_calc ^ ecc_nand; |
| 336 | |
| 337 | if (diff) { |
| 338 | if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { |
| 339 | /* Correctable error */ |
| 340 | if ((diff >> (12 + 3)) < this->ecc.size) { |
| 341 | uint8_t find_bit = 1 << ((diff >> 12) & 7); |
| 342 | uint32_t find_byte = diff >> (12 + 3); |
| 343 | |
| 344 | dat[find_byte] ^= find_bit; |
| 345 | MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single " |
| 346 | "bit ECC error at offset: %d, bit: " |
| 347 | "%d\n", find_byte, find_bit); |
| 348 | return 1; |
| 349 | } else { |
| 350 | return -1; |
| 351 | } |
| 352 | } else if (!(diff & (diff - 1))) { |
| 353 | /* Single bit ECC error in the ECC itself, |
| 354 | nothing to fix */ |
| 355 | MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in " |
| 356 | "ECC.\n"); |
| 357 | return 1; |
| 358 | } else { |
| 359 | /* Uncorrectable error */ |
| 360 | MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); |
| 361 | return -1; |
| 362 | } |
| 363 | } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 364 | #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 365 | return(0); |
| 366 | } |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 367 | #endif /* CONFIG_SYS_NAND_HW_ECC */ |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 368 | |
| 369 | static int nand_davinci_dev_ready(struct mtd_info *mtd) |
| 370 | { |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 371 | return emif_regs->NANDFSR & 0x1; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 372 | } |
| 373 | |
| 374 | static void nand_flash_init(void) |
| 375 | { |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 376 | /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS! |
| 377 | * Instead, have your board_init() set EMIF timings, based on its |
| 378 | * knowledge of the clocks and what devices are hooked up ... and |
| 379 | * don't even do that unless no UBL handled it. |
| 380 | */ |
| 381 | #ifdef CONFIG_SOC_DM6446 |
Wolfgang Denk | 950a392 | 2008-04-11 15:11:26 +0200 | [diff] [blame] | 382 | u_int32_t acfg1 = 0x3ffffffc; |
Wolfgang Denk | 950a392 | 2008-04-11 15:11:26 +0200 | [diff] [blame] | 383 | |
| 384 | /*------------------------------------------------------------------* |
| 385 | * NAND FLASH CHIP TIMEOUT @ 459 MHz * |
| 386 | * * |
| 387 | * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * |
| 388 | * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * |
| 389 | * * |
| 390 | *------------------------------------------------------------------*/ |
| 391 | acfg1 = 0 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 392 | | (0 << 31 ) /* selectStrobe */ |
| 393 | | (0 << 30 ) /* extWait */ |
| 394 | | (1 << 26 ) /* writeSetup 10 ns */ |
| 395 | | (3 << 20 ) /* writeStrobe 40 ns */ |
| 396 | | (1 << 17 ) /* writeHold 10 ns */ |
| 397 | | (1 << 13 ) /* readSetup 10 ns */ |
| 398 | | (5 << 7 ) /* readStrobe 60 ns */ |
| 399 | | (1 << 4 ) /* readHold 10 ns */ |
| 400 | | (3 << 2 ) /* turnAround ?? ns */ |
| 401 | | (0 << 0 ) /* asyncSize 8-bit bus */ |
| 402 | ; |
Wolfgang Denk | 950a392 | 2008-04-11 15:11:26 +0200 | [diff] [blame] | 403 | |
Thomas Lange | d583ef5 | 2009-06-20 11:02:17 +0200 | [diff] [blame] | 404 | emif_regs->AB1CR = acfg1; /* CS2 */ |
| 405 | |
| 406 | emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */ |
David Brownell | fcb7747 | 2009-04-28 13:19:50 -0700 | [diff] [blame^] | 407 | #endif |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | int board_nand_init(struct nand_chip *nand) |
| 411 | { |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 412 | nand->chip_delay = 0; |
| 413 | nand->select_chip = nand_davinci_select_chip; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 414 | #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 415 | nand->options = NAND_USE_FLASH_BBT; |
| 416 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 417 | #ifdef CONFIG_SYS_NAND_HW_ECC |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 418 | nand->ecc.mode = NAND_ECC_HW; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 419 | #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 420 | nand->ecc.layout = &davinci_nand_ecclayout; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 421 | #ifdef CONFIG_SYS_NAND_LARGEPAGE |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 422 | nand->ecc.size = 2048; |
| 423 | nand->ecc.bytes = 12; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 424 | #elif defined(CONFIG_SYS_NAND_SMALLPAGE) |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 425 | nand->ecc.size = 512; |
| 426 | nand->ecc.bytes = 3; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 427 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 428 | #error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!" |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 429 | #endif |
Hugo Villeneuve | 9b05aa7 | 2008-08-30 17:06:55 -0400 | [diff] [blame] | 430 | #else |
| 431 | nand->ecc.size = 512; |
| 432 | nand->ecc.bytes = 3; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 433 | #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */ |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 434 | nand->ecc.calculate = nand_davinci_calculate_ecc; |
| 435 | nand->ecc.correct = nand_davinci_correct_data; |
William Juul | 4cbb651 | 2007-11-08 10:39:53 +0100 | [diff] [blame] | 436 | nand->ecc.hwctl = nand_davinci_enable_hwecc; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 437 | #else |
William Juul | 5e1dae5 | 2007-11-09 13:32:30 +0100 | [diff] [blame] | 438 | nand->ecc.mode = NAND_ECC_SOFT; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 439 | #endif /* CONFIG_SYS_NAND_HW_ECC */ |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 440 | |
| 441 | /* Set address of hardware control function */ |
William Juul | cfa460a | 2007-10-31 13:53:06 +0100 | [diff] [blame] | 442 | nand->cmd_ctrl = nand_davinci_hwcontrol; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 443 | |
| 444 | nand->dev_ready = nand_davinci_dev_ready; |
Sergey Kubushyn | c74b210 | 2007-08-10 20:26:18 +0200 | [diff] [blame] | 445 | |
| 446 | nand_flash_init(); |
| 447 | |
| 448 | return(0); |
| 449 | } |