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Sergey Kubushync74b2102007-08-10 20:26:18 +02001/*
2 * NAND driver for TI DaVinci based boards.
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 *
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
7 */
8
9/*
10 *
11 * linux/drivers/mtd/nand/nand_davinci.c
12 *
13 * NAND Flash Driver
14 *
15 * Copyright (C) 2006 Texas Instruments.
16 *
17 * ----------------------------------------------------------------------------
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
33 *
34 * Overview:
35 * This is a device driver for the NAND flash device found on the
36 * DaVinci board which utilizes the Samsung k9k2g08 part.
37 *
38 Modifications:
39 ver. 1.0: Feb 2005, Vinod/Sudhakar
40 -
41 *
42 */
43
44#include <common.h>
45
46#ifdef CFG_USE_NAND
47#if !defined(CFG_NAND_LEGACY)
48
49#include <nand.h>
50#include <asm/arch/nand_defs.h>
51#include <asm/arch/emif_defs.h>
52
53extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
54
55static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd)
56{
57 struct nand_chip *this = mtd->priv;
58 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
59
60 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
61
62 switch (cmd) {
63 case NAND_CTL_SETCLE:
64 IO_ADDR_W |= MASK_CLE;
65 break;
66 case NAND_CTL_SETALE:
67 IO_ADDR_W |= MASK_ALE;
68 break;
69 }
70
71 this->IO_ADDR_W = (void *)IO_ADDR_W;
72}
73
74/* Set WP on deselect, write enable on select */
75static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
76{
77#define GPIO_SET_DATA01 0x01c67018
78#define GPIO_CLR_DATA01 0x01c6701c
79#define GPIO_NAND_WP (1 << 4)
80#ifdef SONATA_BOARD_GPIOWP
81 if (chip < 0) {
82 REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
83 } else {
84 REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
85 }
86#endif
87}
88
89#ifdef CFG_NAND_HW_ECC
90#ifdef CFG_NAND_LARGEPAGE
91static struct nand_oobinfo davinci_nand_oobinfo = {
92 .useecc = MTD_NANDECC_AUTOPLACE,
93 .eccbytes = 12,
94 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
95 .oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} }
96};
97#elif defined(CFG_NAND_SMALLPAGE)
98static struct nand_oobinfo davinci_nand_oobinfo = {
99 .useecc = MTD_NANDECC_AUTOPLACE,
100 .eccbytes = 3,
101 .eccpos = {0, 1, 2},
102 .oobfree = { {6, 2}, {8, 8} }
103};
104#else
105#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
106#endif
107
108static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
109{
110 emifregs emif_addr;
111 int dummy;
112
113 emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
114
115 dummy = emif_addr->NANDF1ECC;
116 dummy = emif_addr->NANDF2ECC;
117 dummy = emif_addr->NANDF3ECC;
118 dummy = emif_addr->NANDF4ECC;
119
Wolfgang Denk950a3922008-04-11 15:11:26 +0200120 emif_addr->NANDFCR |= (1 << 8);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200121}
122
123static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
124{
125 u_int32_t ecc = 0;
126 emifregs emif_base_addr;
127
128 emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
129
130 if (region == 1)
131 ecc = emif_base_addr->NANDF1ECC;
132 else if (region == 2)
133 ecc = emif_base_addr->NANDF2ECC;
134 else if (region == 3)
135 ecc = emif_base_addr->NANDF3ECC;
136 else if (region == 4)
137 ecc = emif_base_addr->NANDF4ECC;
138
139 return(ecc);
140}
141
142static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
143{
144 u_int32_t tmp;
145 int region, n;
146 struct nand_chip *this = mtd->priv;
147
148 n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
149
Wolfgang Denk950a3922008-04-11 15:11:26 +0200150 region = 1;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200151 while (n--) {
152 tmp = nand_davinci_readecc(mtd, region);
153 *ecc_code++ = tmp;
154 *ecc_code++ = tmp >> 16;
155 *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
156 region++;
157 }
158 return(0);
159}
160
161static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
162{
163 u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
164
165 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
166 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
167 ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
168}
169
170static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
171{
172 u_int32_t i;
173 u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
174 u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8];
175 u_int8_t ecc_bit[24];
176 u_int8_t ecc_sum = 0;
177 u_int8_t find_bit = 0;
178 u_int32_t find_byte = 0;
179 int is_ecc_ff;
180
181 is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
182
183 nand_davinci_gen_true_ecc(ecc_nand);
184 nand_davinci_gen_true_ecc(ecc_calc);
185
186 for (i = 0; i <= 2; i++) {
187 *(ecc_nand + i) = ~(*(ecc_nand + i));
188 *(ecc_calc + i) = ~(*(ecc_calc + i));
189 }
190
191 for (i = 0; i < 8; i++) {
192 tmp0_bit[i] = *ecc_nand % 2;
193 *ecc_nand = *ecc_nand / 2;
194 }
195
196 for (i = 0; i < 8; i++) {
197 tmp1_bit[i] = *(ecc_nand + 1) % 2;
198 *(ecc_nand + 1) = *(ecc_nand + 1) / 2;
199 }
200
201 for (i = 0; i < 8; i++) {
202 tmp2_bit[i] = *(ecc_nand + 2) % 2;
203 *(ecc_nand + 2) = *(ecc_nand + 2) / 2;
204 }
205
206 for (i = 0; i < 8; i++) {
207 comp0_bit[i] = *ecc_calc % 2;
208 *ecc_calc = *ecc_calc / 2;
209 }
210
211 for (i = 0; i < 8; i++) {
212 comp1_bit[i] = *(ecc_calc + 1) % 2;
213 *(ecc_calc + 1) = *(ecc_calc + 1) / 2;
214 }
215
216 for (i = 0; i < 8; i++) {
217 comp2_bit[i] = *(ecc_calc + 2) % 2;
218 *(ecc_calc + 2) = *(ecc_calc + 2) / 2;
219 }
220
221 for (i = 0; i< 6; i++)
222 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
223
224 for (i = 0; i < 8; i++)
225 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
226
227 for (i = 0; i < 8; i++)
228 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
229
230 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
231 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
232
233 for (i = 0; i < 24; i++)
234 ecc_sum += ecc_bit[i];
235
236 switch (ecc_sum) {
237 case 0:
238 /* Not reached because this function is not called if
239 ECC values are equal */
240 return 0;
241 case 1:
242 /* Uncorrectable error */
Scott Wood3167c532008-06-20 12:38:57 -0500243 MTDDEBUG (MTD_DEBUG_LEVEL0,
244 "ECC UNCORRECTED_ERROR 1\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200245 return(-1);
246 case 12:
247 /* Correctable error */
248 find_byte = (ecc_bit[23] << 8) +
249 (ecc_bit[21] << 7) +
250 (ecc_bit[19] << 6) +
251 (ecc_bit[17] << 5) +
252 (ecc_bit[15] << 4) +
253 (ecc_bit[13] << 3) +
254 (ecc_bit[11] << 2) +
255 (ecc_bit[9] << 1) +
256 ecc_bit[7];
257
258 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
259
Scott Wood3167c532008-06-20 12:38:57 -0500260 MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC "
261 "error at offset: %d, bit: %d\n",
262 find_byte, find_bit);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200263
264 page_data[find_byte] ^= (1 << find_bit);
265
266 return(0);
267 default:
268 if (is_ecc_ff) {
269 if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
270 return(0);
271 }
Scott Wood3167c532008-06-20 12:38:57 -0500272 MTDDEBUG (MTD_DEBUG_LEVEL0,
273 "UNCORRECTED_ERROR default\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200274 return(-1);
275 }
276}
277
278static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
279{
280 struct nand_chip *this;
281 int block_count = 0, i, rc;
282
283 this = mtd->priv;
284 block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
285 for (i = 0; i < block_count; i++) {
286 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
287 rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
288 if (rc < 0) {
289 return(rc);
290 }
291 }
292 read_ecc += 3;
293 calc_ecc += 3;
294 dat += 512;
295 }
296 return(0);
297}
298#endif
299
300static int nand_davinci_dev_ready(struct mtd_info *mtd)
301{
302 emifregs emif_addr;
303
304 emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
305
306 return(emif_addr->NANDFSR & 0x1);
307}
308
309static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
310{
311 while(!nand_davinci_dev_ready(mtd)) {;}
312 *NAND_CE0CLE = NAND_STATUS;
313 return(*NAND_CE0DATA);
314}
315
316static void nand_flash_init(void)
317{
Wolfgang Denk950a3922008-04-11 15:11:26 +0200318 u_int32_t acfg1 = 0x3ffffffc;
319 u_int32_t acfg2 = 0x3ffffffc;
320 u_int32_t acfg3 = 0x3ffffffc;
321 u_int32_t acfg4 = 0x3ffffffc;
322 emifregs emif_regs;
323
324 /*------------------------------------------------------------------*
325 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
326 * *
327 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
328 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
329 * *
330 *------------------------------------------------------------------*/
331 acfg1 = 0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200332 | (0 << 31 ) /* selectStrobe */
333 | (0 << 30 ) /* extWait */
334 | (1 << 26 ) /* writeSetup 10 ns */
335 | (3 << 20 ) /* writeStrobe 40 ns */
336 | (1 << 17 ) /* writeHold 10 ns */
337 | (1 << 13 ) /* readSetup 10 ns */
338 | (5 << 7 ) /* readStrobe 60 ns */
339 | (1 << 4 ) /* readHold 10 ns */
340 | (3 << 2 ) /* turnAround ?? ns */
341 | (0 << 0 ) /* asyncSize 8-bit bus */
342 ;
Wolfgang Denk950a3922008-04-11 15:11:26 +0200343
344 emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
345
346 emif_regs->AWCCR |= 0x10000000;
347 emif_regs->AB1CR = acfg1; /* 0x08244128 */;
348 emif_regs->AB2CR = acfg2;
349 emif_regs->AB3CR = acfg3;
350 emif_regs->AB4CR = acfg4;
351 emif_regs->NANDFCR = 0x00000101;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200352}
353
354int board_nand_init(struct nand_chip *nand)
355{
356 nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
357 nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
358 nand->chip_delay = 0;
359 nand->select_chip = nand_davinci_select_chip;
360#ifdef CFG_NAND_USE_FLASH_BBT
361 nand->options = NAND_USE_FLASH_BBT;
362#endif
363#ifdef CFG_NAND_HW_ECC
364#ifdef CFG_NAND_LARGEPAGE
365 nand->eccmode = NAND_ECC_HW12_2048;
366#elif defined(CFG_NAND_SMALLPAGE)
367 nand->eccmode = NAND_ECC_HW3_512;
368#else
369#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
370#endif
371 nand->autooob = &davinci_nand_oobinfo;
372 nand->calculate_ecc = nand_davinci_calculate_ecc;
373 nand->correct_data = nand_davinci_correct_data;
374 nand->enable_hwecc = nand_davinci_enable_hwecc;
375#else
376 nand->eccmode = NAND_ECC_SOFT;
377#endif
378
379 /* Set address of hardware control function */
380 nand->hwcontrol = nand_davinci_hwcontrol;
381
382 nand->dev_ready = nand_davinci_dev_ready;
383 nand->waitfunc = nand_davinci_waitfunc;
384
385 nand_flash_init();
386
387 return(0);
388}
389
390#else
391#error "U-Boot legacy NAND support not available for DaVinci chips"
392#endif
393#endif /* CFG_USE_NAND */