Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * emif4.c |
| 3 | * |
| 4 | * AM33XX emif4 configuration file |
| 5 | * |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <asm/arch/cpu.h> |
| 13 | #include <asm/arch/ddr_defs.h> |
| 14 | #include <asm/arch/hardware.h> |
| 15 | #include <asm/arch/clock.h> |
Tom Rini | b971dfa | 2012-07-03 09:20:06 -0700 | [diff] [blame] | 16 | #include <asm/arch/sys_proto.h> |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 17 | #include <asm/io.h> |
Tom Rini | fda35eb | 2012-07-03 08:51:34 -0700 | [diff] [blame] | 18 | #include <asm/emif.h> |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 19 | |
| 20 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 22 | int dram_init(void) |
| 23 | { |
Tom Rini | 87acf19 | 2014-05-21 12:57:21 -0400 | [diff] [blame] | 24 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 25 | sdram_init(); |
| 26 | #endif |
| 27 | |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 28 | /* dram_init must store complete ramsize in gd->ram_size */ |
| 29 | gd->ram_size = get_ram_size( |
| 30 | (void *)CONFIG_SYS_SDRAM_BASE, |
| 31 | CONFIG_MAX_RAM_BANK_SIZE); |
| 32 | return 0; |
| 33 | } |
| 34 | |
| 35 | void dram_init_banksize(void) |
| 36 | { |
| 37 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
| 38 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 39 | } |
| 40 | |
| 41 | |
Tom Rini | d0e6d34 | 2014-04-09 08:25:57 -0400 | [diff] [blame] | 42 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
Steve Kipisz | c5c7a7c | 2013-07-18 15:13:04 -0400 | [diff] [blame] | 43 | #ifdef CONFIG_TI81XX |
Matt Porter | 4fab8d7 | 2013-03-15 10:07:07 +0000 | [diff] [blame] | 44 | static struct dmm_lisa_map_regs *hw_lisa_map_regs = |
| 45 | (struct dmm_lisa_map_regs *)DMM_BASE; |
Steve Kipisz | c5c7a7c | 2013-07-18 15:13:04 -0400 | [diff] [blame] | 46 | #endif |
TENART Antoine | dcf846d | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 47 | #ifndef CONFIG_TI816X |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 48 | static struct vtp_reg *vtpreg[2] = { |
| 49 | (struct vtp_reg *)VTP0_CTRL_ADDR, |
| 50 | (struct vtp_reg *)VTP1_CTRL_ADDR}; |
TENART Antoine | dcf846d | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 51 | #endif |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 52 | #ifdef CONFIG_AM33XX |
Tom Rini | 942d3f0 | 2012-07-30 14:13:16 -0700 | [diff] [blame] | 53 | static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 54 | #endif |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 55 | #ifdef CONFIG_AM43XX |
| 56 | static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; |
| 57 | static struct cm_device_inst *cm_device = |
| 58 | (struct cm_device_inst *)CM_DEVICE_INST; |
| 59 | #endif |
Tom Rini | 942d3f0 | 2012-07-30 14:13:16 -0700 | [diff] [blame] | 60 | |
Steve Kipisz | c5c7a7c | 2013-07-18 15:13:04 -0400 | [diff] [blame] | 61 | #ifdef CONFIG_TI81XX |
Matt Porter | 4fab8d7 | 2013-03-15 10:07:07 +0000 | [diff] [blame] | 62 | void config_dmm(const struct dmm_lisa_map_regs *regs) |
| 63 | { |
| 64 | enable_dmm_clocks(); |
| 65 | |
| 66 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); |
| 67 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); |
| 68 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); |
| 69 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); |
| 70 | |
| 71 | writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); |
| 72 | writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); |
| 73 | writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); |
| 74 | writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); |
| 75 | } |
Steve Kipisz | c5c7a7c | 2013-07-18 15:13:04 -0400 | [diff] [blame] | 76 | #endif |
Matt Porter | 4fab8d7 | 2013-03-15 10:07:07 +0000 | [diff] [blame] | 77 | |
TENART Antoine | dcf846d | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 78 | #ifndef CONFIG_TI816X |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 79 | static void config_vtp(int nr) |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 80 | { |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 81 | writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, |
| 82 | &vtpreg[nr]->vtp0ctrlreg); |
| 83 | writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), |
| 84 | &vtpreg[nr]->vtp0ctrlreg); |
| 85 | writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, |
| 86 | &vtpreg[nr]->vtp0ctrlreg); |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 87 | |
| 88 | /* Poll for READY */ |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 89 | while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 90 | VTP_CTRL_READY) |
| 91 | ; |
| 92 | } |
TENART Antoine | dcf846d | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 93 | #endif |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 94 | |
Lokesh Vutla | 94d77fb | 2013-07-30 10:48:52 +0530 | [diff] [blame] | 95 | void __weak ddr_pll_config(unsigned int ddrpll_m) |
| 96 | { |
| 97 | } |
| 98 | |
Lokesh Vutla | 965de8b | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 99 | void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, |
Peter Korsgaard | c00f69d | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 100 | const struct ddr_data *data, const struct cmd_control *ctrl, |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 101 | const struct emif_regs *regs, int nr) |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 102 | { |
Peter Korsgaard | c00f69d | 2012-10-18 01:21:12 +0000 | [diff] [blame] | 103 | ddr_pll_config(pll); |
TENART Antoine | dcf846d | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 104 | #ifndef CONFIG_TI816X |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 105 | config_vtp(nr); |
TENART Antoine | dcf846d | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 106 | #endif |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 107 | config_cmd_ctrl(ctrl, nr); |
Tom Rini | 318f27c | 2012-07-30 14:13:56 -0700 | [diff] [blame] | 108 | |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 109 | config_ddr_data(data, nr); |
| 110 | #ifdef CONFIG_AM33XX |
Lokesh Vutla | 965de8b | 2013-12-10 15:02:21 +0530 | [diff] [blame] | 111 | config_io_ctrl(ioregs); |
Tom Rini | 318f27c | 2012-07-30 14:13:56 -0700 | [diff] [blame] | 112 | |
| 113 | /* Set CKE to be controlled by EMIF/DDR PHY */ |
| 114 | writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 115 | #endif |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 116 | #ifdef CONFIG_AM43XX |
| 117 | writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl); |
Jeroen Hofstee | 878cae6 | 2014-06-18 21:22:35 +0200 | [diff] [blame] | 118 | while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0) |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 119 | ; |
Dave Gerlach | b56b9a0 | 2014-02-18 07:32:01 -0500 | [diff] [blame] | 120 | writel(0x80000000, &ddrctrl->ddrioctrl); |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 121 | |
| 122 | config_io_ctrl(ioregs); |
| 123 | |
| 124 | /* Set CKE to be controlled by EMIF/DDR PHY */ |
| 125 | writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); |
| 126 | #endif |
| 127 | |
Tom Rini | 318f27c | 2012-07-30 14:13:56 -0700 | [diff] [blame] | 128 | /* Program EMIF instance */ |
Matt Porter | 3ba65f9 | 2013-03-15 10:07:03 +0000 | [diff] [blame] | 129 | config_ddr_phy(regs, nr); |
| 130 | set_sdram_timings(regs, nr); |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 131 | if (get_emif_rev(EMIF1_BASE) == EMIF_4D5) |
| 132 | config_sdram_emif4d5(regs, nr); |
| 133 | else |
| 134 | config_sdram(regs, nr); |
Chandan Nath | 62d7fe7c | 2011-10-14 02:58:24 +0000 | [diff] [blame] | 135 | } |
| 136 | #endif |