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gerrit.cesnet.cz / github / trini / u-boot / d0e6d34d7cca00cb61707826b52837cc7c43da46 / . / arch / arm / cpu / armv7 / am33xx / emif4.c
blob: 2c67c322cae5ee25b61c868cfeafc0f5098919b4 [file] [log] [blame]
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * emif4.c
3 *
4 * AM33XX emif4 configuration file
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#include <common.h>
12#include <asm/arch/cpu.h>
13#include <asm/arch/ddr_defs.h>
14#include <asm/arch/hardware.h>
15#include <asm/arch/clock.h>
Tom Rinib971dfa2012-07-03 09:20:06 -0700[diff] [blame]16#include <asm/arch/sys_proto.h>
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]17#include <asm/io.h>
Tom Rinifda35eb2012-07-03 08:51:34 -0700[diff] [blame]18#include <asm/emif.h>
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]19
20DECLARE_GLOBAL_DATA_PTR;
21
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]22int dram_init(void)
23{
24 /* dram_init must store complete ramsize in gd->ram_size */
25 gd->ram_size = get_ram_size(
26 (void *)CONFIG_SYS_SDRAM_BASE,
27 CONFIG_MAX_RAM_BANK_SIZE);
28 return 0;
29}
30
31void dram_init_banksize(void)
32{
33 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
34 gd->bd->bi_dram[0].size = gd->ram_size;
35}
36
37
Tom Rinid0e6d342014-04-09 08:25:57 -0400[diff] [blame^]38#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Steve Kipiszc5c7a7c2013-07-18 15:13:04 -0400[diff] [blame]39#ifdef CONFIG_TI81XX
Matt Porter4fab8d72013-03-15 10:07:07 +0000[diff] [blame]40static struct dmm_lisa_map_regs *hw_lisa_map_regs =
41 (struct dmm_lisa_map_regs *)DMM_BASE;
Steve Kipiszc5c7a7c2013-07-18 15:13:04 -0400[diff] [blame]42#endif
TENART Antoinedcf846d2013-07-02 12:05:59 +0200[diff] [blame]43#ifndef CONFIG_TI816X
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]44static struct vtp_reg *vtpreg[2] = {
45 (struct vtp_reg *)VTP0_CTRL_ADDR,
46 (struct vtp_reg *)VTP1_CTRL_ADDR};
TENART Antoinedcf846d2013-07-02 12:05:59 +0200[diff] [blame]47#endif
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]48#ifdef CONFIG_AM33XX
Tom Rini942d3f02012-07-30 14:13:16 -0700[diff] [blame]49static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]50#endif
Lokesh Vutlad3daba12013-12-10 15:02:22 +0530[diff] [blame]51#ifdef CONFIG_AM43XX
52static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
53static struct cm_device_inst *cm_device =
54 (struct cm_device_inst *)CM_DEVICE_INST;
55#endif
Tom Rini942d3f02012-07-30 14:13:16 -0700[diff] [blame]56
Steve Kipiszc5c7a7c2013-07-18 15:13:04 -0400[diff] [blame]57#ifdef CONFIG_TI81XX
Matt Porter4fab8d72013-03-15 10:07:07 +0000[diff] [blame]58void config_dmm(const struct dmm_lisa_map_regs *regs)
59{
60 enable_dmm_clocks();
61
62 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
63 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
64 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
65 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
66
67 writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
68 writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
69 writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
70 writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
71}
Steve Kipiszc5c7a7c2013-07-18 15:13:04 -0400[diff] [blame]72#endif
Matt Porter4fab8d72013-03-15 10:07:07 +0000[diff] [blame]73
TENART Antoinedcf846d2013-07-02 12:05:59 +0200[diff] [blame]74#ifndef CONFIG_TI816X
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]75static void config_vtp(int nr)
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]76{
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]77 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
78 &vtpreg[nr]->vtp0ctrlreg);
79 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
80 &vtpreg[nr]->vtp0ctrlreg);
81 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
82 &vtpreg[nr]->vtp0ctrlreg);
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]83
84 /* Poll for READY */
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]85 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]86 VTP_CTRL_READY)
87 ;
88}
TENART Antoinedcf846d2013-07-02 12:05:59 +0200[diff] [blame]89#endif
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]90
Lokesh Vutla94d77fb2013-07-30 10:48:52 +0530[diff] [blame]91void __weak ddr_pll_config(unsigned int ddrpll_m)
92{
93}
94
Lokesh Vutla965de8b2013-12-10 15:02:21 +0530[diff] [blame]95void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
Peter Korsgaardc00f69d2012-10-18 01:21:12 +0000[diff] [blame]96 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]97 const struct emif_regs *regs, int nr)
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]98{
Peter Korsgaardc00f69d2012-10-18 01:21:12 +0000[diff] [blame]99 ddr_pll_config(pll);
TENART Antoinedcf846d2013-07-02 12:05:59 +0200[diff] [blame]100#ifndef CONFIG_TI816X
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]101 config_vtp(nr);
TENART Antoinedcf846d2013-07-02 12:05:59 +0200[diff] [blame]102#endif
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]103 config_cmd_ctrl(ctrl, nr);
Tom Rini318f27c2012-07-30 14:13:56 -0700[diff] [blame]104
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]105 config_ddr_data(data, nr);
106#ifdef CONFIG_AM33XX
Lokesh Vutla965de8b2013-12-10 15:02:21 +0530[diff] [blame]107 config_io_ctrl(ioregs);
Tom Rini318f27c2012-07-30 14:13:56 -0700[diff] [blame]108
109 /* Set CKE to be controlled by EMIF/DDR PHY */
110 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]111#endif
Lokesh Vutlad3daba12013-12-10 15:02:22 +0530[diff] [blame]112#ifdef CONFIG_AM43XX
113 writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
114 while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
115 ;
Dave Gerlachb56b9a02014-02-18 07:32:01 -0500[diff] [blame]116 writel(0x80000000, &ddrctrl->ddrioctrl);
Lokesh Vutlad3daba12013-12-10 15:02:22 +0530[diff] [blame]117
118 config_io_ctrl(ioregs);
119
120 /* Set CKE to be controlled by EMIF/DDR PHY */
121 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
122#endif
123
Tom Rini318f27c2012-07-30 14:13:56 -0700[diff] [blame]124 /* Program EMIF instance */
Matt Porter3ba65f92013-03-15 10:07:03 +0000[diff] [blame]125 config_ddr_phy(regs, nr);
126 set_sdram_timings(regs, nr);
Lokesh Vutlad3daba12013-12-10 15:02:22 +0530[diff] [blame]127 if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
128 config_sdram_emif4d5(regs, nr);
129 else
130 config_sdram(regs, nr);
Chandan Nath62d7fe7c2011-10-14 02:58:24 +0000[diff] [blame]131}
132#endif