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Marek Vasut6e9a0a32011-11-08 23:18:08 +00001/*
Otavio Salvadorddcf13b2012-08-05 09:05:30 +00002 * Freescale i.MXS Register Accessors
Marek Vasut6e9a0a32011-11-08 23:18:08 +00003 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Marek Vasut6e9a0a32011-11-08 23:18:08 +00008 */
9
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000010#ifndef __MXS_REGS_COMMON_H__
11#define __MXS_REGS_COMMON_H__
Marek Vasut6e9a0a32011-11-08 23:18:08 +000012
13/*
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000014 * The i.MXS has interesting feature when it comes to register access. There
Marek Vasut6e9a0a32011-11-08 23:18:08 +000015 * are four kinds of access to one particular register. Those are:
16 *
17 * 1) Common read/write access. To use this mode, just write to the address of
18 * the register.
19 * 2) Set bits only access. To set bits, write which bits you want to set to the
20 * address of the register + 0x4.
21 * 3) Clear bits only access. To clear bits, write which bits you want to clear
22 * to the address of the register + 0x8.
23 * 4) Toggle bits only access. To toggle bits, write which bits you want to
24 * toggle to the address of the register + 0xc.
25 *
26 * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
27 * can be set/cleared by pure write as in access type 1, some need to be
28 * explicitly set/cleared by using access type 2-3.
29 *
30 * The following macros and structures allow the user to either access the
31 * register in all aforementioned modes (by accessing reg_name, reg_name_set,
32 * reg_name_clr, reg_name_tog) or pass the register structure further into
33 * various functions with correct type information (by accessing reg_name_reg).
34 *
35 */
36
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000037#define __mxs_reg_8(name) \
Robert Delien531bb822012-02-26 12:15:06 +000038 uint8_t name[4]; \
39 uint8_t name##_set[4]; \
40 uint8_t name##_clr[4]; \
41 uint8_t name##_tog[4]; \
42
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000043#define __mxs_reg_32(name) \
Marek Vasut6e9a0a32011-11-08 23:18:08 +000044 uint32_t name; \
45 uint32_t name##_set; \
46 uint32_t name##_clr; \
47 uint32_t name##_tog;
48
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000049struct mxs_register_8 {
50 __mxs_reg_8(reg)
Robert Delien531bb822012-02-26 12:15:06 +000051};
52
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000053struct mxs_register_32 {
54 __mxs_reg_32(reg)
Marek Vasut6e9a0a32011-11-08 23:18:08 +000055};
56
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000057#define mxs_reg_8(name) \
Robert Delien531bb822012-02-26 12:15:06 +000058 union { \
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000059 struct { __mxs_reg_8(name) }; \
60 struct mxs_register_8 name##_reg; \
Robert Delien531bb822012-02-26 12:15:06 +000061 };
62
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000063#define mxs_reg_32(name) \
Marek Vasut6e9a0a32011-11-08 23:18:08 +000064 union { \
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000065 struct { __mxs_reg_32(name) }; \
66 struct mxs_register_32 name##_reg; \
Marek Vasut6e9a0a32011-11-08 23:18:08 +000067 };
68
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000069#endif /* __MXS_REGS_COMMON_H__ */