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Marek Vasut6e9a0a32011-11-08 23:18:08 +00001/*
Otavio Salvadorddcf13b2012-08-05 09:05:30 +00002 * Freescale i.MXS Register Accessors
Marek Vasut6e9a0a32011-11-08 23:18:08 +00003 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000023#ifndef __MXS_REGS_COMMON_H__
24#define __MXS_REGS_COMMON_H__
Marek Vasut6e9a0a32011-11-08 23:18:08 +000025
26/*
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000027 * The i.MXS has interesting feature when it comes to register access. There
Marek Vasut6e9a0a32011-11-08 23:18:08 +000028 * are four kinds of access to one particular register. Those are:
29 *
30 * 1) Common read/write access. To use this mode, just write to the address of
31 * the register.
32 * 2) Set bits only access. To set bits, write which bits you want to set to the
33 * address of the register + 0x4.
34 * 3) Clear bits only access. To clear bits, write which bits you want to clear
35 * to the address of the register + 0x8.
36 * 4) Toggle bits only access. To toggle bits, write which bits you want to
37 * toggle to the address of the register + 0xc.
38 *
39 * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
40 * can be set/cleared by pure write as in access type 1, some need to be
41 * explicitly set/cleared by using access type 2-3.
42 *
43 * The following macros and structures allow the user to either access the
44 * register in all aforementioned modes (by accessing reg_name, reg_name_set,
45 * reg_name_clr, reg_name_tog) or pass the register structure further into
46 * various functions with correct type information (by accessing reg_name_reg).
47 *
48 */
49
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000050#define __mxs_reg_8(name) \
Robert Delien531bb822012-02-26 12:15:06 +000051 uint8_t name[4]; \
52 uint8_t name##_set[4]; \
53 uint8_t name##_clr[4]; \
54 uint8_t name##_tog[4]; \
55
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000056#define __mxs_reg_32(name) \
Marek Vasut6e9a0a32011-11-08 23:18:08 +000057 uint32_t name; \
58 uint32_t name##_set; \
59 uint32_t name##_clr; \
60 uint32_t name##_tog;
61
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000062struct mxs_register_8 {
63 __mxs_reg_8(reg)
Robert Delien531bb822012-02-26 12:15:06 +000064};
65
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000066struct mxs_register_32 {
67 __mxs_reg_32(reg)
Marek Vasut6e9a0a32011-11-08 23:18:08 +000068};
69
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000070#define mxs_reg_8(name) \
Robert Delien531bb822012-02-26 12:15:06 +000071 union { \
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000072 struct { __mxs_reg_8(name) }; \
73 struct mxs_register_8 name##_reg; \
Robert Delien531bb822012-02-26 12:15:06 +000074 };
75
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000076#define mxs_reg_32(name) \
Marek Vasut6e9a0a32011-11-08 23:18:08 +000077 union { \
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000078 struct { __mxs_reg_32(name) }; \
79 struct mxs_register_32 name##_reg; \
Marek Vasut6e9a0a32011-11-08 23:18:08 +000080 };
81
Otavio Salvadorddcf13b2012-08-05 09:05:30 +000082#endif /* __MXS_REGS_COMMON_H__ */