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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0ac6f8b2004-07-09 23:27:13 +000025/*
26 * mpc8540ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8540 1 /* MPC8540 specific */
42#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
wdenk42d1f032003-10-15 23:53:47 +000043
wdenk0ac6f8b2004-07-09 23:27:13 +000044#define CONFIG_PCI
45#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000046#define CONFIG_ENV_OVERWRITE
wdenk0ac6f8b2004-07-09 23:27:13 +000047#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
48#define CONFIG_DDR_ECC /* only for ECC DDR module */
49#define CONFIG_DDR_DLL /* possible DLL fix needed */
50#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk42d1f032003-10-15 23:53:47 +000051
wdenk42d1f032003-10-15 23:53:47 +000052
wdenk0ac6f8b2004-07-09 23:27:13 +000053/*
54 * sysclk for MPC85xx
55 *
56 * Two valid values are:
57 * 33000000
58 * 66000000
59 *
60 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000061 * is likely the desired value here, so that is now the default.
62 * The board, however, can run at 66MHz. In any event, this value
63 * must match the settings of some switches. Details can be found
64 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000065 */
66
wdenk9aea9532004-08-01 23:02:45 +000067#ifndef CONFIG_SYS_CLK_FREQ
68#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000069#endif
70
wdenk9aea9532004-08-01 23:02:45 +000071
wdenk0ac6f8b2004-07-09 23:27:13 +000072/*
73 * These can be toggled for performance analysis, otherwise use default.
74 */
75#define CONFIG_L2_CACHE /* toggle L2 cache */
76#define CONFIG_BTB /* toggle branch predition */
77#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
wdenk42d1f032003-10-15 23:53:47 +000078
wdenk0ac6f8b2004-07-09 23:27:13 +000079#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
wdenk42d1f032003-10-15 23:53:47 +000080
wdenk0ac6f8b2004-07-09 23:27:13 +000081#undef CFG_DRAM_TEST /* memory test, takes time */
82#define CFG_MEMTEST_START 0x00200000 /* memtest region */
wdenk42d1f032003-10-15 23:53:47 +000083#define CFG_MEMTEST_END 0x00400000
84
wdenk42d1f032003-10-15 23:53:47 +000085
86/*
87 * Base addresses -- Note these are effective addresses where the
88 * actual resources get mapped (not physical addresses)
89 */
wdenk0ac6f8b2004-07-09 23:27:13 +000090#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
91#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
92#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
wdenk42d1f032003-10-15 23:53:47 +000093
wdenk9aea9532004-08-01 23:02:45 +000094
95/*
96 * DDR Setup
97 */
wdenk0ac6f8b2004-07-09 23:27:13 +000098#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
wdenk42d1f032003-10-15 23:53:47 +000099#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000100
101#if defined(CONFIG_SPD_EEPROM)
102 /*
103 * Determine DDR configuration from I2C interface.
104 */
105 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
106
107#else
108 /*
109 * Manually set up DDR parameters
110 */
111 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
112 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
113 #define CFG_DDR_CS0_CONFIG 0x80000002
114 #define CFG_DDR_TIMING_1 0x37344321
115 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
116 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
117 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
118 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
119#endif
120
wdenk42d1f032003-10-15 23:53:47 +0000121
wdenk0ac6f8b2004-07-09 23:27:13 +0000122/*
123 * SDRAM on the Local Bus
124 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000125#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
wdenk0ac6f8b2004-07-09 23:27:13 +0000126#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000127
wdenk0ac6f8b2004-07-09 23:27:13 +0000128#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
129#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000130
wdenk0ac6f8b2004-07-09 23:27:13 +0000131#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
132#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
133#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
wdenk42d1f032003-10-15 23:53:47 +0000134#undef CFG_FLASH_CHECKSUM
wdenk0ac6f8b2004-07-09 23:27:13 +0000135#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
136#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000137
wdenk0ac6f8b2004-07-09 23:27:13 +0000138#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
139
wdenk42d1f032003-10-15 23:53:47 +0000140#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
141#define CFG_RAMBOOT
142#else
wdenk0ac6f8b2004-07-09 23:27:13 +0000143#undef CFG_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000144#endif
145
wdenkcf336782004-10-10 20:23:57 +0000146#define CFG_FLASH_CFI_DRIVER
147#define CFG_FLASH_CFI
148#define CFG_FLASH_EMPTY_INFO
wdenk42d1f032003-10-15 23:53:47 +0000149
wdenk42d1f032003-10-15 23:53:47 +0000150#undef CONFIG_CLOCKS_IN_MHZ
151
wdenk0ac6f8b2004-07-09 23:27:13 +0000152
153/*
154 * Local Bus Definitions
155 */
156
157/*
158 * Base Register 2 and Option Register 2 configure SDRAM.
159 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
160 *
161 * For BR2, need:
162 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
163 * port-size = 32-bits = BR2[19:20] = 11
164 * no parity checking = BR2[21:22] = 00
165 * SDRAM for MSEL = BR2[24:26] = 011
166 * Valid = BR[31] = 1
167 *
168 * 0 4 8 12 16 20 24 28
169 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
170 *
171 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
172 * FIXME: the top 17 bits of BR2.
173 */
174
175#define CFG_BR2_PRELIM 0xf0001861
176
177/*
178 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
179 *
180 * For OR2, need:
181 * 64MB mask for AM, OR2[0:7] = 1111 1100
182 * XAM, OR2[17:18] = 11
183 * 9 columns OR2[19-21] = 010
184 * 13 rows OR2[23-25] = 100
185 * EAD set for extra time OR[31] = 1
186 *
187 * 0 4 8 12 16 20 24 28
188 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
189 */
190
wdenk42d1f032003-10-15 23:53:47 +0000191#define CFG_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000192
193#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
194#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
195#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
196#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
197
198/*
199 * LSDMR masks
200 */
201#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
202#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
203#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
204#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
205#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
206#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
207#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
208#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
209#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
210#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
211#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
212#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
213#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
214#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
215#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
216
217#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
218#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
219#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
220#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
221#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
222#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
223#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
224#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
225
226#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
227 | CFG_LBC_LSDMR_RFCR5 \
228 | CFG_LBC_LSDMR_PRETOACT3 \
229 | CFG_LBC_LSDMR_ACTTORW3 \
230 | CFG_LBC_LSDMR_BL8 \
231 | CFG_LBC_LSDMR_WRC2 \
232 | CFG_LBC_LSDMR_CL3 \
233 | CFG_LBC_LSDMR_RFEN \
234 )
235
236/*
237 * SDRAM Controller configuration sequence.
238 */
239#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000240 | CFG_LBC_LSDMR_OP_PCHALL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000241#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000242 | CFG_LBC_LSDMR_OP_ARFRSH)
wdenk0ac6f8b2004-07-09 23:27:13 +0000243#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000244 | CFG_LBC_LSDMR_OP_ARFRSH)
wdenk0ac6f8b2004-07-09 23:27:13 +0000245#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000246 | CFG_LBC_LSDMR_OP_MRW)
wdenk0ac6f8b2004-07-09 23:27:13 +0000247#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000248 | CFG_LBC_LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000249
wdenk42d1f032003-10-15 23:53:47 +0000250
wdenk9aea9532004-08-01 23:02:45 +0000251/*
252 * 32KB, 8-bit wide for ADS config reg
253 */
254#define CFG_BR4_PRELIM 0xf8000801
wdenkc837dcb2004-01-20 23:12:12 +0000255#define CFG_OR4_PRELIM 0xffffe1f1
256#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000257
258#define CONFIG_L1_INIT_RAM
wdenk0ac6f8b2004-07-09 23:27:13 +0000259#define CFG_INIT_RAM_LOCK 1
wdenk9aea9532004-08-01 23:02:45 +0000260#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000261#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000262
wdenk0ac6f8b2004-07-09 23:27:13 +0000263#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
wdenk42d1f032003-10-15 23:53:47 +0000264#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
265#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
266
wdenkcf336782004-10-10 20:23:57 +0000267#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */
wdenk0ac6f8b2004-07-09 23:27:13 +0000268#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000269
270/* Serial Port */
271#define CONFIG_CONS_INDEX 1
272#undef CONFIG_SERIAL_SOFTWARE_FIFO
273#define CFG_NS16550
274#define CFG_NS16550_SERIAL
wdenk0ac6f8b2004-07-09 23:27:13 +0000275#define CFG_NS16550_REG_SIZE 1
wdenk42d1f032003-10-15 23:53:47 +0000276#define CFG_NS16550_CLK get_bus_freq(0)
wdenk42d1f032003-10-15 23:53:47 +0000277
278#define CFG_BAUDRATE_TABLE \
279 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
280
wdenk0ac6f8b2004-07-09 23:27:13 +0000281#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
282#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
wdenk42d1f032003-10-15 23:53:47 +0000283
284/* Use the HUSH parser */
285#define CFG_HUSH_PARSER
wdenk0ac6f8b2004-07-09 23:27:13 +0000286#ifdef CFG_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000287#define CFG_PROMPT_HUSH_PS2 "> "
288#endif
289
290/* I2C */
wdenk0ac6f8b2004-07-09 23:27:13 +0000291#define CONFIG_HARD_I2C /* I2C with hardware support*/
292#undef CONFIG_SOFT_I2C /* I2C bit-banged */
293#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
wdenk42d1f032003-10-15 23:53:47 +0000294#define CFG_I2C_SLAVE 0x7F
wdenk0ac6f8b2004-07-09 23:27:13 +0000295#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
wdenk42d1f032003-10-15 23:53:47 +0000296
wdenk0ac6f8b2004-07-09 23:27:13 +0000297/* RapidIO MMU */
298#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
299#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
300#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
301
302/*
303 * General PCI
304 * Addresses are mapped 1-1.
305 */
306#define CFG_PCI1_MEM_BASE 0x80000000
307#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
308#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
309#define CFG_PCI1_IO_BASE 0xe2000000
310#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
311#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
312
wdenk42d1f032003-10-15 23:53:47 +0000313#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000314
wdenk42d1f032003-10-15 23:53:47 +0000315#define CONFIG_NET_MULTI
wdenk9aea9532004-08-01 23:02:45 +0000316#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000317
wdenk42d1f032003-10-15 23:53:47 +0000318#undef CONFIG_EEPRO100
wdenk0ac6f8b2004-07-09 23:27:13 +0000319#undef CONFIG_TULIP
320
321#if !defined(CONFIG_PCI_PNP)
322 #define PCI_ENET0_IOADDR 0xe0000000
323 #define PCI_ENET0_MEMADDR 0xe0000000
324 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000325#endif
326
wdenk0ac6f8b2004-07-09 23:27:13 +0000327#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
328#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
329
330#endif /* CONFIG_PCI */
331
332
333#if defined(CONFIG_TSEC_ENET)
334
335#ifndef CONFIG_NET_MULTI
336#define CONFIG_NET_MULTI 1
337#endif
338
339#define CONFIG_MII 1 /* MII PHY management */
340#define CONFIG_MPC85XX_TSEC1 1
341#define CONFIG_MPC85XX_TSEC2 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000342#define TSEC1_PHY_ADDR 0
343#define TSEC2_PHY_ADDR 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000344#define TSEC1_PHYIDX 0
345#define TSEC2_PHYIDX 0
wdenk9aea9532004-08-01 23:02:45 +0000346
347#define CONFIG_MPC85XX_FEC 1
348#define FEC_PHY_ADDR 3
wdenk0ac6f8b2004-07-09 23:27:13 +0000349#define FEC_PHYIDX 0
wdenk9aea9532004-08-01 23:02:45 +0000350
wdenk0ac6f8b2004-07-09 23:27:13 +0000351#define CONFIG_ETHPRIME "MOTO ENET0"
352
353#endif /* CONFIG_TSEC_ENET */
354
355
356/*
357 * Environment
358 */
wdenk42d1f032003-10-15 23:53:47 +0000359#ifndef CFG_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000360 #define CFG_ENV_IS_IN_FLASH 1
361 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
wdenk0ac6f8b2004-07-09 23:27:13 +0000362 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
wdenk42d1f032003-10-15 23:53:47 +0000363 #define CFG_ENV_SIZE 0x2000
364#else
wdenk9aea9532004-08-01 23:02:45 +0000365 #define CFG_NO_FLASH 1 /* Flash is not usable now */
366 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
367 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
368 #define CFG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000369#endif
370
wdenk0ac6f8b2004-07-09 23:27:13 +0000371#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
372#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000373
wdenk9aea9532004-08-01 23:02:45 +0000374#if defined(CFG_RAMBOOT)
wdenk42d1f032003-10-15 23:53:47 +0000375 #if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000376 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
377 | CFG_CMD_PING \
378 | CFG_CMD_PCI \
379 | CFG_CMD_I2C) \
380 & \
381 ~(CFG_CMD_ENV \
382 | CFG_CMD_LOADS))
wdenk42d1f032003-10-15 23:53:47 +0000383 #else
wdenk0ac6f8b2004-07-09 23:27:13 +0000384 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
385 | CFG_CMD_PING \
386 | CFG_CMD_I2C) \
387 & \
388 ~(CFG_CMD_ENV \
389 | CFG_CMD_LOADS))
wdenk42d1f032003-10-15 23:53:47 +0000390 #endif
391#else
392 #if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000393 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
394 | CFG_CMD_PCI \
395 | CFG_CMD_PING \
396 | CFG_CMD_I2C)
wdenk42d1f032003-10-15 23:53:47 +0000397 #else
wdenk0ac6f8b2004-07-09 23:27:13 +0000398 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
399 | CFG_CMD_PING \
400 | CFG_CMD_I2C)
wdenk42d1f032003-10-15 23:53:47 +0000401 #endif
402#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000403
wdenk42d1f032003-10-15 23:53:47 +0000404#include <cmd_confdefs.h>
405
wdenk0ac6f8b2004-07-09 23:27:13 +0000406#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000407
408/*
409 * Miscellaneous configurable options
410 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000411#define CFG_LONGHELP /* undef to save memory */
412#define CFG_LOAD_ADDR 0x2000000 /* default load address */
413#define CFG_PROMPT "=> " /* Monitor Command Prompt */
414
wdenk42d1f032003-10-15 23:53:47 +0000415#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk0ac6f8b2004-07-09 23:27:13 +0000416 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000417#else
wdenk0ac6f8b2004-07-09 23:27:13 +0000418 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000419#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000420
wdenk42d1f032003-10-15 23:53:47 +0000421#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000422#define CFG_MAXARGS 16 /* max number of command args */
423#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
424#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk42d1f032003-10-15 23:53:47 +0000425
426/*
427 * For booting Linux, the board info and command line data
428 * have to be in the first 8 MB of memory, since this is
429 * the maximum mapped by the Linux kernel during initialization.
430 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000431#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
wdenk42d1f032003-10-15 23:53:47 +0000432
433/* Cache Configuration */
wdenk0ac6f8b2004-07-09 23:27:13 +0000434#define CFG_DCACHE_SIZE 32768
wdenk42d1f032003-10-15 23:53:47 +0000435#define CFG_CACHELINE_SIZE 32
436#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk0ac6f8b2004-07-09 23:27:13 +0000437#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
wdenk42d1f032003-10-15 23:53:47 +0000438#endif
439
440/*
441 * Internal Definitions
442 *
443 * Boot Flags
444 */
445#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk0ac6f8b2004-07-09 23:27:13 +0000446#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenk42d1f032003-10-15 23:53:47 +0000447
448#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
449#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
450#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
451#endif
452
wdenk9aea9532004-08-01 23:02:45 +0000453
454/*
455 * Environment Configuration
456 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000457
458/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000459#if defined(CONFIG_TSEC_ENET)
wdenk0ac6f8b2004-07-09 23:27:13 +0000460#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
461#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
462#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
wdenk42d1f032003-10-15 23:53:47 +0000463#endif
464
wdenk0ac6f8b2004-07-09 23:27:13 +0000465#define CONFIG_IPADDR 192.168.1.253
466
467#define CONFIG_HOSTNAME unknown
468#define CONFIG_ROOTPATH /nfsroot
469#define CONFIG_BOOTFILE your.uImage
470
471#define CONFIG_SERVERIP 192.168.1.1
472#define CONFIG_GATEWAYIP 192.168.1.1
473#define CONFIG_NETMASK 255.255.255.0
474
475#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
476
477#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
478#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
479
480#define CONFIG_BAUDRATE 115200
481
wdenk9aea9532004-08-01 23:02:45 +0000482#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk0ac6f8b2004-07-09 23:27:13 +0000483 "netdev=eth0\0" \
484 "consoledev=ttyS0\0" \
485 "ramdiskaddr=400000\0" \
486 "ramdiskfile=your.ramdisk.u-boot\0"
487
wdenk9aea9532004-08-01 23:02:45 +0000488#define CONFIG_NFSBOOTCOMMAND \
wdenk0ac6f8b2004-07-09 23:27:13 +0000489 "setenv bootargs root=/dev/nfs rw " \
490 "nfsroot=$serverip:$rootpath " \
491 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
492 "console=$consoledev,$baudrate $othbootargs;" \
493 "tftp $loadaddr $bootfile;" \
494 "bootm $loadaddr"
495
496#define CONFIG_RAMBOOTCOMMAND \
497 "setenv bootargs root=/dev/ram rw " \
498 "console=$consoledev,$baudrate $othbootargs;" \
499 "tftp $ramdiskaddr $ramdiskfile;" \
500 "tftp $loadaddr $bootfile;" \
501 "bootm $loadaddr $ramdiskaddr"
502
503#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000504
505#endif /* __CONFIG_H */