wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 2 | * Copyright 2004 Freescale Semiconductor. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * (C) Copyright 2002,2003 Motorola,Inc. |
| 4 | * Xianghua Xiao <X.Xiao@motorola.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 25 | /* |
| 26 | * mpc8540ads board configuration file |
| 27 | * |
| 28 | * Please refer to doc/README.mpc85xx for more info. |
| 29 | * |
| 30 | * Make sure you change the MAC address and other network params first, |
| 31 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 32 | */ |
| 33 | |
| 34 | #ifndef __CONFIG_H |
| 35 | #define __CONFIG_H |
| 36 | |
| 37 | /* High Level Configuration Options */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 38 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 39 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 40 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
| 41 | #define CONFIG_MPC8540 1 /* MPC8540 specific */ |
| 42 | #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 43 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 44 | #define CONFIG_PCI |
| 45 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 46 | #define CONFIG_ENV_OVERWRITE |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 47 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 48 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 49 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
| 50 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 51 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 52 | /* |
| 53 | * Use Localbus SDRAM to emulate flash before we can program the flash. |
| 54 | * Normally you need a flash-boot image(u-boot.bin). |
| 55 | * If unsure #undef this. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 56 | */ |
| 57 | #undef CONFIG_RAM_AS_FLASH |
| 58 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 59 | /* |
| 60 | * sysclk for MPC85xx |
| 61 | * |
| 62 | * Two valid values are: |
| 63 | * 33000000 |
| 64 | * 66000000 |
| 65 | * |
| 66 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz |
| 67 | * is likely the desired value here. The board, however, can run and |
| 68 | * defaults to 66Mhz. In any event, this value must match the settings |
| 69 | * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well. |
| 70 | * |
| 71 | * SW17[8] ------+ SW6 |
| 72 | * SW15[1] ----+ | [0:1] |
| 73 | * V V V V |
| 74 | * 33MHz 1 1 1 0 |
| 75 | * 66MHz 0 0 0 1 |
| 76 | */ |
| 77 | |
| 78 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 79 | |
| 80 | |
| 81 | #if !defined(CONFIG_SPD_EEPROM) |
| 82 | #define CONFIG_DDR_SETTING /* manually set up DDR parameters */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 83 | #endif |
| 84 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 85 | /* |
| 86 | * These can be toggled for performance analysis, otherwise use default. |
| 87 | */ |
| 88 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 89 | #define CONFIG_BTB /* toggle branch predition */ |
| 90 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 91 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 92 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 93 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 94 | #undef CFG_DRAM_TEST /* memory test, takes time */ |
| 95 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 96 | #define CFG_MEMTEST_END 0x00400000 |
| 97 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 98 | |
| 99 | /* |
| 100 | * Base addresses -- Note these are effective addresses where the |
| 101 | * actual resources get mapped (not physical addresses) |
| 102 | */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 103 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 104 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
| 105 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 106 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 107 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 108 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 109 | #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 110 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 111 | /* |
| 112 | * SDRAM on the Local Bus |
| 113 | */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 114 | #if defined(CONFIG_RAM_AS_FLASH) |
| 115 | #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
| 116 | #else |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 117 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 118 | #endif |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 119 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 120 | |
| 121 | #if defined(CONFIG_RAM_AS_FLASH) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 122 | #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 123 | #define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ |
| 124 | #else /* Boot from real Flash */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 125 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
| 126 | #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 127 | #endif |
| 128 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 129 | #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
| 130 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
| 131 | #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 132 | #undef CFG_FLASH_CHECKSUM |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 133 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 134 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 135 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 136 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 137 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 138 | |
| 139 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 140 | #define CFG_RAMBOOT |
| 141 | #else |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 142 | #undef CFG_RAMBOOT |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 143 | #endif |
| 144 | |
| 145 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
| 146 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 147 | #undef CONFIG_CLOCKS_IN_MHZ |
| 148 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 149 | #if defined(CONFIG_DDR_SETTING) |
| 150 | #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ |
| 151 | #define CFG_DDR_CS0_CONFIG 0x80000002 |
| 152 | #define CFG_DDR_TIMING_1 0x37344321 |
| 153 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
| 154 | #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
| 155 | #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
| 156 | #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ |
| 157 | #endif |
| 158 | |
| 159 | |
| 160 | /* |
| 161 | * Local Bus Definitions |
| 162 | */ |
| 163 | |
| 164 | /* |
| 165 | * Base Register 2 and Option Register 2 configure SDRAM. |
| 166 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
| 167 | * |
| 168 | * For BR2, need: |
| 169 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 170 | * port-size = 32-bits = BR2[19:20] = 11 |
| 171 | * no parity checking = BR2[21:22] = 00 |
| 172 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 173 | * Valid = BR[31] = 1 |
| 174 | * |
| 175 | * 0 4 8 12 16 20 24 28 |
| 176 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 177 | * |
| 178 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
| 179 | * FIXME: the top 17 bits of BR2. |
| 180 | */ |
| 181 | |
| 182 | #define CFG_BR2_PRELIM 0xf0001861 |
| 183 | |
| 184 | /* |
| 185 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
| 186 | * |
| 187 | * For OR2, need: |
| 188 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 189 | * XAM, OR2[17:18] = 11 |
| 190 | * 9 columns OR2[19-21] = 010 |
| 191 | * 13 rows OR2[23-25] = 100 |
| 192 | * EAD set for extra time OR[31] = 1 |
| 193 | * |
| 194 | * 0 4 8 12 16 20 24 28 |
| 195 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 196 | */ |
| 197 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 198 | #define CFG_OR2_PRELIM 0xfc006901 |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 199 | |
| 200 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 201 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ |
| 202 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 203 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ |
| 204 | |
| 205 | /* |
| 206 | * LSDMR masks |
| 207 | */ |
| 208 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
| 209 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
| 210 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
| 211 | #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) |
| 212 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
| 213 | #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) |
| 214 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
| 215 | #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) |
| 216 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
| 217 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
| 218 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
| 219 | #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) |
| 220 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
| 221 | #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) |
| 222 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
| 223 | |
| 224 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
| 225 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
| 226 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
| 227 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
| 228 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
| 229 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
| 230 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
| 231 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
| 232 | |
| 233 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ |
| 234 | | CFG_LBC_LSDMR_RFCR5 \ |
| 235 | | CFG_LBC_LSDMR_PRETOACT3 \ |
| 236 | | CFG_LBC_LSDMR_ACTTORW3 \ |
| 237 | | CFG_LBC_LSDMR_BL8 \ |
| 238 | | CFG_LBC_LSDMR_WRC2 \ |
| 239 | | CFG_LBC_LSDMR_CL3 \ |
| 240 | | CFG_LBC_LSDMR_RFEN \ |
| 241 | ) |
| 242 | |
| 243 | /* |
| 244 | * SDRAM Controller configuration sequence. |
| 245 | */ |
| 246 | #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
| 247 | | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/ |
| 248 | #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
| 249 | | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ |
| 250 | #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
| 251 | | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/ |
| 252 | #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
| 253 | | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/ |
| 254 | #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
| 255 | | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/ |
| 256 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 257 | |
| 258 | #if defined(CONFIG_RAM_AS_FLASH) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 259 | #define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 260 | #else |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 261 | #define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 262 | #endif |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 263 | #define CFG_OR4_PRELIM 0xffffe1f1 |
| 264 | #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 265 | |
| 266 | #define CONFIG_L1_INIT_RAM |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 267 | #define CFG_INIT_RAM_LOCK 1 |
| 268 | #define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ |
| 269 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 270 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 271 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 272 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 273 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 274 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 275 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 276 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 277 | |
| 278 | /* Serial Port */ |
| 279 | #define CONFIG_CONS_INDEX 1 |
| 280 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 281 | #define CFG_NS16550 |
| 282 | #define CFG_NS16550_SERIAL |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 283 | #define CFG_NS16550_REG_SIZE 1 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 284 | #define CFG_NS16550_CLK get_bus_freq(0) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 285 | |
| 286 | #define CFG_BAUDRATE_TABLE \ |
| 287 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 288 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 289 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
| 290 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 291 | |
| 292 | /* Use the HUSH parser */ |
| 293 | #define CFG_HUSH_PARSER |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 294 | #ifdef CFG_HUSH_PARSER |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 295 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 296 | #endif |
| 297 | |
| 298 | /* I2C */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 299 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
| 300 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 301 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 302 | #define CFG_I2C_SLAVE 0x7F |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 303 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 304 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 305 | /* RapidIO MMU */ |
| 306 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ |
| 307 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE |
| 308 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ |
| 309 | |
| 310 | /* |
| 311 | * General PCI |
| 312 | * Addresses are mapped 1-1. |
| 313 | */ |
| 314 | #define CFG_PCI1_MEM_BASE 0x80000000 |
| 315 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
| 316 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 317 | #define CFG_PCI1_IO_BASE 0xe2000000 |
| 318 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
| 319 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
| 320 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 321 | #if defined(CONFIG_PCI) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 322 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 323 | #define CONFIG_NET_MULTI |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 324 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 325 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 326 | #undef CONFIG_EEPRO100 |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 327 | #undef CONFIG_TULIP |
| 328 | |
| 329 | #if !defined(CONFIG_PCI_PNP) |
| 330 | #define PCI_ENET0_IOADDR 0xe0000000 |
| 331 | #define PCI_ENET0_MEMADDR 0xe0000000 |
| 332 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 333 | #endif |
| 334 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 335 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 336 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
| 337 | |
| 338 | #endif /* CONFIG_PCI */ |
| 339 | |
| 340 | |
| 341 | #if defined(CONFIG_TSEC_ENET) |
| 342 | |
| 343 | #ifndef CONFIG_NET_MULTI |
| 344 | #define CONFIG_NET_MULTI 1 |
| 345 | #endif |
| 346 | |
| 347 | #define CONFIG_MII 1 /* MII PHY management */ |
| 348 | #define CONFIG_MPC85XX_TSEC1 1 |
| 349 | #define CONFIG_MPC85XX_TSEC2 1 |
| 350 | #define CONFIG_MPC85XX_FEC 1 |
| 351 | #define TSEC1_PHY_ADDR 0 |
| 352 | #define TSEC2_PHY_ADDR 1 |
| 353 | #define FEC_PHY_ADDR 3 |
| 354 | #define TSEC1_PHYIDX 0 |
| 355 | #define TSEC2_PHYIDX 0 |
| 356 | #define FEC_PHYIDX 0 |
| 357 | #define CONFIG_ETHPRIME "MOTO ENET0" |
| 358 | |
| 359 | #endif /* CONFIG_TSEC_ENET */ |
| 360 | |
| 361 | |
| 362 | /* |
| 363 | * Environment |
| 364 | */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 365 | #ifndef CFG_RAMBOOT |
| 366 | #if defined(CONFIG_RAM_AS_FLASH) |
| 367 | #define CFG_ENV_IS_NOWHERE |
| 368 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) |
| 369 | #define CFG_ENV_SIZE 0x2000 |
| 370 | #else |
| 371 | #define CFG_ENV_IS_IN_FLASH 1 |
| 372 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 373 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 374 | #endif |
| 375 | #define CFG_ENV_SIZE 0x2000 |
| 376 | #else |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 377 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ |
| 378 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 379 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
| 380 | #define CFG_ENV_SIZE 0x2000 |
| 381 | #endif |
| 382 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 383 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 384 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 385 | |
| 386 | #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) |
| 387 | #if defined(CONFIG_PCI) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 388 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
| 389 | | CFG_CMD_PING \ |
| 390 | | CFG_CMD_PCI \ |
| 391 | | CFG_CMD_I2C) \ |
| 392 | & \ |
| 393 | ~(CFG_CMD_ENV \ |
| 394 | | CFG_CMD_LOADS)) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 395 | #else |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 396 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
| 397 | | CFG_CMD_PING \ |
| 398 | | CFG_CMD_I2C) \ |
| 399 | & \ |
| 400 | ~(CFG_CMD_ENV \ |
| 401 | | CFG_CMD_LOADS)) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 402 | #endif |
| 403 | #else |
| 404 | #if defined(CONFIG_PCI) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 405 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
| 406 | | CFG_CMD_PCI \ |
| 407 | | CFG_CMD_PING \ |
| 408 | | CFG_CMD_I2C) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 409 | #else |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 410 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
| 411 | | CFG_CMD_PING \ |
| 412 | | CFG_CMD_I2C) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 413 | #endif |
| 414 | #endif |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 415 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 416 | #include <cmd_confdefs.h> |
| 417 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 418 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 419 | |
| 420 | /* |
| 421 | * Miscellaneous configurable options |
| 422 | */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 423 | #define CFG_LONGHELP /* undef to save memory */ |
| 424 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
| 425 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 426 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 427 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 428 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 429 | #else |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 430 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 431 | #endif |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 432 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 433 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 434 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 435 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 436 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 437 | |
| 438 | /* |
| 439 | * For booting Linux, the board info and command line data |
| 440 | * have to be in the first 8 MB of memory, since this is |
| 441 | * the maximum mapped by the Linux kernel during initialization. |
| 442 | */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 443 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 444 | |
| 445 | /* Cache Configuration */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 446 | #define CFG_DCACHE_SIZE 32768 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 447 | #define CFG_CACHELINE_SIZE 32 |
| 448 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 449 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 450 | #endif |
| 451 | |
| 452 | /* |
| 453 | * Internal Definitions |
| 454 | * |
| 455 | * Boot Flags |
| 456 | */ |
| 457 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 458 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 459 | |
| 460 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 461 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 462 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 463 | #endif |
| 464 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 465 | /*****************************/ |
| 466 | /* Environment Configuration */ |
| 467 | /*****************************/ |
| 468 | |
| 469 | /* The mac addresses for all ethernet interface */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 470 | #if defined(CONFIG_TSEC_ENET) |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 471 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
| 472 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
| 473 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 474 | #endif |
| 475 | |
wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame^] | 476 | #define CONFIG_IPADDR 192.168.1.253 |
| 477 | |
| 478 | #define CONFIG_HOSTNAME unknown |
| 479 | #define CONFIG_ROOTPATH /nfsroot |
| 480 | #define CONFIG_BOOTFILE your.uImage |
| 481 | |
| 482 | #define CONFIG_SERVERIP 192.168.1.1 |
| 483 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 484 | #define CONFIG_NETMASK 255.255.255.0 |
| 485 | |
| 486 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
| 487 | |
| 488 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 489 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 490 | |
| 491 | #define CONFIG_BAUDRATE 115200 |
| 492 | |
| 493 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 494 | "netdev=eth0\0" \ |
| 495 | "consoledev=ttyS0\0" \ |
| 496 | "ramdiskaddr=400000\0" \ |
| 497 | "ramdiskfile=your.ramdisk.u-boot\0" |
| 498 | |
| 499 | #define CONFIG_NFSBOOTCOMMAND \ |
| 500 | "setenv bootargs root=/dev/nfs rw " \ |
| 501 | "nfsroot=$serverip:$rootpath " \ |
| 502 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 503 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 504 | "tftp $loadaddr $bootfile;" \ |
| 505 | "bootm $loadaddr" |
| 506 | |
| 507 | #define CONFIG_RAMBOOTCOMMAND \ |
| 508 | "setenv bootargs root=/dev/ram rw " \ |
| 509 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 510 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 511 | "tftp $loadaddr $bootfile;" \ |
| 512 | "bootm $loadaddr $ramdiskaddr" |
| 513 | |
| 514 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 515 | |
| 516 | #endif /* __CONFIG_H */ |