blob: 1769b6ea881b2f909a0799237869754fd1c777f3 [file] [log] [blame]
Simon Glassdde3b702012-02-23 03:28:41 +00001/*
2 * Copyright (c) 2004-2008 Texas Instruments
3 *
4 * (C) Copyright 2002
5 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Simon Glassdde3b702012-02-23 03:28:41 +00008 */
9
Marc Zyngierbf433af2014-07-12 14:24:02 +010010#include <config.h>
11
Simon Glassdde3b702012-02-23 03:28:41 +000012OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
13OUTPUT_ARCH(arm)
14ENTRY(_start)
15SECTIONS
16{
Simon Glassc1352112016-03-13 19:07:29 -060017#ifndef CONFIG_CMDLINE
18 /DISCARD/ : { *(.u_boot_list_2_cmd_*) }
19#endif
Wang Dongshengc5e954e2016-01-18 11:02:40 +080020#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
Peng Fand47cb0b2015-10-23 10:13:03 +080021 /*
Wang Dongshengc5e954e2016-01-18 11:02:40 +080022 * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not
23 * bundle with u-boot, and code offsets are fixed. Secure zone
24 * only needs to be copied from the loading address to
25 * CONFIG_ARMV7_SECURE_BASE, which is the linking and running
26 * address for secure code.
Peng Fand47cb0b2015-10-23 10:13:03 +080027 *
Wang Dongshengc5e954e2016-01-18 11:02:40 +080028 * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will
29 * be included in u-boot address space, and some absolute address
30 * were used in secure code. The absolute addresses of the secure
31 * code also needs to be relocated along with the accompanying u-boot
32 * code.
33 *
34 * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE.
Peng Fand47cb0b2015-10-23 10:13:03 +080035 */
36 /DISCARD/ : { *(.rel._secure*) }
Wang Dongshengc5e954e2016-01-18 11:02:40 +080037#endif
Simon Glassdde3b702012-02-23 03:28:41 +000038 . = 0x00000000;
39
40 . = ALIGN(4);
41 .text :
42 {
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020043 *(.__image_copy_start)
Albert ARIBAUD41623c92014-04-15 16:13:51 +020044 *(.vectors)
Stephen Warrenb68d6712012-10-22 06:19:32 +000045 CPUDIR/start.o (.text*)
46 *(.text*)
Simon Glassdde3b702012-02-23 03:28:41 +000047 }
48
Jan Kiszka104d6fb2015-04-21 07:18:24 +020049#ifdef CONFIG_ARMV7_NONSEC
Marc Zyngierbf433af2014-07-12 14:24:02 +010050
51#ifndef CONFIG_ARMV7_SECURE_BASE
52#define CONFIG_ARMV7_SECURE_BASE
Chen-Yu Tsaib56e06d2016-06-07 10:54:27 +080053#define __ARMV7_PSCI_STACK_IN_RAM
Marc Zyngierbf433af2014-07-12 14:24:02 +010054#endif
55
56 .__secure_start : {
57 . = ALIGN(0x1000);
58 *(.__secure_start)
59 }
60
61 .secure_text CONFIG_ARMV7_SECURE_BASE :
62 AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
63 {
64 *(._secure.text)
65 }
66
67 . = LOADADDR(.__secure_start) +
68 SIZEOF(.__secure_start) +
69 SIZEOF(.secure_text);
70
Chen-Yu Tsaib56e06d2016-06-07 10:54:27 +080071#ifdef __ARMV7_PSCI_STACK_IN_RAM
72 /* Align to page boundary and skip 2 pages */
73 . = (. & ~ 0xfff) + 0x2000;
74#undef __ARMV7_PSCI_STACK_IN_RAM
75#endif
76
Marc Zyngierbf433af2014-07-12 14:24:02 +010077 __secure_end_lma = .;
78 .__secure_end : AT(__secure_end_lma) {
79 *(.__secure_end)
80 LONG(0x1d1071c); /* Must output something to reset LMA */
81 }
82#endif
83
Simon Glassdde3b702012-02-23 03:28:41 +000084 . = ALIGN(4);
85 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
86
87 . = ALIGN(4);
88 .data : {
Stephen Warrenb68d6712012-10-22 06:19:32 +000089 *(.data*)
Simon Glassdde3b702012-02-23 03:28:41 +000090 }
91
92 . = ALIGN(4);
93
94 . = .;
Simon Glassdde3b702012-02-23 03:28:41 +000095
96 . = ALIGN(4);
Marek Vasut55675142012-10-12 10:27:03 +000097 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +000098 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +000099 }
100
101 . = ALIGN(4);
Simon Glassdde3b702012-02-23 03:28:41 +0000102
Alexander Graf50149ea2016-03-04 01:10:01 +0100103 .__efi_runtime_start : {
104 *(.__efi_runtime_start)
105 }
106
107 .efi_runtime : {
108 *(efi_runtime_text)
109 *(efi_runtime_data)
110 }
111
112 .__efi_runtime_stop : {
113 *(.__efi_runtime_stop)
114 }
115
116 .efi_runtime_rel_start :
117 {
118 *(.__efi_runtime_rel_start)
119 }
120
121 .efi_runtime_rel : {
122 *(.relefi_runtime_text)
123 *(.relefi_runtime_data)
124 }
125
126 .efi_runtime_rel_stop :
127 {
128 *(.__efi_runtime_rel_stop)
129 }
130
131 . = ALIGN(4);
132
Albert ARIBAUDd026dec2013-06-11 14:17:33 +0200133 .image_copy_end :
134 {
135 *(.__image_copy_end)
136 }
Simon Glassdde3b702012-02-23 03:28:41 +0000137
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +0200138 .rel_dyn_start :
139 {
140 *(.__rel_dyn_start)
141 }
142
Simon Glassdde3b702012-02-23 03:28:41 +0000143 .rel.dyn : {
Simon Glassdde3b702012-02-23 03:28:41 +0000144 *(.rel*)
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +0200145 }
146
147 .rel_dyn_end :
148 {
149 *(.__rel_dyn_end)
Simon Glassdde3b702012-02-23 03:28:41 +0000150 }
151
Albert ARIBAUDd0b5d9d2014-02-22 17:53:42 +0100152 .end :
153 {
154 *(.__end)
155 }
156
157 _image_binary_end = .;
Simon Glassdde3b702012-02-23 03:28:41 +0000158
159 /*
160 * Deprecated: this MMU section is used by pxa at present but
161 * should not be used by new boards/CPUs.
162 */
163 . = ALIGN(4096);
164 .mmutable : {
165 *(.mmutable)
166 }
167
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000168/*
169 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
170 * __bss_base and __bss_limit are for linker only (overlay ordering)
171 */
172
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000173 .bss_start __rel_dyn_start (OVERLAY) : {
174 KEEP(*(.__bss_start));
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000175 __bss_base = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000176 }
177
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000178 .bss __bss_base (OVERLAY) : {
Stephen Warrenb68d6712012-10-22 06:19:32 +0000179 *(.bss*)
Simon Glassdde3b702012-02-23 03:28:41 +0000180 . = ALIGN(4);
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000181 __bss_limit = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000182 }
Tom Rini0ce033d2013-03-18 12:31:00 -0400183
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000184 .bss_end __bss_limit (OVERLAY) : {
185 KEEP(*(.__bss_end));
Simon Glassdde3b702012-02-23 03:28:41 +0000186 }
187
Albert ARIBAUDd0b5d9d2014-02-22 17:53:42 +0100188 .dynsym _image_binary_end : { *(.dynsym) }
Albert ARIBAUD47ed5dd2013-11-07 14:21:46 +0100189 .dynbss : { *(.dynbss) }
190 .dynstr : { *(.dynstr*) }
191 .dynamic : { *(.dynamic*) }
192 .plt : { *(.plt*) }
193 .interp : { *(.interp*) }
Andreas Färber2c67e0e2014-01-27 05:48:11 +0100194 .gnu.hash : { *(.gnu.hash) }
Albert ARIBAUD47ed5dd2013-11-07 14:21:46 +0100195 .gnu : { *(.gnu*) }
196 .ARM.exidx : { *(.ARM.exidx*) }
Albert ARIBAUDb02bfc42014-01-13 14:57:05 +0100197 .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
Simon Glassdde3b702012-02-23 03:28:41 +0000198}