blob: 4da5d246e0ef78ce36f6d8520b11932200ac41d8 [file] [log] [blame]
Simon Glassdde3b702012-02-23 03:28:41 +00001/*
2 * Copyright (c) 2004-2008 Texas Instruments
3 *
4 * (C) Copyright 2002
5 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Simon Glassdde3b702012-02-23 03:28:41 +00008 */
9
10OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
11OUTPUT_ARCH(arm)
12ENTRY(_start)
13SECTIONS
14{
15 . = 0x00000000;
16
17 . = ALIGN(4);
18 .text :
19 {
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020020 *(.__image_copy_start)
Stephen Warrenb68d6712012-10-22 06:19:32 +000021 CPUDIR/start.o (.text*)
22 *(.text*)
Simon Glassdde3b702012-02-23 03:28:41 +000023 }
24
25 . = ALIGN(4);
26 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
27
28 . = ALIGN(4);
29 .data : {
Stephen Warrenb68d6712012-10-22 06:19:32 +000030 *(.data*)
Simon Glassdde3b702012-02-23 03:28:41 +000031 }
32
33 . = ALIGN(4);
34
35 . = .;
Simon Glassdde3b702012-02-23 03:28:41 +000036
37 . = ALIGN(4);
Marek Vasut55675142012-10-12 10:27:03 +000038 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +000039 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +000040 }
41
42 . = ALIGN(4);
Simon Glassdde3b702012-02-23 03:28:41 +000043
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020044 .image_copy_end :
45 {
46 *(.__image_copy_end)
47 }
Simon Glassdde3b702012-02-23 03:28:41 +000048
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +020049 .rel_dyn_start :
50 {
51 *(.__rel_dyn_start)
52 }
53
Simon Glassdde3b702012-02-23 03:28:41 +000054 .rel.dyn : {
Simon Glassdde3b702012-02-23 03:28:41 +000055 *(.rel*)
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +020056 }
57
58 .rel_dyn_end :
59 {
60 *(.__rel_dyn_end)
Simon Glassdde3b702012-02-23 03:28:41 +000061 }
62
Simon Glassdde3b702012-02-23 03:28:41 +000063 _end = .;
64
65 /*
66 * Deprecated: this MMU section is used by pxa at present but
67 * should not be used by new boards/CPUs.
68 */
69 . = ALIGN(4096);
70 .mmutable : {
71 *(.mmutable)
72 }
73
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000074/*
75 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
76 * __bss_base and __bss_limit are for linker only (overlay ordering)
77 */
78
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000079 .bss_start __rel_dyn_start (OVERLAY) : {
80 KEEP(*(.__bss_start));
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000081 __bss_base = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000082 }
83
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000084 .bss __bss_base (OVERLAY) : {
Stephen Warrenb68d6712012-10-22 06:19:32 +000085 *(.bss*)
Simon Glassdde3b702012-02-23 03:28:41 +000086 . = ALIGN(4);
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000087 __bss_limit = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000088 }
Tom Rini0ce033d2013-03-18 12:31:00 -040089
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000090 .bss_end __bss_limit (OVERLAY) : {
91 KEEP(*(.__bss_end));
Simon Glassdde3b702012-02-23 03:28:41 +000092 }
93
Albert ARIBAUD47ed5dd2013-11-07 14:21:46 +010094 .dynsym _end : { *(.dynsym) }
Albert ARIBAUD47ed5dd2013-11-07 14:21:46 +010095 .dynbss : { *(.dynbss) }
96 .dynstr : { *(.dynstr*) }
97 .dynamic : { *(.dynamic*) }
98 .plt : { *(.plt*) }
99 .interp : { *(.interp*) }
100 .gnu : { *(.gnu*) }
101 .ARM.exidx : { *(.ARM.exidx*) }
Albert ARIBAUDb02bfc42014-01-13 14:57:05 +0100102 .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
Simon Glassdde3b702012-02-23 03:28:41 +0000103}