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wdenk48c00102002-10-26 17:39:47 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2002-2005
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
wdenk48c00102002-10-26 17:39:47 +00004 * (C) Copyright 2002
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
Detlev Zundel792a09e2009-05-13 10:54:10 +02007 * Gary Jennejohn <garyj@denx.de>
wdenk48c00102002-10-26 17:39:47 +00008 *
9 * Configuation settings for the SAMSUNG board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenk48c00102002-10-26 17:39:47 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_ARM920T 1 /* This is an ARM920T core */
38#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
39#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
40
41/* input clock of PLL */
wdenk7f6c2cb2002-11-10 22:06:23 +000042#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
wdenk48c00102002-10-26 17:39:47 +000043#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44
45#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
46#define CONFIG_SETUP_MEMORY_TAGS 1
47#define CONFIG_INITRD_TAG 1
48
49
50/*
51 * Size of malloc() pool
52 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
54#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk48c00102002-10-26 17:39:47 +000055
56/*
57 * Hardware drivers
58 */
59#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
60#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */
61#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
62
63/*
64 * select serial console configuration
65 */
Jean-Christophe PLAGNIOL-VILLARD300f99f2009-03-30 18:58:39 +020066#define CONFIG_S3C24X0_SERIAL
wdenk48c00102002-10-26 17:39:47 +000067#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SAMSUNG */
68
69#undef CONFIG_HWFLOW /* include RTS/CTS flow control support */
70
71#undef CONFIG_MODEM_SUPPORT /* enable modem initialization stuff */
72
73/*
74 * The following enables modem debugging stuff. The dbg() and
75 * 'char screen[1024]' are used for debug printfs. Unfortunately,
76 * it is usable only from BDI
77 */
78#undef CONFIG_MODEM_SUPPORT_DEBUG
79
80/* allow to overwrite serial and ethaddr */
81#define CONFIG_ENV_OVERWRITE
82
83#define CONFIG_BAUDRATE 115200
84
85#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
86
wdenk48b42612003-06-19 23:01:32 +000087/* Use s3c2400's RTC */
88#define CONFIG_RTC_S3C24X0 1
89
Jon Loeliger46da1e92007-07-04 22:33:30 -050090
91/*
Jon Loeliger079a1362007-07-10 10:12:10 -050092 * BOOTP options
93 */
94#define CONFIG_BOOTP_BOOTFILESIZE
95#define CONFIG_BOOTP_BOOTPATH
96#define CONFIG_BOOTP_GATEWAY
97#define CONFIG_BOOTP_HOSTNAME
98
99
100/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500101 * Command line configuration.
102 */
103#include <config_cmd_default.h>
104
105#define CONFIG_CMD_DATE
106#define CONFIG_CMD_SNTP
107
108#if defined(CONFIG_HWFLOW)
109 #define CONFIG_CONFIG_HWFLOW
wdenk48c00102002-10-26 17:39:47 +0000110#endif
111
Jon Loeliger46da1e92007-07-04 22:33:30 -0500112#if !defined(USE_920T_MMU)
113 #undef CONFIG_CMD_CACHE
wdenk48c00102002-10-26 17:39:47 +0000114#endif
115
wdenk48c00102002-10-26 17:39:47 +0000116
117#define CONFIG_BOOTDELAY 3
wdenk48c00102002-10-26 17:39:47 +0000118#define CONFIG_NETMASK 255.255.255.0
119#define CONFIG_IPADDR 134.98.93.36
120#define CONFIG_SERVERIP 134.98.93.22
wdenk48c00102002-10-26 17:39:47 +0000121
Jon Loeliger46da1e92007-07-04 22:33:30 -0500122#if defined(CONFIG_CMD_KGDB)
wdenk48c00102002-10-26 17:39:47 +0000123#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
124/* what's this ? it's not used anywhere */
125#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
126#endif
127
128/*
129 * Miscellaneous configurable options
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LONGHELP /* undef to save memory */
132#define CONFIG_SYS_PROMPT "SMDK2400 # " /* Monitor Command Prompt */
133#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
135#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk48c00102002-10-26 17:39:47 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x0c000000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x0e000000 /* 32 MB in DRAM */
wdenk48c00102002-10-26 17:39:47 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_LOAD_ADDR 0x0cf00000 /* default load address */
wdenk48c00102002-10-26 17:39:47 +0000142
143/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
144/* it to wrap 100 times (total 1562500) to get 1 sec. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_HZ 1562500
wdenk48c00102002-10-26 17:39:47 +0000146
147/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk48c00102002-10-26 17:39:47 +0000149
150/*-----------------------------------------------------------------------
151 * Stack sizes
152 *
153 * The stack sizes are set up in start.S using the settings below
154 */
155#define CONFIG_STACKSIZE (128*1024) /* regular stack */
156#ifdef CONFIG_USE_IRQ
157#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
158#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
159#endif
160
161/*-----------------------------------------------------------------------
162 * Physical Memory Map
163 */
164#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
165#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
166#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */
wdenk48c00102002-10-26 17:39:47 +0000169
170/*-----------------------------------------------------------------------
171 * FLASH and environment organization
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
174#define CONFIG_SYS_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
wdenk48c00102002-10-26 17:39:47 +0000175
176/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
178#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk48c00102002-10-26 17:39:47 +0000179
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200180#define CONFIG_ENV_IS_IN_FLASH 1
wdenk48c00102002-10-26 17:39:47 +0000181
182/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200184#define CONFIG_ENV_SIZE 0x40000
wdenk48c00102002-10-26 17:39:47 +0000185
186/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
188#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk48c00102002-10-26 17:39:47 +0000189
190#endif /* __CONFIG_H */