blob: f8dc5f57ce16af300ffa362b8c550ab32dc14ec0 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasute94cad92018-04-08 15:22:58 +02002/*
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
Marek Vasute94cad92018-04-08 15:22:58 +02004 */
5
6#include <common.h>
7#include <clk.h>
8#include <fdtdec.h>
9#include <mmc.h>
10#include <dm.h>
11#include <linux/compat.h>
12#include <linux/dma-direction.h>
13#include <linux/io.h>
14#include <linux/sizes.h>
15#include <power/regulator.h>
16#include <asm/unaligned.h>
17
Marek Vasutcb0b6b02018-04-13 23:51:33 +020018#include "tmio-common.h"
Marek Vasute94cad92018-04-08 15:22:58 +020019
Marek Vasutf63968b2018-04-08 19:09:17 +020020#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
21
22/* SCC registers */
23#define RENESAS_SDHI_SCC_DTCNTL 0x800
24#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
25#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
26#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
27#define RENESAS_SDHI_SCC_TAPSET 0x804
28#define RENESAS_SDHI_SCC_DT2FF 0x808
29#define RENESAS_SDHI_SCC_CKSEL 0x80c
30#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
31#define RENESAS_SDHI_SCC_RVSCNTL 0x810
32#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
33#define RENESAS_SDHI_SCC_RVSREQ 0x814
34#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
35#define RENESAS_SDHI_SCC_SMPCMP 0x818
36#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
37
38#define RENESAS_SDHI_MAX_TAP 3
39
Marek Vasutcb0b6b02018-04-13 23:51:33 +020040static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
Marek Vasutf63968b2018-04-08 19:09:17 +020041{
42 u32 reg;
43
44 /* Initialize SCC */
Marek Vasutcb0b6b02018-04-13 23:51:33 +020045 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
Marek Vasutf63968b2018-04-08 19:09:17 +020046
Marek Vasutcb0b6b02018-04-13 23:51:33 +020047 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
48 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
49 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020050
51 /* Set sampling clock selection range */
Marek Vasutcb0b6b02018-04-13 23:51:33 +020052 tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
Marek Vasutf63968b2018-04-08 19:09:17 +020053 RENESAS_SDHI_SCC_DTCNTL);
54
Marek Vasutcb0b6b02018-04-13 23:51:33 +020055 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020056 reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +020057 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020058
Marek Vasutcb0b6b02018-04-13 23:51:33 +020059 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +020060 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
Marek Vasutcb0b6b02018-04-13 23:51:33 +020061 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +020062
Marek Vasutcb0b6b02018-04-13 23:51:33 +020063 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020064 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +020065 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020066
Marek Vasutcb0b6b02018-04-13 23:51:33 +020067 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
Marek Vasutf63968b2018-04-08 19:09:17 +020068 RENESAS_SDHI_SCC_DT2FF);
69
Marek Vasutcb0b6b02018-04-13 23:51:33 +020070 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
71 reg |= TMIO_SD_CLKCTL_SCLKEN;
72 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020073
74 /* Read TAPNUM */
Marek Vasutcb0b6b02018-04-13 23:51:33 +020075 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
Marek Vasutf63968b2018-04-08 19:09:17 +020076 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
77 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
78}
79
Marek Vasutcb0b6b02018-04-13 23:51:33 +020080static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
Marek Vasutf63968b2018-04-08 19:09:17 +020081{
82 u32 reg;
83
84 /* Reset SCC */
Marek Vasutcb0b6b02018-04-13 23:51:33 +020085 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
86 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
87 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020088
Marek Vasutcb0b6b02018-04-13 23:51:33 +020089 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +020090 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
Marek Vasutcb0b6b02018-04-13 23:51:33 +020091 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +020092
Marek Vasutcb0b6b02018-04-13 23:51:33 +020093 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
94 reg |= TMIO_SD_CLKCTL_SCLKEN;
95 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020096
Marek Vasutcb0b6b02018-04-13 23:51:33 +020097 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +020098 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +020099 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200100
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200101 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200102 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200103 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200104}
105
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200106static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
Marek Vasutf63968b2018-04-08 19:09:17 +0200107 unsigned long tap)
108{
109 /* Set sampling clock position */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200110 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
Marek Vasutf63968b2018-04-08 19:09:17 +0200111}
112
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200113static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
Marek Vasutf63968b2018-04-08 19:09:17 +0200114{
115 /* Get comparison of sampling data */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200116 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
Marek Vasutf63968b2018-04-08 19:09:17 +0200117}
118
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200119static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
Marek Vasutf63968b2018-04-08 19:09:17 +0200120 unsigned int tap_num, unsigned int taps,
121 unsigned int smpcmp)
122{
123 unsigned long tap_cnt; /* counter of tuning success */
124 unsigned long tap_set; /* tap position */
125 unsigned long tap_start;/* start position of tuning success */
126 unsigned long tap_end; /* end position of tuning success */
127 unsigned long ntap; /* temporary counter of tuning success */
128 unsigned long match_cnt;/* counter of matching data */
129 unsigned long i;
130 bool select = false;
131 u32 reg;
132
133 /* Clear SCC_RVSREQ */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200134 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
Marek Vasutf63968b2018-04-08 19:09:17 +0200135
136 /* Merge the results */
137 for (i = 0; i < tap_num * 2; i++) {
138 if (!(taps & BIT(i))) {
139 taps &= ~BIT(i % tap_num);
140 taps &= ~BIT((i % tap_num) + tap_num);
141 }
142 if (!(smpcmp & BIT(i))) {
143 smpcmp &= ~BIT(i % tap_num);
144 smpcmp &= ~BIT((i % tap_num) + tap_num);
145 }
146 }
147
148 /*
149 * Find the longest consecutive run of successful probes. If that
150 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
151 * center index as the tap.
152 */
153 tap_cnt = 0;
154 ntap = 0;
155 tap_start = 0;
156 tap_end = 0;
157 for (i = 0; i < tap_num * 2; i++) {
158 if (taps & BIT(i))
159 ntap++;
160 else {
161 if (ntap > tap_cnt) {
162 tap_start = i - ntap;
163 tap_end = i - 1;
164 tap_cnt = ntap;
165 }
166 ntap = 0;
167 }
168 }
169
170 if (ntap > tap_cnt) {
171 tap_start = i - ntap;
172 tap_end = i - 1;
173 tap_cnt = ntap;
174 }
175
176 /*
177 * If all of the TAP is OK, the sampling clock position is selected by
178 * identifying the change point of data.
179 */
180 if (tap_cnt == tap_num * 2) {
181 match_cnt = 0;
182 ntap = 0;
183 tap_start = 0;
184 tap_end = 0;
185 for (i = 0; i < tap_num * 2; i++) {
186 if (smpcmp & BIT(i))
187 ntap++;
188 else {
189 if (ntap > match_cnt) {
190 tap_start = i - ntap;
191 tap_end = i - 1;
192 match_cnt = ntap;
193 }
194 ntap = 0;
195 }
196 }
197 if (ntap > match_cnt) {
198 tap_start = i - ntap;
199 tap_end = i - 1;
200 match_cnt = ntap;
201 }
202 if (match_cnt)
203 select = true;
204 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
205 select = true;
206
207 if (select)
208 tap_set = ((tap_start + tap_end) / 2) % tap_num;
209 else
210 return -EIO;
211
212 /* Set SCC */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200213 tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
Marek Vasutf63968b2018-04-08 19:09:17 +0200214
215 /* Enable auto re-tuning */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200216 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200217 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200218 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200219
220 return 0;
221}
222
223int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
224{
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200225 struct tmio_sd_priv *priv = dev_get_priv(dev);
Marek Vasutf63968b2018-04-08 19:09:17 +0200226 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
227 struct mmc *mmc = upriv->mmc;
228 unsigned int tap_num;
229 unsigned int taps = 0, smpcmp = 0;
230 int i, ret = 0;
231 u32 caps;
232
233 /* Only supported on Renesas RCar */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200234 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
Marek Vasutf63968b2018-04-08 19:09:17 +0200235 return -EINVAL;
236
237 /* clock tuning is not needed for upto 52MHz */
238 if (!((mmc->selected_mode == MMC_HS_200) ||
239 (mmc->selected_mode == UHS_SDR104) ||
240 (mmc->selected_mode == UHS_SDR50)))
241 return 0;
242
243 tap_num = renesas_sdhi_init_tuning(priv);
244 if (!tap_num)
245 /* Tuning is not supported */
246 goto out;
247
248 if (tap_num * 2 >= sizeof(taps) * 8) {
249 dev_err(dev,
250 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
251 goto out;
252 }
253
254 /* Issue CMD19 twice for each tap */
255 for (i = 0; i < 2 * tap_num; i++) {
256 renesas_sdhi_prepare_tuning(priv, i % tap_num);
257
258 /* Force PIO for the tuning */
259 caps = priv->caps;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200260 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
Marek Vasutf63968b2018-04-08 19:09:17 +0200261
262 ret = mmc_send_tuning(mmc, opcode, NULL);
263
264 priv->caps = caps;
265
266 if (ret == 0)
267 taps |= BIT(i);
268
269 ret = renesas_sdhi_compare_scc_data(priv);
270 if (ret == 0)
271 smpcmp |= BIT(i);
272
273 mdelay(1);
274 }
275
276 ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
277
278out:
279 if (ret < 0) {
280 dev_warn(dev, "Tuning procedure failed\n");
281 renesas_sdhi_reset_tuning(priv);
282 }
283
284 return ret;
285}
286#endif
287
288static int renesas_sdhi_set_ios(struct udevice *dev)
289{
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200290 int ret = tmio_sd_set_ios(dev);
Marek Vasutcf39f3f2018-04-09 20:47:31 +0200291
292 mdelay(10);
293
Marek Vasutf63968b2018-04-08 19:09:17 +0200294#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200295 struct tmio_sd_priv *priv = dev_get_priv(dev);
Marek Vasutf63968b2018-04-08 19:09:17 +0200296
297 renesas_sdhi_reset_tuning(priv);
298#endif
299
300 return ret;
301}
302
Marek Vasute94cad92018-04-08 15:22:58 +0200303static const struct dm_mmc_ops renesas_sdhi_ops = {
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200304 .send_cmd = tmio_sd_send_cmd,
Marek Vasutf63968b2018-04-08 19:09:17 +0200305 .set_ios = renesas_sdhi_set_ios,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200306 .get_cd = tmio_sd_get_cd,
Marek Vasutf63968b2018-04-08 19:09:17 +0200307#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
308 .execute_tuning = renesas_sdhi_execute_tuning,
309#endif
Marek Vasute94cad92018-04-08 15:22:58 +0200310};
311
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200312#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
Marek Vasutf98833d2018-04-08 18:49:52 +0200313#define RENESAS_GEN3_QUIRKS \
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200314 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
Marek Vasutf98833d2018-04-08 18:49:52 +0200315
Marek Vasute94cad92018-04-08 15:22:58 +0200316static const struct udevice_id renesas_sdhi_match[] = {
Marek Vasutf98833d2018-04-08 18:49:52 +0200317 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
318 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
319 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
320 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
321 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
322 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
323 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
324 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
325 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
Marek Vasutd6291522018-04-26 13:19:29 +0200326 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
Marek Vasutf98833d2018-04-08 18:49:52 +0200327 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
Marek Vasute94cad92018-04-08 15:22:58 +0200328 { /* sentinel */ }
329};
330
Marek Vasutc769e602018-04-08 17:45:23 +0200331static int renesas_sdhi_probe(struct udevice *dev)
332{
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900333 struct tmio_sd_priv *priv = dev_get_priv(dev);
Marek Vasutc769e602018-04-08 17:45:23 +0200334 u32 quirks = dev_get_driver_data(dev);
Marek Vasut7cf7ef82018-04-08 18:14:22 +0200335 struct fdt_resource reg_res;
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900336 struct clk clk;
Marek Vasut7cf7ef82018-04-08 18:14:22 +0200337 DECLARE_GLOBAL_DATA_PTR;
338 int ret;
339
Marek Vasutf98833d2018-04-08 18:49:52 +0200340 if (quirks == RENESAS_GEN2_QUIRKS) {
341 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
342 "reg", 0, &reg_res);
343 if (ret < 0) {
344 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
345 ret);
346 return ret;
347 }
Marek Vasut7cf7ef82018-04-08 18:14:22 +0200348
Marek Vasutf98833d2018-04-08 18:49:52 +0200349 if (fdt_resource_size(&reg_res) == 0x100)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200350 quirks |= TMIO_SD_CAP_16BIT;
Marek Vasutf98833d2018-04-08 18:49:52 +0200351 }
Marek Vasutc769e602018-04-08 17:45:23 +0200352
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900353 ret = clk_get_by_index(dev, 0, &clk);
354 if (ret < 0) {
355 dev_err(dev, "failed to get host clock\n");
356 return ret;
357 }
358
359 /* set to max rate */
360 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
361 if (IS_ERR_VALUE(priv->mclk)) {
362 dev_err(dev, "failed to set rate for host clock\n");
363 clk_free(&clk);
364 return priv->mclk;
365 }
366
367 ret = clk_enable(&clk);
368 clk_free(&clk);
369 if (ret) {
370 dev_err(dev, "failed to enable host clock\n");
371 return ret;
372 }
373
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200374 ret = tmio_sd_probe(dev, quirks);
Marek Vasutf63968b2018-04-08 19:09:17 +0200375#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
376 if (!ret)
Marek Vasut65186972018-08-30 15:27:26 +0200377 renesas_sdhi_reset_tuning(priv);
Marek Vasutf63968b2018-04-08 19:09:17 +0200378#endif
379 return ret;
Marek Vasutc769e602018-04-08 17:45:23 +0200380}
381
Marek Vasute94cad92018-04-08 15:22:58 +0200382U_BOOT_DRIVER(renesas_sdhi) = {
383 .name = "renesas-sdhi",
384 .id = UCLASS_MMC,
385 .of_match = renesas_sdhi_match,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200386 .bind = tmio_sd_bind,
Marek Vasutc769e602018-04-08 17:45:23 +0200387 .probe = renesas_sdhi_probe,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200388 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
389 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
Marek Vasute94cad92018-04-08 15:22:58 +0200390 .ops = &renesas_sdhi_ops,
391};