mmc: tmio: Rename Matsushita to TMIO
Synchronize the naming with Linux, call the common code TMIO.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 8564f42..56a43ca 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -16,7 +16,7 @@
#include <power/regulator.h>
#include <asm/unaligned.h>
-#include "matsushita-common.h"
+#include "tmio-common.h"
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
@@ -38,86 +38,86 @@
#define RENESAS_SDHI_MAX_TAP 3
-static unsigned int renesas_sdhi_init_tuning(struct matsu_sd_priv *priv)
+static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
/* Initialize SCC */
- matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
+ tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
- reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
- reg &= ~MATSU_SD_CLKCTL_SCLKEN;
- matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg &= ~TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
/* Set sampling clock selection range */
- matsu_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
+ tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
RENESAS_SDHI_SCC_DTCNTL);
- reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
- matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
- reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
- matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
- reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
- matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
- matsu_sd_writel(priv, 0x300 /* scc_tappos */,
+ tmio_sd_writel(priv, 0x300 /* scc_tappos */,
RENESAS_SDHI_SCC_DT2FF);
- reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
- reg |= MATSU_SD_CLKCTL_SCLKEN;
- matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg |= TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
/* Read TAPNUM */
- return (matsu_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
+ return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
}
-static void renesas_sdhi_reset_tuning(struct matsu_sd_priv *priv)
+static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
{
u32 reg;
/* Reset SCC */
- reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
- reg &= ~MATSU_SD_CLKCTL_SCLKEN;
- matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg &= ~TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
- reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
- matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
- reg = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
- reg |= MATSU_SD_CLKCTL_SCLKEN;
- matsu_sd_writel(priv, reg, MATSU_SD_CLKCTL);
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg |= TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
- reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
- matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
- reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
- matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
}
-static void renesas_sdhi_prepare_tuning(struct matsu_sd_priv *priv,
+static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
unsigned long tap)
{
/* Set sampling clock position */
- matsu_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
+ tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
}
-static unsigned int renesas_sdhi_compare_scc_data(struct matsu_sd_priv *priv)
+static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
{
/* Get comparison of sampling data */
- return matsu_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
+ return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
}
-static int renesas_sdhi_select_tuning(struct matsu_sd_priv *priv,
+static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
unsigned int tap_num, unsigned int taps,
unsigned int smpcmp)
{
@@ -132,7 +132,7 @@
u32 reg;
/* Clear SCC_RVSREQ */
- matsu_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
+ tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
/* Merge the results */
for (i = 0; i < tap_num * 2; i++) {
@@ -211,19 +211,19 @@
return -EIO;
/* Set SCC */
- matsu_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
+ tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
/* Enable auto re-tuning */
- reg = matsu_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
+ reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
- matsu_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+ tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
return 0;
}
int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
{
- struct matsu_sd_priv *priv = dev_get_priv(dev);
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct mmc *mmc = upriv->mmc;
unsigned int tap_num;
@@ -232,7 +232,7 @@
u32 caps;
/* Only supported on Renesas RCar */
- if (!(priv->caps & MATSU_SD_CAP_RCAR_UHS))
+ if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
return -EINVAL;
/* clock tuning is not needed for upto 52MHz */
@@ -258,7 +258,7 @@
/* Force PIO for the tuning */
caps = priv->caps;
- priv->caps &= ~MATSU_SD_CAP_DMA_INTERNAL;
+ priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
ret = mmc_send_tuning(mmc, opcode, NULL);
@@ -288,12 +288,12 @@
static int renesas_sdhi_set_ios(struct udevice *dev)
{
- int ret = matsu_sd_set_ios(dev);
+ int ret = tmio_sd_set_ios(dev);
mdelay(10);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
- struct matsu_sd_priv *priv = dev_get_priv(dev);
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
renesas_sdhi_reset_tuning(priv);
#endif
@@ -302,17 +302,17 @@
}
static const struct dm_mmc_ops renesas_sdhi_ops = {
- .send_cmd = matsu_sd_send_cmd,
+ .send_cmd = tmio_sd_send_cmd,
.set_ios = renesas_sdhi_set_ios,
- .get_cd = matsu_sd_get_cd,
+ .get_cd = tmio_sd_get_cd,
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
.execute_tuning = renesas_sdhi_execute_tuning,
#endif
};
-#define RENESAS_GEN2_QUIRKS MATSU_SD_CAP_RCAR_GEN2
+#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
#define RENESAS_GEN3_QUIRKS \
- MATSU_SD_CAP_64BIT | MATSU_SD_CAP_RCAR_GEN3 | MATSU_SD_CAP_RCAR_UHS
+ TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
static const struct udevice_id renesas_sdhi_match[] = {
{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
@@ -345,10 +345,10 @@
}
if (fdt_resource_size(®_res) == 0x100)
- quirks |= MATSU_SD_CAP_16BIT;
+ quirks |= TMIO_SD_CAP_16BIT;
}
- ret = matsu_sd_probe(dev, quirks);
+ ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
if (!ret)
renesas_sdhi_reset_tuning(dev_get_priv(dev));
@@ -360,9 +360,9 @@
.name = "renesas-sdhi",
.id = UCLASS_MMC,
.of_match = renesas_sdhi_match,
- .bind = matsu_sd_bind,
+ .bind = tmio_sd_bind,
.probe = renesas_sdhi_probe,
- .priv_auto_alloc_size = sizeof(struct matsu_sd_priv),
- .platdata_auto_alloc_size = sizeof(struct matsu_sd_plat),
+ .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
+ .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
.ops = &renesas_sdhi_ops,
};