blob: 9acbc47fe8edf780e04246197beeeb6179c9b0f9 [file] [log] [blame]
Masahiro Yamada81385812016-01-12 16:36:38 +09001menu "Clock"
2
Simon Glassf26c8a82015-06-23 15:39:15 -06003config CLK
4 bool "Enable clock driver support"
5 depends on DM
6 help
7 This allows drivers to be provided for clock generators, including
8 oscillators and PLLs. Devices can use a common clock API to request
9 a particular clock rate and check on available clocks. Clocks can
10 feed into other clocks in a tree structure, with multiplexers to
11 choose the source for each clock.
12
Masahiro Yamada05435892015-08-12 07:31:46 +090013config SPL_CLK
Simon Glassf26c8a82015-06-23 15:39:15 -060014 bool "Enable clock support in SPL"
Wenyou Yang0712b672017-07-31 15:21:57 +080015 depends on CLK && SPL && SPL_DM
Simon Glassf26c8a82015-06-23 15:39:15 -060016 help
17 The clock subsystem adds a small amount of overhead to the image.
18 If this is acceptable and you have a need to use clock drivers in
19 SPL, enable this option. It might provide a cleaner interface to
20 setting up clocks within SPL, and allows the same drivers to be
21 used as U-Boot proper.
Masahiro Yamada81385812016-01-12 16:36:38 +090022
Philipp Tomsich7c819e72017-06-29 01:45:01 +020023config TPL_CLK
24 bool "Enable clock support in TPL"
25 depends on CLK && TPL_DM
26 help
27 The clock subsystem adds a small amount of overhead to the image.
28 If this is acceptable and you have a need to use clock drivers in
29 SPL, enable this option. It might provide a cleaner interface to
30 setting up clocks within TPL, and allows the same drivers to be
31 used as U-Boot proper.
32
Simon Glass747093d2022-04-30 00:56:53 -060033config VPL_CLK
34 bool "Enable clock support in VPL"
35 depends on CLK && VPL_DM
36 help
37 The clock subsystem adds a small amount of overhead to the image.
38 If this is acceptable and you have a need to use clock drivers in
39 SPL, enable this option. It might provide a cleaner interface to
40 setting up clocks within TPL, and allows the same drivers to be
41 used as U-Boot proper.
42
43config CLK_BCM6345
44 bool "Clock controller driver for BCM6345"
45 depends on CLK && ARCH_BMIPS
46 default y
47 help
48 This clock driver adds support for enabling and disabling peripheral
49 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
50
51config CLK_BOSTON
52 def_bool y if TARGET_BOSTON
53 depends on CLK
54 select REGMAP
55 select SYSCON
56 help
57 Enable this to support the clocks
58
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020059config SPL_CLK_CCF
Michal Simekd20bcba2024-04-16 08:55:15 +020060 bool "SPL Common Clock Framework [CCF] support"
Adam Forda0746672019-08-24 13:50:34 -050061 depends on SPL
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020062 help
63 Enable this option if you want to (re-)use the Linux kernel's Common
64 Clock Framework [CCF] code in U-Boot's SPL.
65
Peng Fan00097632019-07-31 07:01:54 +000066config SPL_CLK_COMPOSITE_CCF
Michal Simekd20bcba2024-04-16 08:55:15 +020067 bool "SPL Common Clock Framework [CCF] composite clk support"
Peng Fan00097632019-07-31 07:01:54 +000068 depends on SPL_CLK_CCF
69 help
70 Enable this option if you want to (re-)use the Linux kernel's Common
71 Clock Framework [CCF] composite code in U-Boot's SPL.
72
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020073config CLK_CCF
Michal Simekd20bcba2024-04-16 08:55:15 +020074 bool "Common Clock Framework [CCF] support"
Lukasz Majewski1d7993d2019-06-24 15:50:45 +020075 help
76 Enable this option if you want to (re-)use the Linux kernel's Common
77 Clock Framework [CCF] code in U-Boot's clock driver.
78
Peng Fan00097632019-07-31 07:01:54 +000079config CLK_COMPOSITE_CCF
Michal Simekd20bcba2024-04-16 08:55:15 +020080 bool "Common Clock Framework [CCF] composite clk support"
Peng Fan00097632019-07-31 07:01:54 +000081 depends on CLK_CCF
82 help
83 Enable this option if you want to (re-)use the Linux kernel's Common
84 Clock Framework [CCF] composite code in U-Boot's clock driver.
85
Marek Vasut92d5f992023-08-14 01:51:27 +020086config CLK_GPIO
87 bool "GPIO-controlled clock gate driver"
88 depends on CLK
89 help
90 Enable this option to add GPIO-controlled clock gate driver.
91
92config SPL_CLK_GPIO
93 bool "GPIO-controlled clock gate driver in SPL"
94 depends on SPL_CLK
95 help
96 Enable this option to add GPIO-controlled clock gate driver
97 in U-Boot SPL.
98
Sean Anderson7d4a7852021-12-15 11:36:19 -050099config CLK_BCM6345
100 bool "Clock controller driver for BCM6345"
101 depends on CLK && ARCH_BMIPS
102 default y
103 help
104 This clock driver adds support for enabling and disabling peripheral
105 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
106
107config CLK_BOSTON
108 def_bool y if TARGET_BOSTON
109 depends on CLK
110 select REGMAP
111 select SYSCON
112 help
113 Enable this to support the clocks
114
115config CLK_CDCE9XX
116 bool "Enable CDCD9XX clock driver"
117 depends on CLK
118 help
119 Enable the clock synthesizer driver for CDCE913/925/937/949
120 series of chips.
121
Sean Anderson052bebe2021-12-15 11:36:20 -0500122config CLK_ICS8N3QV01
Sean Anderson7d4a7852021-12-15 11:36:19 -0500123 bool "Enable ICS8N3QV01 VCXO driver"
124 depends on CLK
125 help
126 Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
127 Crystal Oscillator). The output frequency can be programmed via an
128 I2C interface.
129
Simon Glassb4d00b22020-02-06 09:54:53 -0700130config CLK_INTEL
131 bool "Enable clock driver for Intel x86"
132 depends on CLK && X86
133 help
134 This provides very basic support for clocks on Intel SoCs. The driver
135 is barely used at present but could be expanded as needs arise.
136 Much clock configuration in U-Boot is either set up by the FSP, or
137 set up by U-Boot itself but only statically. Thus the driver does not
138 support changing clock rates, only querying them.
139
Sean Anderson7d4a7852021-12-15 11:36:19 -0500140config CLK_K210
141 bool "Clock support for Kendryte K210"
142 depends on CLK
143 help
144 This enables support clock driver for Kendryte K210 platforms.
145
146config CLK_K210_SET_RATE
147 bool "Enable setting the Kendryte K210 PLL rate"
148 depends on CLK_K210
149 help
150 Add functionality to calculate new rates for K210 PLLs. Enabling this
151 feature adds around 1K to U-Boot's final size.
152
153config CLK_MPC83XX
154 bool "Enable MPC83xx clock driver"
155 depends on CLK
156 help
157 Support for the clock driver of the MPC83xx series of SoCs.
158
Stefan Roeseb113c9b2020-07-30 13:56:16 +0200159config CLK_OCTEON
160 bool "Clock controller driver for Marvell MIPS Octeon"
161 depends on CLK && ARCH_OCTEON
162 default y
163 help
164 Enable this to support the clocks on Octeon MIPS platforms.
165
Sean Anderson7d4a7852021-12-15 11:36:19 -0500166config SANDBOX_CLK_CCF
Michal Simekd20bcba2024-04-16 08:55:15 +0200167 bool "Sandbox Common Clock Framework [CCF] support"
Sean Anderson7d4a7852021-12-15 11:36:19 -0500168 depends on SANDBOX
169 select CLK_CCF
170 help
171 Enable this option if you want to test the Linux kernel's Common
172 Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
173
174config CLK_SCMI
175 bool "Enable SCMI clock driver"
AKASHI Takahiro45a00522023-06-12 10:14:49 +0900176 depends on CLK
Sean Anderson7d4a7852021-12-15 11:36:19 -0500177 depends on SCMI_FIRMWARE
178 help
179 Enable this option if you want to support clock devices exposed
180 by a SCMI agent based on SCMI clock protocol communication
181 with a SCMI server.
182
Jonas Karlman22297582023-04-17 19:07:18 +0000183config SPL_CLK_SCMI
184 bool "Enable SCMI clock driver in SPL"
185 depends on SCMI_FIRMWARE && SPL_FIRMWARE
186 help
187 Enable this option if you want to support clock devices exposed
188 by a SCMI agent based on SCMI clock protocol communication
189 with a SCMI server in SPL.
190
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300191config CLK_HSDK
Eugeniy Paltsev80a76742020-05-07 22:20:10 +0300192 bool "Enable cgu clock driver for HSDK boards"
193 depends on CLK && TARGET_HSDK
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300194 help
Eugeniy Paltsev80a76742020-05-07 22:20:10 +0300195 Enable this to support the cgu clocks on Synopsys ARC HSDK and
196 Synopsys ARC HSDK-4xD boards
Eugeniy Paltseve80dac02017-12-10 21:20:08 +0300197
Sean Anderson7d4a7852021-12-15 11:36:19 -0500198config CLK_VERSACLOCK
199 tristate "Enable VersaClock 5/6 devices"
200 depends on CLK
201 depends on CLK_CCF
202 depends on OF_CONTROL
203 help
204 This driver supports the IDT VersaClock 5 and VersaClock 6
205 programmable clock generators.
206
Siva Durga Prasad Paladugu95105082019-06-23 12:24:57 +0530207config CLK_VERSAL
208 bool "Enable clock driver support for Versal"
Jay Buddhabhattiff332272022-09-19 14:21:05 +0200209 depends on (ARCH_VERSAL || ARCH_VERSAL_NET)
Algapally Santosh Sagar6d87b152023-02-01 02:55:53 -0700210 imply ZYNQMP_FIRMWARE
Siva Durga Prasad Paladugu95105082019-06-23 12:24:57 +0530211 help
212 This clock driver adds support for clock realted settings for
213 Versal platform.
214
Liviu Dudaua71e9072018-09-17 17:50:00 +0100215config CLK_VEXPRESS_OSC
216 bool "Enable driver for Arm Versatile Express OSC clock generators"
217 depends on CLK && VEXPRESS_CONFIG
218 help
219 This clock driver adds support for clock generators present on
220 Arm Versatile Express platforms.
221
Zhengxun2b157d82021-06-11 15:10:48 +0000222config CLK_XLNX_CLKWZRD
223 bool "Xilinx Clocking Wizard"
224 depends on CLK
225 help
226 Support for the Xilinx Clocking Wizard IP core clock generator.
227 The wizard support for dynamically reconfiguring the clocking
228 primitives for Multiply, Divide, Phase Shift/Offset, or Duty
229 Cycle. Limited by U-Boot clk uclass without set_phase API and
230 set_duty_cycle API, this driver only supports set_rate to modify
231 the frequency.
232
Sean Anderson7d4a7852021-12-15 11:36:19 -0500233config CLK_ZYNQ
234 bool "Enable clock driver support for Zynq"
235 depends on CLK && ARCH_ZYNQ
236 default y
237 help
238 This clock driver adds support for clock related settings for
239 Zynq platform.
240
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530241config CLK_ZYNQMP
242 bool "Enable clock driver support for ZynqMP"
243 depends on ARCH_ZYNQMP
Algapally Santosh Sagar6d87b152023-02-01 02:55:53 -0700244 imply ZYNQMP_FIRMWARE
Siva Durga Prasad Paladugu128ec1f2016-11-15 16:15:41 +0530245 help
246 This clock driver adds support for clock realted settings for
247 ZynqMP platform.
248
Tom Rini03de3052024-05-20 13:35:03 -0600249source "drivers/clk/adi/Kconfig"
Anup Pateld04c79d2019-06-25 06:31:02 +0000250source "drivers/clk/analogbits/Kconfig"
Wenyou Yang9e5935c2016-07-20 17:55:12 +0800251source "drivers/clk/at91/Kconfig"
Jagan Tekicf682252018-07-30 18:26:18 +0530252source "drivers/clk/exynos/Kconfig"
Peng Fanf77d4412018-10-18 14:28:30 +0200253source "drivers/clk/imx/Kconfig"
Jerome Brunetf5abfed2019-02-10 14:54:30 +0100254source "drivers/clk/meson/Kconfig"
Padmarao Begari2f27c922021-01-15 08:20:38 +0530255source "drivers/clk/microchip/Kconfig"
Marek BehĂșn82a248d2018-04-24 17:21:25 +0200256source "drivers/clk/mvebu/Kconfig"
Manivannan Sadhasivamae485b52018-06-14 23:38:35 +0530257source "drivers/clk/owl/Kconfig"
Caleb Connollya623c142023-11-07 12:40:59 +0000258source "drivers/clk/qcom/Kconfig"
Jagan Tekicf682252018-07-30 18:26:18 +0530259source "drivers/clk/renesas/Kconfig"
Jagan Teki0d47bc72018-12-22 21:32:49 +0530260source "drivers/clk/sunxi/Kconfig"
Anup Patelc40b6df2019-02-25 08:14:49 +0000261source "drivers/clk/sifive/Kconfig"
Yanhong Wangc13fe7c2023-03-29 11:42:13 +0800262source "drivers/clk/starfive/Kconfig"
Patrick Delaunayb9929332022-05-19 17:56:45 +0200263source "drivers/clk/stm32/Kconfig"
Jagan Tekicf682252018-07-30 18:26:18 +0530264source "drivers/clk/tegra/Kconfig"
Dario Binacchid09f0632020-12-30 00:06:32 +0100265source "drivers/clk/ti/Kconfig"
Jagan Tekicf682252018-07-30 18:26:18 +0530266source "drivers/clk/uniphier/Kconfig"
Masahiro Yamada48264d92016-02-02 21:11:32 +0900267
Masahiro Yamada81385812016-01-12 16:36:38 +0900268endmenu