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wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Galaa09b9b62010-12-30 12:09:53 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Ed Swarthout29372ff2007-07-27 01:50:47 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <watchdog.h>
31#include <asm/processor.h>
32#include <ioports.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050033#include <sata.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050034#include <fm_eth.h>
wdenk42d1f032003-10-15 23:53:47 +000035#include <asm/io.h>
Kumar Galafd3c9be2010-05-05 22:35:27 -050036#include <asm/cache.h>
Kumar Gala87163182008-01-16 22:38:34 -060037#include <asm/mmu.h>
Kumar Gala83d40df2008-01-16 01:13:58 -060038#include <asm/fsl_law.h>
Kumar Galaf54fe872010-04-20 10:21:25 -050039#include <asm/fsl_serdes.h>
Liu Gang5ffa88e2012-03-08 00:33:17 +000040#include <asm/fsl_srio.h>
York Sun57125f22012-08-08 18:04:53 +000041#include <hwconfig.h>
Timur Tabifbc20aa2011-11-21 17:10:23 -060042#include <linux/compiler.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060043#include "mp.h"
Timur Tabif2717b42011-11-22 09:21:25 -060044#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -050045#include <nand.h>
46#include <errno.h>
47#endif
wdenk42d1f032003-10-15 23:53:47 +000048
Timur Tabifbc20aa2011-11-21 17:10:23 -060049#include "../../../../drivers/block/fsl_sata.h"
50
Wolfgang Denkd87080b2006-03-31 18:32:53 +020051DECLARE_GLOBAL_DATA_PTR;
52
Andy Flemingda9d4612007-08-14 00:14:25 -050053#ifdef CONFIG_QE
54extern qe_iop_conf_t qe_iop_conf_tab[];
55extern void qe_config_iopin(u8 port, u8 pin, int dir,
56 int open_drain, int assign);
57extern void qe_init(uint qe_base);
58extern void qe_reset(void);
59
60static void config_qe_ioports(void)
61{
62 u8 port, pin;
63 int dir, open_drain, assign;
64 int i;
65
66 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
67 port = qe_iop_conf_tab[i].port;
68 pin = qe_iop_conf_tab[i].pin;
69 dir = qe_iop_conf_tab[i].dir;
70 open_drain = qe_iop_conf_tab[i].open_drain;
71 assign = qe_iop_conf_tab[i].assign;
72 qe_config_iopin(port, pin, dir, open_drain, assign);
73 }
74}
75#endif
Matthew McClintock40d5fa32006-06-28 10:43:36 -050076
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050077#ifdef CONFIG_CPM2
Kumar Galaaafeefb2007-11-28 00:36:33 -060078void config_8560_ioports (volatile ccsr_cpm_t * cpm)
wdenk42d1f032003-10-15 23:53:47 +000079{
80 int portnum;
81
82 for (portnum = 0; portnum < 4; portnum++) {
83 uint pmsk = 0,
84 ppar = 0,
85 psor = 0,
86 pdir = 0,
87 podr = 0,
88 pdat = 0;
89 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
90 iop_conf_t *eiopc = iopc + 32;
91 uint msk = 1;
92
93 /*
94 * NOTE:
95 * index 0 refers to pin 31,
96 * index 31 refers to pin 0
97 */
98 while (iopc < eiopc) {
99 if (iopc->conf) {
100 pmsk |= msk;
101 if (iopc->ppar)
102 ppar |= msk;
103 if (iopc->psor)
104 psor |= msk;
105 if (iopc->pdir)
106 pdir |= msk;
107 if (iopc->podr)
108 podr |= msk;
109 if (iopc->pdat)
110 pdat |= msk;
111 }
112
113 msk <<= 1;
114 iopc++;
115 }
116
117 if (pmsk != 0) {
Kumar Galaaafeefb2007-11-28 00:36:33 -0600118 volatile ioport_t *iop = ioport_addr (cpm, portnum);
wdenk42d1f032003-10-15 23:53:47 +0000119 uint tpmsk = ~pmsk;
120
121 /*
122 * the (somewhat confused) paragraph at the
123 * bottom of page 35-5 warns that there might
124 * be "unknown behaviour" when programming
125 * PSORx and PDIRx, if PPARx = 1, so I
126 * decided this meant I had to disable the
127 * dedicated function first, and enable it
128 * last.
129 */
130 iop->ppar &= tpmsk;
131 iop->psor = (iop->psor & tpmsk) | psor;
132 iop->podr = (iop->podr & tpmsk) | podr;
133 iop->pdat = (iop->pdat & tpmsk) | pdat;
134 iop->pdir = (iop->pdir & tpmsk) | pdir;
135 iop->ppar |= ppar;
136 }
137 }
138}
139#endif
140
Kumar Gala6aba33e2009-03-19 03:40:08 -0500141#ifdef CONFIG_SYS_FSL_CPC
142static void enable_cpc(void)
143{
144 int i;
145 u32 size = 0;
146
147 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
148
149 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
150 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
151 size += CPC_CFG0_SZ_K(cpccfg0);
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800152#ifdef CONFIG_RAMBOOT_PBL
153 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
154 /* find and disable LAW of SRAM */
155 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
156
157 if (law.index == -1) {
158 printf("\nFatal error happened\n");
159 return;
160 }
161 disable_law(law.index);
162
163 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
164 out_be32(&cpc->cpccsr0, 0);
165 out_be32(&cpc->cpcsrcr0, 0);
166 }
167#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500168
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600169#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
170 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
171#endif
Kumar Gala868da592011-01-13 01:56:18 -0600172#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
173 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
174#endif
Kumar Gala1d2c2a62011-01-13 01:54:01 -0600175
Kumar Gala6aba33e2009-03-19 03:40:08 -0500176 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
177 /* Read back to sync write */
178 in_be32(&cpc->cpccsr0);
179
180 }
181
182 printf("Corenet Platform Cache: %d KB enabled\n", size);
183}
184
185void invalidate_cpc(void)
186{
187 int i;
188 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
189
190 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
Shaohui Xie2a9fab82011-03-16 10:10:32 +0800191 /* skip CPC when it used as all SRAM */
192 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
193 continue;
Kumar Gala6aba33e2009-03-19 03:40:08 -0500194 /* Flash invalidate the CPC and clear all the locks */
195 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
196 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
197 ;
198 }
199}
200#else
201#define enable_cpc()
202#define invalidate_cpc()
203#endif /* CONFIG_SYS_FSL_CPC */
204
wdenk42d1f032003-10-15 23:53:47 +0000205/*
206 * Breathe some life into the CPU...
207 *
208 * Set up the memory map
209 * initialize a bunch of registers
210 */
211
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500212#ifdef CONFIG_FSL_CORENET
213static void corenet_tb_init(void)
214{
215 volatile ccsr_rcpm_t *rcpm =
216 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
217 volatile ccsr_pic_t *pic =
Kim Phillips680c6132010-08-09 18:39:57 -0500218 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500219 u32 whoami = in_be32(&pic->whoami);
220
221 /* Enable the timebase register for this core */
222 out_be32(&rcpm->ctbenrl, (1 << whoami));
223}
224#endif
225
wdenk42d1f032003-10-15 23:53:47 +0000226void cpu_init_f (void)
227{
wdenk42d1f032003-10-15 23:53:47 +0000228 extern void m8560_cpm_reset (void);
Stephen Georgef110fe92011-07-20 09:47:26 -0500229#ifdef CONFIG_SYS_DCSRBAR_PHYS
230 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
231#endif
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000232#if defined(CONFIG_SECURE_BOOT)
233 struct law_entry law;
234#endif
Peter Tysera2cd50e2008-11-11 10:17:10 -0600235#ifdef CONFIG_MPC8548
236 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
237 uint svr = get_svr();
238
239 /*
240 * CPU2 errata workaround: A core hang possible while executing
241 * a msync instruction and a snoopable transaction from an I/O
242 * master tagged to make quick forward progress is present.
243 * Fixed in silicon rev 2.1.
244 */
245 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
246 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
247#endif
wdenk42d1f032003-10-15 23:53:47 +0000248
Kumar Gala87163182008-01-16 22:38:34 -0600249 disable_tlb(14);
250 disable_tlb(15);
251
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000252#if defined(CONFIG_SECURE_BOOT)
253 /* Disable the LAW created for NOR flash by the PBI commands */
254 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
255 if (law.index != -1)
256 disable_law(law.index);
257#endif
258
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500259#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000261#endif
262
Becky Brucef51cdaf2010-06-17 11:37:20 -0500263 init_early_memctl_regs();
wdenk42d1f032003-10-15 23:53:47 +0000264
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500265#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +0000266 m8560_cpm_reset();
267#endif
Andy Flemingda9d4612007-08-14 00:14:25 -0500268#ifdef CONFIG_QE
269 /* Config QE ioports */
270 config_qe_ioports();
271#endif
Peter Tyser79f43332009-06-30 17:15:47 -0500272#if defined(CONFIG_FSL_DMA)
273 dma_init();
274#endif
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500275#ifdef CONFIG_FSL_CORENET
276 corenet_tb_init();
277#endif
Kumar Gala94e94112009-11-12 10:26:16 -0600278 init_used_tlb_cams();
Kumar Gala6aba33e2009-03-19 03:40:08 -0500279
280 /* Invalidate the CPC before DDR gets enabled */
281 invalidate_cpc();
Stephen Georgef110fe92011-07-20 09:47:26 -0500282
283 #ifdef CONFIG_SYS_DCSRBAR_PHYS
284 /* set DCSRCR so that DCSR space is 1G */
285 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
286 in_be32(&gur->dcsrcr);
287#endif
288
wdenk42d1f032003-10-15 23:53:47 +0000289}
290
Kumar Gala35079aa2010-12-15 03:50:47 -0600291/* Implement a dummy function for those platforms w/o SERDES */
292static void __fsl_serdes__init(void)
293{
294 return ;
295}
296__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500297
wdenk42d1f032003-10-15 23:53:47 +0000298/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500299 * Initialize L2 as cache.
300 *
301 * The newer 8548, etc, parts have twice as much cache, but
302 * use the same bit-encoding as the older 8555, etc, parts.
303 *
wdenk42d1f032003-10-15 23:53:47 +0000304 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500305int cpu_init_r(void)
wdenk42d1f032003-10-15 23:53:47 +0000306{
Timur Tabifbc20aa2011-11-21 17:10:23 -0600307 __maybe_unused u32 svr = get_svr();
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500308#ifdef CONFIG_SYS_LBC_LCRR
Becky Brucef51cdaf2010-06-17 11:37:20 -0500309 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500310#endif
311
York Sun5e23ab02012-05-07 07:26:47 +0000312#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
313 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
314 /*
York Sun57125f22012-08-08 18:04:53 +0000315 * CPU22 and NMG_CPU_A011 share the same workaround.
York Sun5e23ab02012-05-07 07:26:47 +0000316 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
317 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
York Sun57125f22012-08-08 18:04:53 +0000318 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
319 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
320 * be disabled by hwconfig with syntax:
321 *
322 * fsl_cpu_a011:disable
York Sun5e23ab02012-05-07 07:26:47 +0000323 */
York Sun57125f22012-08-08 18:04:53 +0000324 extern int enable_cpu_a011_workaround;
325#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
326 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
327#else
328 char buffer[HWCONFIG_BUFFER_SIZE];
329 char *buf = NULL;
330 int n, res;
331
332 n = getenv_f("hwconfig", buffer, sizeof(buffer));
333 if (n > 0)
334 buf = buffer;
335
336 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
337 if (res > 0)
338 enable_cpu_a011_workaround = 0;
339 else {
340 if (n >= HWCONFIG_BUFFER_SIZE) {
341 printf("fsl_cpu_a011 was not found. hwconfig variable "
342 "may be too long\n");
343 }
344 enable_cpu_a011_workaround =
345 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
346 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
347 }
348#endif
349 if (enable_cpu_a011_workaround) {
York Sun1e9ea852012-05-07 07:26:45 +0000350 flush_dcache();
351 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
352 sync();
353 }
Kumar Galafd3c9be2010-05-05 22:35:27 -0500354#endif
355
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200356 puts ("L2: ");
357
wdenk42d1f032003-10-15 23:53:47 +0000358#if defined(CONFIG_L2_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500360 volatile uint cache_ctl;
Timur Tabifbc20aa2011-11-21 17:10:23 -0600361 uint ver;
Kumar Gala73f15a02008-07-14 14:07:00 -0500362 u32 l2siz_field;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500363
Kumar Galaf3e04bd2008-04-08 10:45:50 -0500364 ver = SVR_SOC_VER(svr);
wdenk42d1f032003-10-15 23:53:47 +0000365
366 asm("msync;isync");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500367 cache_ctl = l2cache->l2ctl;
Mingkai Hu7da53352009-09-11 14:19:10 +0800368
369#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
370 if (cache_ctl & MPC85xx_L2CTL_L2E) {
371 /* Clear L2 SRAM memory-mapped base address */
372 out_be32(&l2cache->l2srbar0, 0x0);
373 out_be32(&l2cache->l2srbar1, 0x0);
374
375 /* set MBECCDIS=0, SBECCDIS=0 */
376 clrbits_be32(&l2cache->l2errdis,
377 (MPC85xx_L2ERRDIS_MBECC |
378 MPC85xx_L2ERRDIS_SBECC));
379
380 /* set L2E=0, L2SRAM=0 */
381 clrbits_be32(&l2cache->l2ctl,
382 (MPC85xx_L2CTL_L2E |
383 MPC85xx_L2CTL_L2SRAM_ENTIRE));
384 }
385#endif
386
Kumar Gala73f15a02008-07-14 14:07:00 -0500387 l2siz_field = (cache_ctl >> 28) & 0x3;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500388
Kumar Gala73f15a02008-07-14 14:07:00 -0500389 switch (l2siz_field) {
390 case 0x0:
391 printf(" unknown size (0x%08x)\n", cache_ctl);
392 return -1;
393 break;
394 case 0x1:
395 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500396 ver == SVR_8541 || ver == SVR_8555) {
Kumar Gala73f15a02008-07-14 14:07:00 -0500397 puts("128 KB ");
398 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
399 cache_ctl = 0xc4000000;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500400 } else {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200401 puts("256 KB ");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500402 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
403 }
404 break;
Kumar Gala73f15a02008-07-14 14:07:00 -0500405 case 0x2:
406 if (ver == SVR_8540 || ver == SVR_8560 ||
York Sun48f6a5c2012-07-06 17:10:33 -0500407 ver == SVR_8541 || ver == SVR_8555) {
Kumar Gala73f15a02008-07-14 14:07:00 -0500408 puts("256 KB ");
409 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
410 cache_ctl = 0xc8000000;
411 } else {
412 puts ("512 KB ");
413 /* set L2E=1, L2I=1, & L2SRAM=0 */
414 cache_ctl = 0xc0000000;
415 }
416 break;
417 case 0x3:
418 puts("1024 KB ");
419 /* set L2E=1, L2I=1, & L2SRAM=0 */
420 cache_ctl = 0xc0000000;
421 break;
Jon Loeligerd65cfe82005-07-25 10:58:39 -0500422 }
423
Mingkai Hu76b474e2009-08-18 15:37:15 +0800424 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200425 puts("already enabled");
Haiying Wang888279b2010-12-01 10:35:30 -0500426#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
Kumar Galae4c9a352011-11-09 09:56:41 -0600427 u32 l2srbar = l2cache->l2srbar0;
Mingkai Hu76b474e2009-08-18 15:37:15 +0800428 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
429 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
Ed Swarthout29372ff2007-07-27 01:50:47 -0500431 l2cache->l2srbar0 = l2srbar;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
Ed Swarthout29372ff2007-07-27 01:50:47 -0500433 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#endif /* CONFIG_SYS_INIT_L2_ADDR */
Ed Swarthout29372ff2007-07-27 01:50:47 -0500435 puts("\n");
436 } else {
437 asm("msync;isync");
438 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
439 asm("msync;isync");
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200440 puts("enabled\n");
Ed Swarthout29372ff2007-07-27 01:50:47 -0500441 }
Kumar Gala1b3e4042009-03-19 09:16:10 -0500442#elif defined(CONFIG_BACKSIDE_L2_CACHE)
York Sun48f6a5c2012-07-06 17:10:33 -0500443 if (SVR_SOC_VER(svr) == SVR_P2040) {
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500444 puts("N/A\n");
445 goto skip_l2;
446 }
447
Kumar Gala1b3e4042009-03-19 09:16:10 -0500448 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
449
450 /* invalidate the L2 cache */
Kumar Gala25bacf72009-09-22 15:45:44 -0500451 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
452 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
Kumar Gala1b3e4042009-03-19 09:16:10 -0500453 ;
454
Kumar Gala82fd1f82009-03-19 02:53:01 -0500455#ifdef CONFIG_SYS_CACHE_STASHING
456 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
457 mtspr(SPRN_L2CSR1, (32 + 1));
458#endif
459
Kumar Gala1b3e4042009-03-19 09:16:10 -0500460 /* enable the cache */
461 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
462
Dave Liu654ea1f2009-10-22 00:10:23 -0500463 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
464 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
465 ;
Kumar Gala1b3e4042009-03-19 09:16:10 -0500466 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
Dave Liu654ea1f2009-10-22 00:10:23 -0500467 }
Kumar Galaacf3f8d2011-07-21 00:20:21 -0500468
469skip_l2:
wdenk42d1f032003-10-15 23:53:47 +0000470#else
Wolfgang Grandegger6beecfb2008-06-05 13:11:59 +0200471 puts("disabled\n");
wdenk42d1f032003-10-15 23:53:47 +0000472#endif
Kumar Gala6aba33e2009-03-19 03:40:08 -0500473
474 enable_cpc();
475
Kumar Galaaf025062010-05-22 13:21:39 -0500476 /* needs to be in ram since code uses global static vars */
477 fsl_serdes_init();
Kumar Galaaf025062010-05-22 13:21:39 -0500478
Kumar Galaa09b9b62010-12-30 12:09:53 -0600479#ifdef CONFIG_SYS_SRIO
480 srio_init();
Liu Gangff65f122012-08-09 05:09:59 +0000481#ifdef CONFIG_FSL_CORENET
482 char *s = getenv("bootmaster");
483 if (s) {
484 if (!strcmp(s, "SRIO1")) {
485 srio_boot_master(1);
486 srio_boot_master_release_slave(1);
487 }
488 if (!strcmp(s, "SRIO2")) {
489 srio_boot_master(2);
490 srio_boot_master_release_slave(2);
491 }
492 }
Liu Gang5ffa88e2012-03-08 00:33:17 +0000493#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600494#endif
495
Kumar Galaec2b74f2008-01-17 16:48:33 -0600496#if defined(CONFIG_MP)
497 setup_mp();
498#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500499
Roy Zangae026ff2011-01-07 00:24:27 -0600500#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
501 {
502 void *p;
503 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
504 setbits_be32(p, 1 << (31 - 14));
505 }
506#endif
507
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500508#ifdef CONFIG_SYS_LBC_LCRR
509 /*
510 * Modify the CLKDIV field of LCRR register to improve the writing
511 * speed for NOR flash.
512 */
513 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
514 __raw_readl(&lbc->lcrr);
515 isync();
Kumar Gala2b3a1cd2011-10-03 08:37:57 -0500516#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
517 udelay(100);
518#endif
Lan Chunhe3f0202e2010-04-21 07:40:50 -0500519#endif
520
Roy Zang86221f02011-04-13 00:08:51 -0500521#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
522 {
523 ccsr_usb_phy_t *usb_phy1 =
524 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
525 out_be32(&usb_phy1->usb_enable_override,
526 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
527 }
528#endif
529#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
530 {
531 ccsr_usb_phy_t *usb_phy2 =
532 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
533 out_be32(&usb_phy2->usb_enable_override,
534 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
535 }
536#endif
537
Kumar Galac916d7c2011-04-13 08:37:44 -0500538#ifdef CONFIG_FMAN_ENET
539 fman_enet_init();
540#endif
541
Timur Tabifbc20aa2011-11-21 17:10:23 -0600542#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
543 /*
544 * For P1022/1013 Rev1.0 silicon, after power on SATA host
545 * controller is configured in legacy mode instead of the
546 * expected enterprise mode. Software needs to clear bit[28]
547 * of HControl register to change to enterprise mode from
548 * legacy mode. We assume that the controller is offline.
549 */
550 if (IS_SVR_REV(svr, 1, 0) &&
551 ((SVR_SOC_VER(svr) == SVR_P1022) ||
York Sun48f6a5c2012-07-06 17:10:33 -0500552 (SVR_SOC_VER(svr) == SVR_P1013))) {
Timur Tabifbc20aa2011-11-21 17:10:23 -0600553 fsl_sata_reg_t *reg;
554
555 /* first SATA controller */
556 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
557 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
558
559 /* second SATA controller */
560 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
561 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
562 }
563#endif
564
565
wdenk42d1f032003-10-15 23:53:47 +0000566 return 0;
567}
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500568
569extern void setup_ivors(void);
570
571void arch_preboot_os(void)
572{
Kumar Gala15fba322009-09-11 15:28:41 -0500573 u32 msr;
574
575 /*
576 * We are changing interrupt offsets and are about to boot the OS so
577 * we need to make sure we disable all async interrupts. EE is already
578 * disabled by the time we get called.
579 */
580 msr = mfmsr();
Prabhakar Kushwaha5344f7a2012-04-29 23:56:30 +0000581 msr &= ~(MSR_ME|MSR_CE);
Kumar Gala15fba322009-09-11 15:28:41 -0500582 mtmsr(msr);
583
Kumar Gala26f4cdba2009-08-14 13:37:54 -0500584 setup_ivors();
585}
Kumar Galaf54fe872010-04-20 10:21:25 -0500586
587#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
588int sata_initialize(void)
589{
590 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
591 return __sata_initialize();
592
593 return 1;
594}
595#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600596
597void cpu_secondary_init_r(void)
598{
599#ifdef CONFIG_QE
600 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
Timur Tabif2717b42011-11-22 09:21:25 -0600601#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500602 int ret;
Timur Tabif2717b42011-11-22 09:21:25 -0600603 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500604
605 /* load QE firmware from NAND flash to DDR first */
Timur Tabif2717b42011-11-22 09:21:25 -0600606 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
607 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500608
609 if (ret && ret == -EUCLEAN) {
610 printf ("NAND read for QE firmware at offset %x failed %d\n",
Timur Tabif2717b42011-11-22 09:21:25 -0600611 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
Haiying Wanga7b1e1b2011-02-07 16:14:15 -0500612 }
613#endif
Kumar Galaf9a33f12011-02-02 11:23:50 -0600614 qe_init(qe_base);
615 qe_reset();
616#endif
617}