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Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	1	/*
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	3	*
				4	* This program is free software; you can redistribute it and/or
				5	* modify it under the terms of the GNU General Public License as
				6	* published by the Free Software Foundation; either version 2 of
				7	* the License, or (at your option) any later version.
				8	*
				9	* This program is distributed in the hope that it will be useful,
				10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
				11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				12	* GNU General Public License for more details.
				13	*
				14	* You should have received a copy of the GNU General Public License
				15	* along with this program; if not, write to the Free Software
				16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
				17	* MA 02111-1307 USA
				18	*
				19	*/
				20
				21	#ifndef _ASM_MPC85xx_CONFIG_H_
				22	#define _ASM_MPC85xx_CONFIG_H_
				23
				24	/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
				25
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	26	#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
				27	#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
				28	#endif
				29
York Sun	2a5fcb8	2012-10-28 08:12:54 +0000	[diff] [blame]	30	/*
				31	* This macro should be removed when we no longer care about backwards
				32	* compatibility with older operating systems.
				33	*/
				34	#define CONFIG_PPC_SPINTABLE_COMPATIBLE
				35
York Sun	57495e4	2012-10-08 07:44:22 +0000	[diff] [blame]	36	#define FSL_DDR_VER_4_7 47
				37
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	38	/* Number of TLB CAM entries we have on FSL Book-E chips */
				39	#if defined(CONFIG_E500MC)
				40	#define CONFIG_SYS_NUM_TLBCAMS 64
				41	#elif defined(CONFIG_E500)
				42	#define CONFIG_SYS_NUM_TLBCAMS 16
				43	#endif
				44
				45	#if defined(CONFIG_MPC8536)
				46	#define CONFIG_MAX_CPUS 1
				47	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	48	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	49	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	50	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	51
Wolfgang Denk	d1a24f0	2011-02-02 22:36:10 +0100	[diff] [blame]	52	#elif defined(CONFIG_MPC8540)
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	53	#define CONFIG_MAX_CPUS 1
				54	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	55	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	56
Wolfgang Denk	d1a24f0	2011-02-02 22:36:10 +0100	[diff] [blame]	57	#elif defined(CONFIG_MPC8541)
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	58	#define CONFIG_MAX_CPUS 1
				59	#define CONFIG_SYS_FSL_NUM_LAWS 8
				60	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	61	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	62
				63	#elif defined(CONFIG_MPC8544)
				64	#define CONFIG_MAX_CPUS 1
				65	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	66	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	67	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	68	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	69
				70	#elif defined(CONFIG_MPC8548)
				71	#define CONFIG_MAX_CPUS 1
				72	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	73	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	74	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	75	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	5ace299	2011-09-16 09:54:30 -0500	[diff] [blame]	76	#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala	2b3a1cd	2011-10-03 08:37:57 -0500	[diff] [blame]	77	#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhao	aada81d	2011-10-03 08:38:50 -0500	[diff] [blame]	78	#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	79	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				80	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				81	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				82	#define CONFIG_SYS_FSL_RMU
				83	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	84
				85	#elif defined(CONFIG_MPC8555)
				86	#define CONFIG_MAX_CPUS 1
				87	#define CONFIG_SYS_FSL_NUM_LAWS 8
				88	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	89	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	90
				91	#elif defined(CONFIG_MPC8560)
				92	#define CONFIG_MAX_CPUS 1
				93	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	94	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	95
				96	#elif defined(CONFIG_MPC8568)
				97	#define CONFIG_MAX_CPUS 1
				98	#define CONFIG_SYS_FSL_NUM_LAWS 10
				99	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	fdb4dad	2011-01-31 23:09:25 -0600	[diff] [blame]	100	#define QE_MURAM_SIZE 0x10000UL
				101	#define MAX_QE_RISC 2
				102	#define QE_NUM_OF_SNUM 28
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	103	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	104	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				105	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				106	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				107	#define CONFIG_SYS_FSL_RMU
				108	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	109
				110	#elif defined(CONFIG_MPC8569)
				111	#define CONFIG_MAX_CPUS 1
				112	#define CONFIG_SYS_FSL_NUM_LAWS 10
				113	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	fdb4dad	2011-01-31 23:09:25 -0600	[diff] [blame]	114	#define QE_MURAM_SIZE 0x20000UL
				115	#define MAX_QE_RISC 4
				116	#define QE_NUM_OF_SNUM 46
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	117	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	118	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				119	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				120	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				121	#define CONFIG_SYS_FSL_RMU
				122	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	123
				124	#elif defined(CONFIG_MPC8572)
				125	#define CONFIG_MAX_CPUS 2
				126	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	e4879af	2012-08-15 04:12:43 +0000	[diff] [blame]	127	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	128	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	129	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	eb0aff7	2011-01-25 21:51:27 -0800	[diff] [blame]	130	#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun	9167191	2011-01-25 22:05:49 -0800	[diff] [blame]	131	#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	132
				133	#elif defined(CONFIG_P1010)
				134	#define CONFIG_MAX_CPUS 1
Priyanka Jain	32c8cfb	2011-02-09 09:24:10 +0530	[diff] [blame]	135	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	136	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	137	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	138	#define CONFIG_TSECV2
				139	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	140	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				141	#define CONFIG_NUM_DDR_CONTROLLERS 1
				142	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	143	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh	1b719e6	2011-03-23 15:20:43 +0530	[diff] [blame]	144	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	42aee64	2011-06-30 03:00:28 -0500	[diff] [blame]	145	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	fb855f4	2011-06-29 16:32:52 +0530	[diff] [blame]	146	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal	bc6bbd6	2011-07-07 20:36:47 +0530	[diff] [blame]	147	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	148
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	149	/* P1011 is single core version of P1020 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	150	#elif defined(CONFIG_P1011)
				151	#define CONFIG_MAX_CPUS 1
				152	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	153	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	154	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	155	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	156	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	157	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	158	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				159	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	160
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	161	/* P1012 is single core version of P1021 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	162	#elif defined(CONFIG_P1012)
				163	#define CONFIG_MAX_CPUS 1
				164	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	165	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	166	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	167	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	168	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	169	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	170	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				171	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	172	#define QE_MURAM_SIZE 0x6000UL
				173	#define MAX_QE_RISC 1
				174	#define QE_NUM_OF_SNUM 28
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	175
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	176	/* P1013 is single core version of P1022 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	177	#elif defined(CONFIG_P1013)
				178	#define CONFIG_MAX_CPUS 1
				179	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	180	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	181	#define CONFIG_TSECV2
				182	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	183	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	2d7534a	2011-01-30 17:06:20 -0600	[diff] [blame]	184	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				185	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				186	#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	187
				188	#elif defined(CONFIG_P1014)
				189	#define CONFIG_MAX_CPUS 1
Priyanka Jain	32c8cfb	2011-02-09 09:24:10 +0530	[diff] [blame]	190	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	191	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	192	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	193	#define CONFIG_TSECV2
				194	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	1fbf348	2011-02-06 11:31:44 +0530	[diff] [blame]	195	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				196	#define CONFIG_NUM_DDR_CONTROLLERS 1
				197	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh	1b719e6	2011-03-23 15:20:43 +0530	[diff] [blame]	198	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	42aee64	2011-06-30 03:00:28 -0500	[diff] [blame]	199	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	fb855f4	2011-06-29 16:32:52 +0530	[diff] [blame]	200	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal	bc6bbd6	2011-07-07 20:36:47 +0530	[diff] [blame]	201	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	202
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	203	/* P1017 is single core version of P1023 */
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	204	#elif defined(CONFIG_P1017)
				205	#define CONFIG_MAX_CPUS 1
				206	#define CONFIG_SYS_FSL_NUM_LAWS 12
				207	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				208	#define CONFIG_SYS_NUM_FMAN 1
				209	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				210	#define CONFIG_NUM_DDR_CONTROLLERS 1
				211	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				212	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	213	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	214	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	215	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	216
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	217	#elif defined(CONFIG_P1020)
				218	#define CONFIG_MAX_CPUS 2
				219	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	220	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	221	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	222	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	223	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	224	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	225	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				226	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	227
				228	#elif defined(CONFIG_P1021)
				229	#define CONFIG_MAX_CPUS 2
				230	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	231	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	232	#define CONFIG_TSECV2
Prabhakar Kushwaha	b03a466	2011-02-01 15:55:58 +0000	[diff] [blame]	233	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	234	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	235	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	236	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				237	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	238	#define QE_MURAM_SIZE 0x6000UL
				239	#define MAX_QE_RISC 1
				240	#define QE_NUM_OF_SNUM 28
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	241
				242	#elif defined(CONFIG_P1022)
				243	#define CONFIG_MAX_CPUS 2
				244	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	245	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	246	#define CONFIG_TSECV2
				247	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	248	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	2d7534a	2011-01-30 17:06:20 -0600	[diff] [blame]	249	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				250	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				251	#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	252
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	253	#elif defined(CONFIG_P1023)
				254	#define CONFIG_MAX_CPUS 2
				255	#define CONFIG_SYS_FSL_NUM_LAWS 12
				256	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				257	#define CONFIG_SYS_NUM_FMAN 1
				258	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				259	#define CONFIG_NUM_DDR_CONTROLLERS 1
				260	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				261	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	262	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	263	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	264	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang	67a719d	2011-02-03 22:14:19 -0600	[diff] [blame]	265
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	266	/* P1024 is lower end variant of P1020 */
				267	#elif defined(CONFIG_P1024)
				268	#define CONFIG_MAX_CPUS 2
				269	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	270	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	271	#define CONFIG_TSECV2
				272	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				273	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	274	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	275	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				276	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				277
				278	/* P1025 is lower end variant of P1021 */
				279	#elif defined(CONFIG_P1025)
				280	#define CONFIG_MAX_CPUS 2
				281	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	282	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	283	#define CONFIG_TSECV2
				284	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				285	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	286	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	287	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				288	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	a52d2f8	2011-02-11 01:25:30 -0600	[diff] [blame]	289	#define QE_MURAM_SIZE 0x6000UL
				290	#define MAX_QE_RISC 1
				291	#define QE_NUM_OF_SNUM 28
Kumar Gala	093cffb	2011-02-05 13:45:07 -0600	[diff] [blame]	292
				293	/* P2010 is single core version of P2020 */
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	294	#elif defined(CONFIG_P2010)
				295	#define CONFIG_MAX_CPUS 1
				296	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	297	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	298	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	299	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	6e7f0bc0	2011-01-26 01:43:15 -0600	[diff] [blame]	300	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	5103a03	2011-01-29 15:36:10 -0600	[diff] [blame]	301	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	302
				303	#elif defined(CONFIG_P2020)
				304	#define CONFIG_MAX_CPUS 2
				305	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	ad75d44	2012-04-29 23:57:12 +0000	[diff] [blame]	306	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	307	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	308	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	6e7f0bc0	2011-01-26 01:43:15 -0600	[diff] [blame]	309	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	5103a03	2011-01-29 15:36:10 -0600	[diff] [blame]	310	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	311	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				312	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				313	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				314	#define CONFIG_SYS_FSL_RMU
				315	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	316
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	317	#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	318	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	319	#define CONFIG_MAX_CPUS 4
				320	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
				321	#define CONFIG_SYS_FSL_NUM_LAWS 32
				322	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				323	#define CONFIG_SYS_NUM_FMAN 1
				324	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				325	#define CONFIG_SYS_NUM_FM1_10GEC 1
				326	#define CONFIG_NUM_DDR_CONTROLLERS 1
				327	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				328	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				329	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	330	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	331	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				332	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	333	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	334	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	5e23ab0	2012-05-07 07:26:47 +0000	[diff] [blame]	335	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	336	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	337	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	338	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	339	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	19e4a00	2012-10-14 20:55:17 +0000	[diff] [blame]	340	#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	341	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				342	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				343	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	344	#define CONFIG_SYS_FSL_ERRATUM_A004510
				345	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				346	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				347	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	348	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	349	#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala	1f97987	2011-05-13 01:16:07 -0500	[diff] [blame]	350
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	351	#elif defined(CONFIG_PPC_P3041)
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	352	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	353	#define CONFIG_MAX_CPUS 4
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	354	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	355	#define CONFIG_SYS_FSL_NUM_LAWS 32
				356	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	fbee0f7	2011-01-25 12:42:32 -0600	[diff] [blame]	357	#define CONFIG_SYS_NUM_FMAN 1
				358	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				359	#define CONFIG_SYS_NUM_FM1_10GEC 1
				360	#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	361	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	362	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	363	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	364	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	86221f0	2011-04-13 00:08:51 -0500	[diff] [blame]	365	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				366	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	367	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3000976	2011-04-19 15:28:41 +0800	[diff] [blame]	368	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	57125f2	2012-08-08 18:04:53 +0000	[diff] [blame]	369	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	370	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	371	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	372	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	373	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	19e4a00	2012-10-14 20:55:17 +0000	[diff] [blame]	374	#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	375	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				376	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				377	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	378	#define CONFIG_SYS_FSL_ERRATUM_A004510
				379	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				380	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				381	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	382	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	383	#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	384
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	385	#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	386	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	387	#define CONFIG_MAX_CPUS 8
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	388	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	389	#define CONFIG_SYS_FSL_NUM_LAWS 32
				390	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				391	#define CONFIG_SYS_NUM_FMAN 2
				392	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				393	#define CONFIG_SYS_NUM_FM2_DTSEC 4
				394	#define CONFIG_SYS_NUM_FM1_10GEC 1
				395	#define CONFIG_SYS_NUM_FM2_10GEC 1
				396	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	397	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	398	#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	399	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	400	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	401	#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
				402	#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun	fa8d23c	2011-01-10 12:03:01 +0000	[diff] [blame]	403	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	404	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				405	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				406	#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R61911	4e0be34	2012-09-18 09:50:08 +0000	[diff] [blame]	407	#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	408	#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun	5e23ab0	2012-05-07 07:26:47 +0000	[diff] [blame]	409	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	410	#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medve	df8af0b	2010-08-31 22:57:38 -0500	[diff] [blame]	411	#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi	d90fdba	2011-04-18 17:16:00 -0500	[diff] [blame]	412	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi	da30b9f	2011-04-01 13:19:36 -0500	[diff] [blame]	413	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala	43f082b	2011-11-22 06:51:15 -0600	[diff] [blame]	414	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	415	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	19e4a00	2012-10-14 20:55:17 +0000	[diff] [blame]	416	#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	417	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				418	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				419	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				420	#define CONFIG_SYS_FSL_RMU
				421	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	422	#define CONFIG_SYS_FSL_ERRATUM_A004510
				423	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
				424	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	425	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	0118033	2012-10-25 12:40:00 +0000	[diff] [blame]	426	#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabi	d607b96	2012-11-01 08:20:23 +0000	[diff] [blame]	427	#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chen	c0a4e6b	2012-11-26 23:49:45 +0000	[diff] [blame]	428	#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	429
Scott Wood	3e978f5	2012-08-14 10:14:51 +0000	[diff] [blame]	430	#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun	ffd06e0	2012-10-08 07:44:30 +0000	[diff] [blame]	431	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	d1001e3	2012-10-08 07:44:15 +0000	[diff] [blame]	432	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	433	#define CONFIG_MAX_CPUS 2
Kumar Gala	b5c8753	2011-02-16 02:03:29 -0600	[diff] [blame]	434	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	435	#define CONFIG_SYS_FSL_NUM_LAWS 32
				436	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	fbee0f7	2011-01-25 12:42:32 -0600	[diff] [blame]	437	#define CONFIG_SYS_NUM_FMAN 1
				438	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				439	#define CONFIG_SYS_NUM_FM1_10GEC 1
				440	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	c657d89	2011-02-04 00:43:34 -0600	[diff] [blame]	441	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	66412c6	2011-02-18 05:40:54 -0600	[diff] [blame]	442	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	8f29084	2011-05-20 00:39:21 -0500	[diff] [blame]	443	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	444	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	86221f0	2011-04-13 00:08:51 -0500	[diff] [blame]	445	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				446	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	b6c3722	2011-04-13 00:19:10 -0500	[diff] [blame]	447	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3000976	2011-04-19 15:28:41 +0800	[diff] [blame]	448	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	449	#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sun	e22be77	2013-03-25 07:30:11 +0000	[diff] [blame]	450	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	4108508	2011-11-20 10:01:35 -0800	[diff] [blame]	451	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	19e4a00	2012-10-14 20:55:17 +0000	[diff] [blame]	452	#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang	7d67ed5	2012-03-08 00:33:14 +0000	[diff] [blame]	453	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				454	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				455	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	33eee33	2012-08-14 10:14:53 +0000	[diff] [blame]	456	#define CONFIG_SYS_FSL_ERRATUM_A004510
				457	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				458	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang	d59c557	2012-09-28 21:26:19 +0000	[diff] [blame]	459	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	460
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	461	#elif defined(CONFIG_PPC_P5040)
Timur Tabi	1956e43	2012-10-23 10:48:09 +0000	[diff] [blame]	462	#define CONFIG_SYS_PPC64
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	463	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
				464	#define CONFIG_MAX_CPUS 4
				465	#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
				466	#define CONFIG_SYS_FSL_NUM_LAWS 32
				467	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				468	#define CONFIG_SYS_NUM_FMAN 2
				469	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				470	#define CONFIG_SYS_NUM_FM1_10GEC 1
				471	#define CONFIG_SYS_NUM_FM2_DTSEC 5
				472	#define CONFIG_SYS_NUM_FM2_10GEC 1
				473	#define CONFIG_NUM_DDR_CONTROLLERS 2
				474	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				475	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				476	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				477	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				478	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				479	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				480	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				481	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	99d7b0a	2013-03-11 17:56:34 +0000	[diff] [blame]	482	#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	483	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
				484	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
				485	#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi	4905443	2012-10-05 11:09:19 +0000	[diff] [blame]	486	#define CONFIG_SYS_FSL_ERRATUM_A004510
				487	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				488	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
				489
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	490	#elif defined(CONFIG_BSC9131)
				491	#define CONFIG_MAX_CPUS 1
				492	#define CONFIG_FSL_SDHC_V2_3
				493	#define CONFIG_SYS_FSL_NUM_LAWS 12
				494	#define CONFIG_TSECV2
				495	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				496	#define CONFIG_NUM_DDR_CONTROLLERS 1
				497	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				498	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	19a8dbd	2012-04-24 20:16:49 +0000	[diff] [blame]	499	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				500
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	501	#elif defined(CONFIG_BSC9132)
				502	#define CONFIG_MAX_CPUS 2
				503	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				504	#define CONFIG_FSL_SDHC_V2_3
				505	#define CONFIG_SYS_FSL_NUM_LAWS 12
				506	#define CONFIG_TSECV2
				507	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				508	#define CONFIG_NUM_DDR_CONTROLLERS 2
				509	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				510	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	35fe948	2013-01-23 17:59:57 +0000	[diff] [blame]	511	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				512	#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
				513	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
				514
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	515	#elif defined(CONFIG_PPC_T4240)
York Sun	ffd06e0	2012-10-08 07:44:30 +0000	[diff] [blame]	516	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	517	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				518	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
				519	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
				520	#define CONFIG_MAX_CPUS 12
				521	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				522	#define CONFIG_SYS_FSL_NUM_LAWS 32
				523	#define CONFIG_SYS_FSL_SRDS_3
				524	#define CONFIG_SYS_FSL_SRDS_4
				525	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				526	#define CONFIG_SYS_NUM_FMAN 2
				527	#define CONFIG_SYS_NUM_FM1_DTSEC 8
				528	#define CONFIG_SYS_NUM_FM1_10GEC 2
				529	#define CONFIG_SYS_NUM_FM2_DTSEC 8
				530	#define CONFIG_SYS_NUM_FM2_10GEC 2
				531	#define CONFIG_NUM_DDR_CONTROLLERS 3
				532	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zang	111fd19	2012-10-08 07:44:21 +0000	[diff] [blame]	533	#define CONFIG_SYS_FMAN_V3
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	534	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				535	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				536	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
				537	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				538	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				539	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				540	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				541	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				542	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
York Sun	eb53941	2012-10-08 07:44:25 +0000	[diff] [blame]	543	#define CONFIG_SYS_FSL_ERRATUM_A004468
York Sun	a1d558a	2012-10-08 07:44:26 +0000	[diff] [blame]	544	#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu	72bd83c	2013-01-23 19:56:23 +0000	[diff] [blame]	545	#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun	9e75875	2012-10-08 07:44:19 +0000	[diff] [blame]	546	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				547
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	548	#elif defined(CONFIG_PPC_B4420)
				549	#define CONFIG_SYS_PPC64 /* 64-bit core */
				550	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				551	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
				552	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
				553	#define CONFIG_MAX_CPUS 2
				554	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
				555	#define CONFIG_SYS_FSL_NUM_LAWS 32
				556	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				557	#define CONFIG_SYS_NUM_FMAN 1
				558	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				559	#define CONFIG_NUM_DDR_CONTROLLERS 1
				560	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
				561	#define CONFIG_SYS_FMAN_V3
				562	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				563	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				564	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				565	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				566	#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu	04feb57	2013-02-27 21:56:54 +0000	[diff] [blame]	567	#define CONFIG_SYS_FSL_ERRATUM_A005871
Poonam Aggrwal	e1dbdd8	2012-12-23 19:24:16 +0000	[diff] [blame]	568	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				569
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	570	#elif defined(CONFIG_PPC_B4860)
York Sun	ffd06e0	2012-10-08 07:44:30 +0000	[diff] [blame]	571	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	572	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				573	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
				574	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
				575	#define CONFIG_MAX_CPUS 4
				576	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
				577	#define CONFIG_SYS_FSL_NUM_LAWS 32
				578	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				579	#define CONFIG_SYS_NUM_FMAN 1
				580	#define CONFIG_SYS_NUM_FM1_DTSEC 6
				581	#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwal	e394ceb	2012-12-23 19:22:33 +0000	[diff] [blame]	582	#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	583	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zang	111fd19	2012-10-08 07:44:21 +0000	[diff] [blame]	584	#define CONFIG_SYS_FMAN_V3
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	585	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				586	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				587	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				588	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				589	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				590	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				591	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				592	#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu	04feb57	2013-02-27 21:56:54 +0000	[diff] [blame]	593	#define CONFIG_SYS_FSL_ERRATUM_A005871
York Sun	d240414	2012-10-08 07:44:20 +0000	[diff] [blame]	594	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				595
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	596	#else
				597	#error Processor type not defined for this platform
				598	#endif
				599
Timur Tabi	e46fedf	2011-08-04 18:03:41 -0500	[diff] [blame]	600	#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
				601	#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
				602	#endif
				603
Kumar Gala	243be8e	2011-01-19 03:05:26 -0600	[diff] [blame]	604	#endif /* _ASM_MPC85xx_CONFIG_H_ */