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wdenkf4675562002-10-02 14:20:15 +00001/*
wdenkf12e5682003-07-07 20:07:54 +00002 * (C) Copyright 2000-2003
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
wdenk6aff3112002-12-17 01:51:00 +000042
wdenkf4675562002-10-02 14:20:15 +000043#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenk6aff3112002-12-17 01:51:00 +000044
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
wdenk6aff3112002-12-17 01:51:00 +000051#define CONFIG_PREBOOT "echo;" \
52 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
53 "echo"
wdenkf4675562002-10-02 14:20:15 +000054
55#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000056
57#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000058 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000059 "nfsargs=setenv bootargs root=/dev/nfs rw " \
60 "nfsroot=$(serverip):$(rootpath)\0" \
61 "ramargs=setenv bootargs root=/dev/ram rw\0" \
62 "addip=setenv bootargs $(bootargs) " \
63 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
64 ":$(hostname):$(netdev):off panic=1\0" \
65 "flash_nfs=run nfsargs addip;" \
66 "bootm $(kernel_addr)\0" \
67 "flash_self=run ramargs addip;" \
68 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
69 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
70 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenk5e4be002004-01-31 20:13:31 +000071 "bootfile=/tftpboot/TQM855L/uImage\0" \
wdenk6aff3112002-12-17 01:51:00 +000072 "kernel_addr=40040000\0" \
73 "ramdisk_addr=40100000\0" \
74 ""
75#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000076
77#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
79
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83
84#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
85
86#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
87
88#define CONFIG_MAC_PARTITION
89#define CONFIG_DOS_PARTITION
90
91#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
92
93#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk6aff3112002-12-17 01:51:00 +000094 CFG_CMD_ASKENV | \
wdenkf4675562002-10-02 14:20:15 +000095 CFG_CMD_DHCP | \
96 CFG_CMD_IDE | \
97 CFG_CMD_DATE )
98
99/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
100#include <cmd_confdefs.h>
101
102/*
103 * Miscellaneous configurable options
104 */
105#define CFG_LONGHELP /* undef to save memory */
wdenk6aff3112002-12-17 01:51:00 +0000106#define CFG_PROMPT "=> " /* Monitor Command Prompt */
107
108#if 0
109#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
110#endif
111#ifdef CFG_HUSH_PARSER
112#define CFG_PROMPT_HUSH_PS2 "> "
113#endif
114
wdenkf4675562002-10-02 14:20:15 +0000115#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk6aff3112002-12-17 01:51:00 +0000116#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000117#else
wdenk6aff3112002-12-17 01:51:00 +0000118#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000119#endif
120#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenk6aff3112002-12-17 01:51:00 +0000121#define CFG_MAXARGS 16 /* max number of command args */
wdenkf4675562002-10-02 14:20:15 +0000122#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
123
124#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
125#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
126
127#define CFG_LOAD_ADDR 0x100000 /* default load address */
128
wdenk6aff3112002-12-17 01:51:00 +0000129#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000130
131#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132
133/*
134 * Low Level Configuration Settings
135 * (address mappings, register initial values, etc.)
136 * You should know what you are doing if you make changes here.
137 */
138/*-----------------------------------------------------------------------
139 * Internal Memory Mapped Register
140 */
141#define CFG_IMMR 0xFFF00000
142
143/*-----------------------------------------------------------------------
144 * Definitions for initial stack pointer and data area (in DPRAM)
145 */
146#define CFG_INIT_RAM_ADDR CFG_IMMR
147#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
148#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
149#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
150#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
151
152/*-----------------------------------------------------------------------
153 * Start addresses for the final memory configuration
154 * (Set up by the startup code)
155 * Please note that CFG_SDRAM_BASE _must_ start at 0
156 */
157#define CFG_SDRAM_BASE 0x00000000
158#define CFG_FLASH_BASE 0x40000000
159#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
160#define CFG_MONITOR_BASE CFG_FLASH_BASE
161#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
162
163/*
164 * For booting Linux, the board info and command line data
165 * have to be in the first 8 MB of memory, since this is
166 * the maximum mapped by the Linux kernel during initialization.
167 */
168#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
169
170/*-----------------------------------------------------------------------
171 * FLASH organization
172 */
173#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenkaacf9a42003-01-17 16:27:01 +0000174#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000175
176#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
177#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
178
179#define CFG_ENV_IS_IN_FLASH 1
180#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
181#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
182
183/* Address and size of Redundant Environment Sector */
184#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
185#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
186
187/*-----------------------------------------------------------------------
188 * Hardware Information Block
189 */
190#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
191#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
192#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
193
194/*-----------------------------------------------------------------------
195 * Cache Configuration
196 */
197#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
198#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
199#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
200#endif
201
202/*-----------------------------------------------------------------------
203 * SYPCR - System Protection Control 11-9
204 * SYPCR can only be written once after reset!
205 *-----------------------------------------------------------------------
206 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
207 */
208#if defined(CONFIG_WATCHDOG)
209#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
210 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
211#else
212#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
213#endif
214
215/*-----------------------------------------------------------------------
216 * SIUMCR - SIU Module Configuration 11-6
217 *-----------------------------------------------------------------------
218 * PCMCIA config., multi-function pin tri-state
219 */
220#ifndef CONFIG_CAN_DRIVER
221#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
222#else /* we must activate GPL5 in the SIUMCR for CAN */
223#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
224#endif /* CONFIG_CAN_DRIVER */
225
226/*-----------------------------------------------------------------------
227 * TBSCR - Time Base Status and Control 11-26
228 *-----------------------------------------------------------------------
229 * Clear Reference Interrupt Status, Timebase freezing enabled
230 */
231#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
232
233/*-----------------------------------------------------------------------
234 * RTCSC - Real-Time Clock Status and Control Register 11-27
235 *-----------------------------------------------------------------------
236 */
237#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
238
239/*-----------------------------------------------------------------------
240 * PISCR - Periodic Interrupt Status and Control 11-31
241 *-----------------------------------------------------------------------
242 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
243 */
244#define CFG_PISCR (PISCR_PS | PISCR_PITF)
245
246/*-----------------------------------------------------------------------
247 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
248 *-----------------------------------------------------------------------
249 * Reset PLL lock status sticky bit, timer expired status bit and timer
250 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000251 */
wdenkf4675562002-10-02 14:20:15 +0000252#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000253
254/*-----------------------------------------------------------------------
255 * SCCR - System Clock and reset Control Register 15-27
256 *-----------------------------------------------------------------------
257 * Set clock output, timebase and RTC source and divider,
258 * power management and some other internal clocks
259 */
260#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000261#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000262 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
263 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000264
265/*-----------------------------------------------------------------------
266 * PCMCIA stuff
267 *-----------------------------------------------------------------------
268 *
269 */
270#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
271#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
272#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
273#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
274#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
275#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
276#define CFG_PCMCIA_IO_ADDR (0xEC000000)
277#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
278
279/*-----------------------------------------------------------------------
280 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
281 *-----------------------------------------------------------------------
282 */
283
284#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
285
286#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
287#undef CONFIG_IDE_LED /* LED for ide not supported */
288#undef CONFIG_IDE_RESET /* reset for ide not supported */
289
290#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
291#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
292
293#define CFG_ATA_IDE0_OFFSET 0x0000
294
295#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
296
297/* Offset for data I/O */
298#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
299
300/* Offset for normal register accesses */
301#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
302
303/* Offset for alternate registers */
304#define CFG_ATA_ALT_OFFSET 0x0100
305
wdenkf4675562002-10-02 14:20:15 +0000306/*-----------------------------------------------------------------------
307 *
308 *-----------------------------------------------------------------------
309 *
310 */
wdenkf4675562002-10-02 14:20:15 +0000311#define CFG_DER 0
312
313/*
314 * Init Memory Controller:
315 *
316 * BR0/1 and OR0/1 (FLASH)
317 */
318
319#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
320#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
321
322/* used to re-map FLASH both when starting from SRAM or FLASH:
323 * restrict access enough to keep SRAM working (if any)
324 * but not too much to meddle with FLASH accesses
325 */
326#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
327#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
328
329/*
330 * FLASH timing:
331 */
wdenkf4675562002-10-02 14:20:15 +0000332#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
333 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000334
335#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
336#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
337#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
338
339#define CFG_OR1_REMAP CFG_OR0_REMAP
340#define CFG_OR1_PRELIM CFG_OR0_PRELIM
341#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
342
343/*
344 * BR2/3 and OR2/3 (SDRAM)
345 *
346 */
347#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
348#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
349#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
350
351/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
352#define CFG_OR_TIMING_SDRAM 0x00000A00
353
354#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
355#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
356
357#ifndef CONFIG_CAN_DRIVER
358#define CFG_OR3_PRELIM CFG_OR2_PRELIM
359#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
360#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
361#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
362#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
363#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
364#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
365 BR_PS_8 | BR_MS_UPMB | BR_V )
366#endif /* CONFIG_CAN_DRIVER */
367
368/*
369 * Memory Periodic Timer Prescaler
370 *
371 * The Divider for PTA (refresh timer) configuration is based on an
372 * example SDRAM configuration (64 MBit, one bank). The adjustment to
373 * the number of chip selects (NCS) and the actually needed refresh
374 * rate is done by setting MPTPR.
375 *
376 * PTA is calculated from
377 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
378 *
379 * gclk CPU clock (not bus clock!)
380 * Trefresh Refresh cycle * 4 (four word bursts used)
381 *
382 * 4096 Rows from SDRAM example configuration
383 * 1000 factor s -> ms
384 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
385 * 4 Number of refresh cycles per period
386 * 64 Refresh cycle in ms per number of rows
387 * --------------------------------------------
388 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
389 *
390 * 50 MHz => 50.000.000 / Divider = 98
391 * 66 Mhz => 66.000.000 / Divider = 129
392 * 80 Mhz => 80.000.000 / Divider = 156
393 */
wdenke9132ea2004-04-24 23:23:30 +0000394
395#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
396#define CFG_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000397
398/*
399 * For 16 MBit, refresh rates could be 31.3 us
400 * (= 64 ms / 2K = 125 / quad bursts).
401 * For a simpler initialization, 15.6 us is used instead.
402 *
403 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
404 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
405 */
406#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
407#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
408
409/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
410#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
411#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
412
413/*
414 * MAMR settings for SDRAM
415 */
416
417/* 8 column SDRAM */
418#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
419 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
420 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
421/* 9 column SDRAM */
422#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
423 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
424 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
425
426
427/*
428 * Internal Definitions
429 *
430 * Boot Flags
431 */
432#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
433#define BOOTFLAG_WARM 0x02 /* Software reboot */
434
435#define CONFIG_SCC1_ENET
wdenk6aff3112002-12-17 01:51:00 +0000436#define CONFIG_FEC_ENET
437#define CONFIG_ETHPRIME "SCC ETHERNET"
wdenkf4675562002-10-02 14:20:15 +0000438
439#endif /* __CONFIG_H */