blob: 6c0dd3f267069c572acc672b403ff75dacba7d0e [file] [log] [blame]
Mingkai Huf3a8e2b2015-10-26 19:47:52 +08001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <asm/io.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/fsl_serdes.h>
12#include <asm/arch/soc.h>
13#include <hwconfig.h>
14#include <ahci.h>
15#include <scsi.h>
Shaohui Xiee8297342015-10-26 19:47:54 +080016#include <fm_eth.h>
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080017#include <fsl_csu.h>
18#include <fsl_esdhc.h>
19#include <fsl_ifc.h>
20#include "cpld.h"
21
22DECLARE_GLOBAL_DATA_PTR;
23
24int checkboard(void)
25{
26 static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
27 u8 cfg_rcw_src1, cfg_rcw_src2;
28 u32 cfg_rcw_src;
29 u32 sd1refclk_sel;
30
31 printf("Board: LS1043ARDB, boot from ");
32
33 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
34 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
35 cpld_rev_bit(&cfg_rcw_src1);
36 cfg_rcw_src = cfg_rcw_src1;
37 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
38
39 if (cfg_rcw_src == 0x25)
40 printf("vBank %d\n", CPLD_READ(vbank));
41 else if (cfg_rcw_src == 0x106)
42 puts("NAND\n");
43 else
44 printf("Invalid setting of SW4\n");
45
46 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
47 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
48
49 puts("SERDES Reference Clocks:\n");
50 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
51 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
52
53 return 0;
54}
55
56int dram_init(void)
57{
58 gd->ram_size = initdram(0);
59
60 return 0;
61}
62
63int board_early_init_f(void)
64{
65 fsl_lsch2_early_init_f();
66 return 0;
67}
68
69int board_init(void)
70{
71 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
72
73 /*
74 * Set CCI-400 control override register to enable barrier
75 * transaction
76 */
77 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
78
79#ifdef CONFIG_FSL_IFC
80 init_final_memctl_regs();
81#endif
82
83#ifdef CONFIG_ENV_IS_NOWHERE
84 gd->env_addr = (ulong)&default_environment[0];
85#endif
86
87#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
88 enable_layerscape_ns_access();
89#endif
90
91 return 0;
92}
93
94int config_board_mux(void)
95{
96 return 0;
97}
98
99#if defined(CONFIG_MISC_INIT_R)
100int misc_init_r(void)
101{
102 config_board_mux();
103
104 return 0;
105}
106#endif
107
108int ft_board_setup(void *blob, bd_t *bd)
109{
110 ft_cpu_setup(blob, bd);
111
Shaohui Xiee8297342015-10-26 19:47:54 +0800112#ifdef CONFIG_SYS_DPAA_FMAN
113 fdt_fixup_fman_ethernet(blob);
114#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800115 return 0;
116}
117
118u8 flash_read8(void *addr)
119{
120 return __raw_readb(addr + 1);
121}
122
123void flash_write16(u16 val, void *addr)
124{
125 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
126
127 __raw_writew(shftval, addr);
128}
129
130u16 flash_read16(void *addr)
131{
132 u16 val = __raw_readw(addr);
133
134 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
135}