blob: 24130e620bf76a4ac4b86b28ef4c6c78503abc7f [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasute94cad92018-04-08 15:22:58 +02002/*
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
Marek Vasute94cad92018-04-08 15:22:58 +02004 */
5
6#include <common.h>
Marek Vasutd2661d82020-04-04 12:45:04 +02007#include <bouncebuf.h>
Marek Vasute94cad92018-04-08 15:22:58 +02008#include <clk.h>
9#include <fdtdec.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070011#include <malloc.h>
Marek Vasute94cad92018-04-08 15:22:58 +020012#include <mmc.h>
13#include <dm.h>
Simon Glass336d4612020-02-03 07:36:16 -070014#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Marek Vasute94cad92018-04-08 15:22:58 +020016#include <linux/compat.h>
Simon Glassc05ed002020-05-10 11:40:11 -060017#include <linux/delay.h>
Marek Vasute94cad92018-04-08 15:22:58 +020018#include <linux/dma-direction.h>
19#include <linux/io.h>
20#include <linux/sizes.h>
21#include <power/regulator.h>
22#include <asm/unaligned.h>
Marek Vasutcb0b6b02018-04-13 23:51:33 +020023#include "tmio-common.h"
Marek Vasute94cad92018-04-08 15:22:58 +020024
Marek Vasut50aa1d92018-06-13 08:02:55 +020025#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
26 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
27 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
Marek Vasutf63968b2018-04-08 19:09:17 +020028
29/* SCC registers */
30#define RENESAS_SDHI_SCC_DTCNTL 0x800
Marek Vasut1bac2b62019-05-19 02:33:06 +020031#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
32#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
33#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
Marek Vasutf63968b2018-04-08 19:09:17 +020034#define RENESAS_SDHI_SCC_TAPSET 0x804
35#define RENESAS_SDHI_SCC_DT2FF 0x808
36#define RENESAS_SDHI_SCC_CKSEL 0x80c
Marek Vasut1bac2b62019-05-19 02:33:06 +020037#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
38#define RENESAS_SDHI_SCC_RVSCNTL 0x810
39#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
Marek Vasutf63968b2018-04-08 19:09:17 +020040#define RENESAS_SDHI_SCC_RVSREQ 0x814
Marek Vasut1bac2b62019-05-19 02:33:06 +020041#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
Marek Vasut69000662019-11-23 13:36:23 +010042#define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
43#define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
Marek Vasutf63968b2018-04-08 19:09:17 +020044#define RENESAS_SDHI_SCC_SMPCMP 0x818
Marek Vasut69000662019-11-23 13:36:23 +010045#define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
46#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
47#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
Marek Vasut1bac2b62019-05-19 02:33:06 +020048#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
49#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
50#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
Marek Vasutb5900a52019-05-19 03:47:07 +020051#define RENESAS_SDHI_SCC_TMPPORT3 0x828
52#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
53#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
54#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
55#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
56#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
57#define RENESAS_SDHI_SCC_TMPPORT4 0x82c
58#define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
59#define RENESAS_SDHI_SCC_TMPPORT5 0x830
60#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
61#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
62#define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
63#define RENESAS_SDHI_SCC_TMPPORT6 0x834
64#define RENESAS_SDHI_SCC_TMPPORT7 0x838
65#define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
66#define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
67#define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
Marek Vasutf63968b2018-04-08 19:09:17 +020068
69#define RENESAS_SDHI_MAX_TAP 3
70
Marek Vasut56b0bb92019-11-23 13:36:25 +010071#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
72
73static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
74 { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
75 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
76 { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
77 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
78};
79
80static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
81 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
82 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
83 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
84 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
85};
86
87static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
88 { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
89 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
90 { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
91 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
92};
93
94static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
95 { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
96 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
97 { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
98 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
99};
100
101static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
102 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
103 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
104 { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
105 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
106};
107
108static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
109{
110 /* On R-Car Gen3, MMC0 is at 0xee140000 */
111 return (uintptr_t)(priv->regbase) == 0xee140000;
112}
113
Marek Vasutb5900a52019-05-19 03:47:07 +0200114static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
115{
116 /* read mode */
117 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
118 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
119 RENESAS_SDHI_SCC_TMPPORT5);
120
121 /* access start and stop */
122 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
123 RENESAS_SDHI_SCC_TMPPORT4);
124 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
125
126 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
127}
128
129static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
130{
131 /* write mode */
132 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
133 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
134 RENESAS_SDHI_SCC_TMPPORT5);
135 tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
136
137 /* access start and stop */
138 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
139 RENESAS_SDHI_SCC_TMPPORT4);
140 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
141}
142
Marek Vasut69000662019-11-23 13:36:23 +0100143static bool renesas_sdhi_check_scc_error(struct udevice *dev)
144{
145 struct tmio_sd_priv *priv = dev_get_priv(dev);
146 struct mmc *mmc = mmc_get_mmc_dev(dev);
147 unsigned long new_tap = priv->tap_set;
Marek Vasut1bdcb832019-11-23 13:36:24 +0100148 unsigned long error_tap = priv->tap_set;
Marek Vasut69000662019-11-23 13:36:23 +0100149 u32 reg, smpcmp;
150
151 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
152 (mmc->selected_mode != UHS_SDR104) &&
153 (mmc->selected_mode != MMC_HS_200) &&
154 (mmc->selected_mode != MMC_HS_400) &&
155 (priv->nrtaps != 4))
156 return false;
157
158 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
159 /* Handle automatic tuning correction */
160 if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
161 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
162 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
163 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
164 return true;
165 }
166
167 return false;
168 }
169
170 /* Handle manual tuning correction */
171 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
172 if (!reg) /* No error */
173 return false;
174
175 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
176
177 if (mmc->selected_mode == MMC_HS_400) {
178 /*
179 * Correction Error Status contains CMD and DAT signal status.
180 * In HS400, DAT signal based on DS signal, not CLK.
181 * Therefore, use only CMD status.
182 */
183 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
184 RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
185
186 switch (smpcmp) {
187 case 0:
188 return false; /* No error in CMD signal */
189 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
190 new_tap = (priv->tap_set +
191 priv->tap_num + 1) % priv->tap_num;
Marek Vasut1bdcb832019-11-23 13:36:24 +0100192 error_tap = (priv->tap_set +
193 priv->tap_num - 1) % priv->tap_num;
Marek Vasut69000662019-11-23 13:36:23 +0100194 break;
195 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
196 new_tap = (priv->tap_set +
197 priv->tap_num - 1) % priv->tap_num;
Marek Vasut1bdcb832019-11-23 13:36:24 +0100198 error_tap = (priv->tap_set +
199 priv->tap_num + 1) % priv->tap_num;
Marek Vasut69000662019-11-23 13:36:23 +0100200 break;
201 default:
202 return true; /* Need re-tune */
203 }
204
Marek Vasut1bdcb832019-11-23 13:36:24 +0100205 if (priv->hs400_bad_tap & BIT(new_tap)) {
206 /*
207 * New tap is bad tap (cannot change).
208 * Compare with HS200 tuning result.
209 * In HS200 tuning, when smpcmp[error_tap]
210 * is OK, retune is executed.
211 */
212 if (priv->smpcmp & BIT(error_tap))
213 return true; /* Need retune */
214
215 return false; /* cannot change */
216 }
217
Marek Vasut69000662019-11-23 13:36:23 +0100218 priv->tap_set = new_tap;
219 } else {
220 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
221 return true; /* Need re-tune */
222 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
223 priv->tap_set = (priv->tap_set +
224 priv->tap_num + 1) % priv->tap_num;
225 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
226 priv->tap_set = (priv->tap_set +
227 priv->tap_num - 1) % priv->tap_num;
228 else
229 return false;
230 }
231
232 /* Set TAP position */
233 tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
234 RENESAS_SDHI_SCC_TAPSET);
235
236 return false;
237}
238
Marek Vasutb5900a52019-05-19 03:47:07 +0200239static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
240{
241 u32 calib_code;
242
243 if (!priv->adjust_hs400_enable)
244 return;
245
246 if (!priv->needs_adjust_hs400)
247 return;
248
Marek Vasut56b0bb92019-11-23 13:36:25 +0100249 if (!priv->adjust_hs400_calib_table)
250 return;
251
Marek Vasutb5900a52019-05-19 03:47:07 +0200252 /*
253 * Enabled Manual adjust HS400 mode
254 *
255 * 1) Disabled Write Protect
256 * W(addr=0x00, WP_DISABLE_CODE)
Marek Vasut56b0bb92019-11-23 13:36:25 +0100257 *
258 * 2) Read Calibration code
259 * read_value = R(addr=0x26)
260 * 3) Refer to calibration table
261 * Calibration code = table[read_value]
262 * 4) Enabled Manual Calibration
Marek Vasutb5900a52019-05-19 03:47:07 +0200263 * W(addr=0x22, manual mode | Calibration code)
Marek Vasut56b0bb92019-11-23 13:36:25 +0100264 * 5) Set Offset value to TMPPORT3 Reg
Marek Vasutb5900a52019-05-19 03:47:07 +0200265 */
266 sd_scc_tmpport_write32(priv, 0x00,
267 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
268 calib_code = sd_scc_tmpport_read32(priv, 0x26);
269 calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
Marek Vasutb5900a52019-05-19 03:47:07 +0200270 sd_scc_tmpport_write32(priv, 0x22,
271 RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
Marek Vasut56b0bb92019-11-23 13:36:25 +0100272 priv->adjust_hs400_calib_table[calib_code]);
Marek Vasutb5900a52019-05-19 03:47:07 +0200273 tmio_sd_writel(priv, priv->adjust_hs400_offset,
274 RENESAS_SDHI_SCC_TMPPORT3);
275
276 /* Clear flag */
277 priv->needs_adjust_hs400 = false;
278}
279
280static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
281{
282
283 /* Disabled Manual adjust HS400 mode
284 *
285 * 1) Disabled Write Protect
286 * W(addr=0x00, WP_DISABLE_CODE)
287 * 2) Disabled Manual Calibration
288 * W(addr=0x22, 0)
289 * 3) Clear offset value to TMPPORT3 Reg
290 */
291 sd_scc_tmpport_write32(priv, 0x00,
292 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
293 sd_scc_tmpport_write32(priv, 0x22, 0);
294 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
295}
296
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200297static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
Marek Vasutf63968b2018-04-08 19:09:17 +0200298{
299 u32 reg;
300
301 /* Initialize SCC */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200302 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
Marek Vasutf63968b2018-04-08 19:09:17 +0200303
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200304 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
305 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
306 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200307
308 /* Set sampling clock selection range */
Marek Vasuta376dde2018-06-13 08:02:55 +0200309 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
310 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
311 RENESAS_SDHI_SCC_DTCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200312
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200313 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200314 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200315 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200316
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200317 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200318 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200319 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200320
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200321 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
Marek Vasutf63968b2018-04-08 19:09:17 +0200322 RENESAS_SDHI_SCC_DT2FF);
323
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200324 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
325 reg |= TMIO_SD_CLKCTL_SCLKEN;
326 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200327
328 /* Read TAPNUM */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200329 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
Marek Vasutf63968b2018-04-08 19:09:17 +0200330 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
331 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
332}
333
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200334static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
Marek Vasutf63968b2018-04-08 19:09:17 +0200335{
336 u32 reg;
337
338 /* Reset SCC */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200339 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
340 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
341 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200342
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200343 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200344 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200345 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200346
Marek Vasutdc1488f2018-06-13 08:02:55 +0200347 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
348 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
349 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
350 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
351
Marek Vasutb5900a52019-05-19 03:47:07 +0200352 /* Disable HS400 mode adjustment */
353 renesas_sdhi_adjust_hs400_mode_disable(priv);
354
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200355 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
356 reg |= TMIO_SD_CLKCTL_SCLKEN;
357 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200358
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200359 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200360 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200361 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200362
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200363 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200364 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200365 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200366}
367
Marek Vasut50aa1d92018-06-13 08:02:55 +0200368static int renesas_sdhi_hs400(struct udevice *dev)
369{
370 struct tmio_sd_priv *priv = dev_get_priv(dev);
371 struct mmc *mmc = mmc_get_mmc_dev(dev);
372 bool hs400 = (mmc->selected_mode == MMC_HS_400);
373 int ret, taps = hs400 ? priv->nrtaps : 8;
Marek Vasut1bdcb832019-11-23 13:36:24 +0100374 unsigned long new_tap;
Marek Vasut50aa1d92018-06-13 08:02:55 +0200375 u32 reg;
376
377 if (taps == 4) /* HS400 on 4tap SoC needs different clock */
378 ret = clk_set_rate(&priv->clk, 400000000);
379 else
380 ret = clk_set_rate(&priv->clk, 200000000);
381 if (ret < 0)
382 return ret;
383
Marek Vasut8f39b032019-11-23 13:36:22 +0100384 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
385 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
386 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasut50aa1d92018-06-13 08:02:55 +0200387
388 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
389 if (hs400) {
390 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
391 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
392 } else {
393 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
394 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
395 }
396
397 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
398
Marek Vasutb5900a52019-05-19 03:47:07 +0200399 /* Disable HS400 mode adjustment */
400 if (!hs400)
401 renesas_sdhi_adjust_hs400_mode_disable(priv);
402
Marek Vasutba41c452019-02-19 19:32:28 +0100403 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
Marek Vasut50aa1d92018-06-13 08:02:55 +0200404 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
405 RENESAS_SDHI_SCC_DTCNTL);
406
Marek Vasut1bdcb832019-11-23 13:36:24 +0100407 /* Avoid bad TAP */
408 if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
409 new_tap = (priv->tap_set +
410 priv->tap_num + 1) % priv->tap_num;
411
412 if (priv->hs400_bad_tap & BIT(new_tap))
413 new_tap = (priv->tap_set +
414 priv->tap_num - 1) % priv->tap_num;
415
416 if (priv->hs400_bad_tap & BIT(new_tap)) {
417 new_tap = priv->tap_set;
418 debug("Three consecutive bad tap is prohibited\n");
419 }
420
421 priv->tap_set = new_tap;
422 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
423 }
424
Marek Vasut50aa1d92018-06-13 08:02:55 +0200425 if (taps == 4) {
426 tmio_sd_writel(priv, priv->tap_set >> 1,
427 RENESAS_SDHI_SCC_TAPSET);
Marek Vasutdc419fc2019-11-23 13:36:20 +0100428 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
429 RENESAS_SDHI_SCC_DT2FF);
Marek Vasut50aa1d92018-06-13 08:02:55 +0200430 } else {
431 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
Marek Vasutdc419fc2019-11-23 13:36:20 +0100432 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
Marek Vasut50aa1d92018-06-13 08:02:55 +0200433 }
434
435 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
436 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
437 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
438
Marek Vasutb5900a52019-05-19 03:47:07 +0200439 /* Execute adjust hs400 offset after setting to HS400 mode */
440 if (hs400)
441 priv->needs_adjust_hs400 = true;
442
Marek Vasut50aa1d92018-06-13 08:02:55 +0200443 return 0;
444}
445
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200446static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
Marek Vasutf63968b2018-04-08 19:09:17 +0200447 unsigned long tap)
448{
449 /* Set sampling clock position */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200450 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
Marek Vasutf63968b2018-04-08 19:09:17 +0200451}
452
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200453static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
Marek Vasutf63968b2018-04-08 19:09:17 +0200454{
455 /* Get comparison of sampling data */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200456 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
Marek Vasutf63968b2018-04-08 19:09:17 +0200457}
458
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200459static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
Marek Vasut37c39902019-11-23 13:36:18 +0100460 unsigned int taps)
Marek Vasutf63968b2018-04-08 19:09:17 +0200461{
462 unsigned long tap_cnt; /* counter of tuning success */
Marek Vasutf63968b2018-04-08 19:09:17 +0200463 unsigned long tap_start;/* start position of tuning success */
464 unsigned long tap_end; /* end position of tuning success */
465 unsigned long ntap; /* temporary counter of tuning success */
466 unsigned long match_cnt;/* counter of matching data */
467 unsigned long i;
468 bool select = false;
469 u32 reg;
470
Marek Vasutb5900a52019-05-19 03:47:07 +0200471 priv->needs_adjust_hs400 = false;
472
Marek Vasutf63968b2018-04-08 19:09:17 +0200473 /* Clear SCC_RVSREQ */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200474 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
Marek Vasutf63968b2018-04-08 19:09:17 +0200475
476 /* Merge the results */
Marek Vasut0196a582019-11-23 13:36:17 +0100477 for (i = 0; i < priv->tap_num * 2; i++) {
Marek Vasutf63968b2018-04-08 19:09:17 +0200478 if (!(taps & BIT(i))) {
Marek Vasut0196a582019-11-23 13:36:17 +0100479 taps &= ~BIT(i % priv->tap_num);
480 taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
Marek Vasutf63968b2018-04-08 19:09:17 +0200481 }
Marek Vasut37c39902019-11-23 13:36:18 +0100482 if (!(priv->smpcmp & BIT(i))) {
483 priv->smpcmp &= ~BIT(i % priv->tap_num);
484 priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
Marek Vasutf63968b2018-04-08 19:09:17 +0200485 }
486 }
487
488 /*
489 * Find the longest consecutive run of successful probes. If that
490 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
491 * center index as the tap.
492 */
493 tap_cnt = 0;
494 ntap = 0;
495 tap_start = 0;
496 tap_end = 0;
Marek Vasut0196a582019-11-23 13:36:17 +0100497 for (i = 0; i < priv->tap_num * 2; i++) {
Marek Vasutf63968b2018-04-08 19:09:17 +0200498 if (taps & BIT(i))
499 ntap++;
500 else {
501 if (ntap > tap_cnt) {
502 tap_start = i - ntap;
503 tap_end = i - 1;
504 tap_cnt = ntap;
505 }
506 ntap = 0;
507 }
508 }
509
510 if (ntap > tap_cnt) {
511 tap_start = i - ntap;
512 tap_end = i - 1;
513 tap_cnt = ntap;
514 }
515
516 /*
517 * If all of the TAP is OK, the sampling clock position is selected by
518 * identifying the change point of data.
519 */
Marek Vasut0196a582019-11-23 13:36:17 +0100520 if (tap_cnt == priv->tap_num * 2) {
Marek Vasutf63968b2018-04-08 19:09:17 +0200521 match_cnt = 0;
522 ntap = 0;
523 tap_start = 0;
524 tap_end = 0;
Marek Vasut0196a582019-11-23 13:36:17 +0100525 for (i = 0; i < priv->tap_num * 2; i++) {
Marek Vasut37c39902019-11-23 13:36:18 +0100526 if (priv->smpcmp & BIT(i))
Marek Vasutf63968b2018-04-08 19:09:17 +0200527 ntap++;
528 else {
529 if (ntap > match_cnt) {
530 tap_start = i - ntap;
531 tap_end = i - 1;
532 match_cnt = ntap;
533 }
534 ntap = 0;
535 }
536 }
537 if (ntap > match_cnt) {
538 tap_start = i - ntap;
539 tap_end = i - 1;
540 match_cnt = ntap;
541 }
542 if (match_cnt)
543 select = true;
544 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
545 select = true;
546
547 if (select)
Marek Vasut0196a582019-11-23 13:36:17 +0100548 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
Marek Vasutf63968b2018-04-08 19:09:17 +0200549 else
550 return -EIO;
551
552 /* Set SCC */
Marek Vasut95ead3d2018-06-13 08:02:55 +0200553 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
Marek Vasutf63968b2018-04-08 19:09:17 +0200554
555 /* Enable auto re-tuning */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200556 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200557 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200558 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
Marek Vasutf63968b2018-04-08 19:09:17 +0200559
560 return 0;
561}
562
563int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
564{
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200565 struct tmio_sd_priv *priv = dev_get_priv(dev);
Marek Vasutf63968b2018-04-08 19:09:17 +0200566 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
567 struct mmc *mmc = upriv->mmc;
568 unsigned int tap_num;
Marek Vasut37c39902019-11-23 13:36:18 +0100569 unsigned int taps = 0;
Marek Vasutf63968b2018-04-08 19:09:17 +0200570 int i, ret = 0;
571 u32 caps;
572
573 /* Only supported on Renesas RCar */
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200574 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
Marek Vasutf63968b2018-04-08 19:09:17 +0200575 return -EINVAL;
576
577 /* clock tuning is not needed for upto 52MHz */
578 if (!((mmc->selected_mode == MMC_HS_200) ||
Marek Vasut50aa1d92018-06-13 08:02:55 +0200579 (mmc->selected_mode == MMC_HS_400) ||
Marek Vasutf63968b2018-04-08 19:09:17 +0200580 (mmc->selected_mode == UHS_SDR104) ||
581 (mmc->selected_mode == UHS_SDR50)))
582 return 0;
583
584 tap_num = renesas_sdhi_init_tuning(priv);
585 if (!tap_num)
586 /* Tuning is not supported */
587 goto out;
588
Marek Vasut0196a582019-11-23 13:36:17 +0100589 priv->tap_num = tap_num;
590
591 if (priv->tap_num * 2 >= sizeof(taps) * 8) {
Marek Vasutf63968b2018-04-08 19:09:17 +0200592 dev_err(dev,
593 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
594 goto out;
595 }
596
Marek Vasut37c39902019-11-23 13:36:18 +0100597 priv->smpcmp = 0;
598
Marek Vasutf63968b2018-04-08 19:09:17 +0200599 /* Issue CMD19 twice for each tap */
Marek Vasut0196a582019-11-23 13:36:17 +0100600 for (i = 0; i < 2 * priv->tap_num; i++) {
601 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
Marek Vasutf63968b2018-04-08 19:09:17 +0200602
603 /* Force PIO for the tuning */
604 caps = priv->caps;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200605 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
Marek Vasutf63968b2018-04-08 19:09:17 +0200606
607 ret = mmc_send_tuning(mmc, opcode, NULL);
608
609 priv->caps = caps;
610
611 if (ret == 0)
612 taps |= BIT(i);
613
614 ret = renesas_sdhi_compare_scc_data(priv);
615 if (ret == 0)
Marek Vasut37c39902019-11-23 13:36:18 +0100616 priv->smpcmp |= BIT(i);
Marek Vasutf63968b2018-04-08 19:09:17 +0200617
618 mdelay(1);
619 }
620
Marek Vasut37c39902019-11-23 13:36:18 +0100621 ret = renesas_sdhi_select_tuning(priv, taps);
Marek Vasutf63968b2018-04-08 19:09:17 +0200622
623out:
624 if (ret < 0) {
625 dev_warn(dev, "Tuning procedure failed\n");
626 renesas_sdhi_reset_tuning(priv);
627 }
628
629 return ret;
630}
Marek Vasut50aa1d92018-06-13 08:02:55 +0200631#else
632static int renesas_sdhi_hs400(struct udevice *dev)
633{
634 return 0;
635}
Marek Vasutf63968b2018-04-08 19:09:17 +0200636#endif
637
638static int renesas_sdhi_set_ios(struct udevice *dev)
639{
Marek Vasut50aa1d92018-06-13 08:02:55 +0200640 struct tmio_sd_priv *priv = dev_get_priv(dev);
641 u32 tmp;
642 int ret;
643
644 /* Stop the clock before changing its rate to avoid a glitch signal */
645 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
646 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
647 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
648
649 ret = renesas_sdhi_hs400(dev);
650 if (ret)
651 return ret;
652
653 ret = tmio_sd_set_ios(dev);
Marek Vasutcf39f3f2018-04-09 20:47:31 +0200654
655 mdelay(10);
656
Marek Vasut50aa1d92018-06-13 08:02:55 +0200657#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
658 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
659 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
660 struct mmc *mmc = mmc_get_mmc_dev(dev);
661 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
662 (mmc->selected_mode != UHS_SDR104) &&
663 (mmc->selected_mode != MMC_HS_200) &&
664 (mmc->selected_mode != MMC_HS_400)) {
Marek Vasut52e17962018-10-28 15:30:06 +0100665 renesas_sdhi_reset_tuning(priv);
Marek Vasut50aa1d92018-06-13 08:02:55 +0200666 }
Marek Vasutf63968b2018-04-08 19:09:17 +0200667#endif
668
669 return ret;
670}
671
Marek Vasut2fc10752018-10-28 19:28:56 +0100672#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300673static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
674 int timeout_us)
Marek Vasut2fc10752018-10-28 19:28:56 +0100675{
676 int ret = -ETIMEDOUT;
677 bool dat0_high;
678 bool target_dat0_high = !!state;
679 struct tmio_sd_priv *priv = dev_get_priv(dev);
680
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300681 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
682 while (timeout_us--) {
Marek Vasut2fc10752018-10-28 19:28:56 +0100683 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
684 if (dat0_high == target_dat0_high) {
685 ret = 0;
686 break;
687 }
688 udelay(10);
689 }
690
691 return ret;
692}
693#endif
694
Marek Vasutd2661d82020-04-04 12:45:04 +0200695#define RENESAS_SDHI_DMA_ALIGNMENT 128
696
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200697static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
698 size_t len, size_t len_aligned)
Marek Vasutd2661d82020-04-04 12:45:04 +0200699{
Marek Vasutd2661d82020-04-04 12:45:04 +0200700 /* Check if start is aligned */
701 if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200702 debug("Unaligned buffer address %lx\n", ubuf);
Marek Vasutd2661d82020-04-04 12:45:04 +0200703 return 0;
704 }
705
706 /* Check if length is aligned */
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200707 if (len != len_aligned) {
708 debug("Unaligned buffer length %zu\n", len);
Marek Vasutd2661d82020-04-04 12:45:04 +0200709 return 0;
710 }
711
712#ifdef CONFIG_PHYS_64BIT
713 /* Check if below 32bit boundary */
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200714 if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
715 debug("Buffer above 32bit boundary %lx-%lx\n",
716 ubuf, ubuf + len_aligned);
Marek Vasutd2661d82020-04-04 12:45:04 +0200717 return 0;
718 }
719#endif
720
721 /* Aligned */
722 return 1;
723}
724
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200725static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
726{
727 uintptr_t ubuf = (uintptr_t)state->user_buffer;
728
729 return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
730 state->len_aligned);
731}
732
Marek Vasutb5900a52019-05-19 03:47:07 +0200733static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
734 struct mmc_data *data)
735{
Marek Vasutd2661d82020-04-04 12:45:04 +0200736 struct bounce_buffer bbstate;
737 unsigned int bbflags;
738 bool bbok = false;
739 size_t len;
740 void *buf;
Marek Vasutb5900a52019-05-19 03:47:07 +0200741 int ret;
742
Marek Vasutd2661d82020-04-04 12:45:04 +0200743 if (data) {
744 if (data->flags & MMC_DATA_READ) {
745 buf = data->dest;
746 bbflags = GEN_BB_WRITE;
747 } else {
748 buf = (void *)data->src;
749 bbflags = GEN_BB_READ;
750 }
751 len = data->blocks * data->blocksize;
752
753 ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
754 RENESAS_SDHI_DMA_ALIGNMENT,
755 renesas_sdhi_addr_aligned);
756 /*
757 * If the amount of data to transfer is too large, we can get
758 * -ENOMEM when starting the bounce buffer. If that happens,
759 * fall back to PIO as it was before, otherwise use the BB.
760 */
761 if (!ret) {
762 bbok = true;
763 if (data->flags & MMC_DATA_READ)
764 data->dest = bbstate.bounce_buffer;
765 else
766 data->src = bbstate.bounce_buffer;
767 }
768 }
769
Marek Vasutb5900a52019-05-19 03:47:07 +0200770 ret = tmio_sd_send_cmd(dev, cmd, data);
Marek Vasutd2661d82020-04-04 12:45:04 +0200771
772 if (data && bbok) {
773 buf = bbstate.user_buffer;
774
775 bounce_buffer_stop(&bbstate);
776
777 if (data->flags & MMC_DATA_READ)
778 data->dest = buf;
779 else
780 data->src = buf;
781 }
782
Marek Vasutb5900a52019-05-19 03:47:07 +0200783 if (ret)
784 return ret;
785
786#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
787 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
788 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
789 struct tmio_sd_priv *priv = dev_get_priv(dev);
790
Marek Vasut69000662019-11-23 13:36:23 +0100791 renesas_sdhi_check_scc_error(dev);
792
Marek Vasutb5900a52019-05-19 03:47:07 +0200793 if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
794 renesas_sdhi_adjust_hs400_mode_enable(priv);
795#endif
796
797 return 0;
798}
799
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200800int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
801{
802 struct tmio_sd_priv *priv = dev_get_priv(dev);
803 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
804 struct mmc *mmc = upriv->mmc;
805 size_t len = blkcnt * mmc->read_bl_len;
806 size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
807
808 if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
809 if (priv->quirks & TMIO_SD_CAP_16BIT)
810 return U16_MAX;
811 else
812 return U32_MAX;
813 } else {
814 return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
815 }
816}
817
Marek Vasute94cad92018-04-08 15:22:58 +0200818static const struct dm_mmc_ops renesas_sdhi_ops = {
Marek Vasutb5900a52019-05-19 03:47:07 +0200819 .send_cmd = renesas_sdhi_send_cmd,
Marek Vasutf63968b2018-04-08 19:09:17 +0200820 .set_ios = renesas_sdhi_set_ios,
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200821 .get_cd = tmio_sd_get_cd,
Marek Vasut50aa1d92018-06-13 08:02:55 +0200822#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
823 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
824 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
Marek Vasutf63968b2018-04-08 19:09:17 +0200825 .execute_tuning = renesas_sdhi_execute_tuning,
826#endif
Marek Vasut2fc10752018-10-28 19:28:56 +0100827#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
828 .wait_dat0 = renesas_sdhi_wait_dat0,
829#endif
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200830 .get_b_max = renesas_sdhi_get_b_max,
Marek Vasute94cad92018-04-08 15:22:58 +0200831};
832
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200833#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
Marek Vasutf98833d2018-04-08 18:49:52 +0200834#define RENESAS_GEN3_QUIRKS \
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200835 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
Marek Vasutf98833d2018-04-08 18:49:52 +0200836
Marek Vasute94cad92018-04-08 15:22:58 +0200837static const struct udevice_id renesas_sdhi_match[] = {
Marek Vasutf98833d2018-04-08 18:49:52 +0200838 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
839 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
840 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
841 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
842 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
843 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
844 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
Adam Ford4ce95662020-06-30 09:30:10 -0500845 { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
Marek Vasutf98833d2018-04-08 18:49:52 +0200846 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
847 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
Marek Vasutd6291522018-04-26 13:19:29 +0200848 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
Marek Vasutf98833d2018-04-08 18:49:52 +0200849 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
Marek Vasute94cad92018-04-08 15:22:58 +0200850 { /* sentinel */ }
851};
852
Marek Vasut8ec6a042018-06-13 08:02:55 +0200853static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
854{
855 return clk_get_rate(&priv->clk);
856}
857
Marek Vasutd34bd2d2018-06-13 08:02:55 +0200858static void renesas_sdhi_filter_caps(struct udevice *dev)
859{
Marek Vasutd34bd2d2018-06-13 08:02:55 +0200860 struct tmio_sd_priv *priv = dev_get_priv(dev);
861
862 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
863 return;
864
Marek Vasut56b0bb92019-11-23 13:36:25 +0100865#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
866 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
867 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
Simon Glassc69cda22020-12-03 16:55:20 -0700868 struct tmio_sd_plat *plat = dev_get_plat(dev);
Marek Vasut56b0bb92019-11-23 13:36:25 +0100869
870 /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
Marek Vasutd34bd2d2018-06-13 08:02:55 +0200871 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
872 (rmobile_get_cpu_rev_integer() <= 1)) ||
873 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
874 (rmobile_get_cpu_rev_integer() == 1) &&
Marek Vasut56b0bb92019-11-23 13:36:25 +0100875 (rmobile_get_cpu_rev_fraction() < 2)))
Marek Vasutd34bd2d2018-06-13 08:02:55 +0200876 plat->cfg.host_caps &= ~MMC_MODE_HS400;
Marek Vasut50aa1d92018-06-13 08:02:55 +0200877
Marek Vasut1bdcb832019-11-23 13:36:24 +0100878 /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
879 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
880 (rmobile_get_cpu_rev_integer() >= 2)) ||
881 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
882 (rmobile_get_cpu_rev_integer() == 1) &&
883 (rmobile_get_cpu_rev_fraction() == 2)) ||
884 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
885 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
886
Marek Vasut56b0bb92019-11-23 13:36:25 +0100887 /* H3 ES3.0 can use HS400 with manual adjustment */
888 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
889 (rmobile_get_cpu_rev_integer() >= 3)) {
890 priv->adjust_hs400_enable = true;
891 priv->adjust_hs400_offset = 0;
892 priv->adjust_hs400_calib_table =
893 r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
894 }
895
896 /* M3W ES1.2 can use HS400 with manual adjustment */
897 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
898 (rmobile_get_cpu_rev_integer() == 1) &&
899 (rmobile_get_cpu_rev_fraction() == 2)) {
900 priv->adjust_hs400_enable = true;
901 priv->adjust_hs400_offset = 3;
902 priv->adjust_hs400_calib_table =
903 r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
904 }
905
Marek Vasut1bdcb832019-11-23 13:36:24 +0100906 /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
Marek Vasutb5900a52019-05-19 03:47:07 +0200907 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
908 (rmobile_get_cpu_rev_integer() == 1) &&
909 (rmobile_get_cpu_rev_fraction() > 2)) {
910 priv->adjust_hs400_enable = true;
Marek Vasut56b0bb92019-11-23 13:36:25 +0100911 priv->adjust_hs400_offset = 0;
Marek Vasut1bdcb832019-11-23 13:36:24 +0100912 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
Marek Vasut56b0bb92019-11-23 13:36:25 +0100913 priv->adjust_hs400_calib_table =
914 r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
Marek Vasutb5900a52019-05-19 03:47:07 +0200915 }
916
917 /* M3N can use HS400 with manual adjustment */
918 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
919 priv->adjust_hs400_enable = true;
Marek Vasute5d3f3d2019-11-23 13:36:21 +0100920 priv->adjust_hs400_offset = 3;
Marek Vasut56b0bb92019-11-23 13:36:25 +0100921 priv->adjust_hs400_calib_table =
922 r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
Marek Vasutb5900a52019-05-19 03:47:07 +0200923 }
924
925 /* E3 can use HS400 with manual adjustment */
926 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
927 priv->adjust_hs400_enable = true;
Marek Vasute5d3f3d2019-11-23 13:36:21 +0100928 priv->adjust_hs400_offset = 3;
Marek Vasut56b0bb92019-11-23 13:36:25 +0100929 priv->adjust_hs400_calib_table =
930 r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
Marek Vasutb5900a52019-05-19 03:47:07 +0200931 }
932
Marek Vasut81099882019-11-23 13:36:19 +0100933 /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
934 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
935 (rmobile_get_cpu_rev_integer() <= 2)) ||
936 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
937 (rmobile_get_cpu_rev_integer() == 1) &&
938 (rmobile_get_cpu_rev_fraction() <= 2)))
Marek Vasut50aa1d92018-06-13 08:02:55 +0200939 priv->nrtaps = 4;
940 else
941 priv->nrtaps = 8;
Marek Vasut56b0bb92019-11-23 13:36:25 +0100942#endif
Marek Vasut992bcf42019-01-11 23:45:54 +0100943 /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
944 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
945 (rmobile_get_cpu_rev_integer() <= 1)) ||
946 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
947 (rmobile_get_cpu_rev_integer() == 1) &&
948 (rmobile_get_cpu_rev_fraction() == 0)))
949 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
950 else
951 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
Marek Vasutd34bd2d2018-06-13 08:02:55 +0200952}
953
Marek Vasutc769e602018-04-08 17:45:23 +0200954static int renesas_sdhi_probe(struct udevice *dev)
955{
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900956 struct tmio_sd_priv *priv = dev_get_priv(dev);
Marek Vasutc769e602018-04-08 17:45:23 +0200957 u32 quirks = dev_get_driver_data(dev);
Marek Vasut7cf7ef82018-04-08 18:14:22 +0200958 struct fdt_resource reg_res;
959 DECLARE_GLOBAL_DATA_PTR;
960 int ret;
961
Marek Vasut8ec6a042018-06-13 08:02:55 +0200962 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
963
Marek Vasutf98833d2018-04-08 18:49:52 +0200964 if (quirks == RENESAS_GEN2_QUIRKS) {
965 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
966 "reg", 0, &reg_res);
967 if (ret < 0) {
968 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
969 ret);
970 return ret;
971 }
Marek Vasut7cf7ef82018-04-08 18:14:22 +0200972
Marek Vasutf98833d2018-04-08 18:49:52 +0200973 if (fdt_resource_size(&reg_res) == 0x100)
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200974 quirks |= TMIO_SD_CAP_16BIT;
Marek Vasutf98833d2018-04-08 18:49:52 +0200975 }
Marek Vasutc769e602018-04-08 17:45:23 +0200976
Marek Vasut8ec6a042018-06-13 08:02:55 +0200977 ret = clk_get_by_index(dev, 0, &priv->clk);
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900978 if (ret < 0) {
979 dev_err(dev, "failed to get host clock\n");
980 return ret;
981 }
982
983 /* set to max rate */
Marek Vasut8ec6a042018-06-13 08:02:55 +0200984 ret = clk_set_rate(&priv->clk, 200000000);
985 if (ret < 0) {
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900986 dev_err(dev, "failed to set rate for host clock\n");
Marek Vasut8ec6a042018-06-13 08:02:55 +0200987 clk_free(&priv->clk);
988 return ret;
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900989 }
990
Marek Vasut8ec6a042018-06-13 08:02:55 +0200991 ret = clk_enable(&priv->clk);
Masahiro Yamada30b5d9a2018-04-20 18:14:24 +0900992 if (ret) {
993 dev_err(dev, "failed to enable host clock\n");
994 return ret;
995 }
996
Marek Vasut4a66d4e2020-04-04 12:45:06 +0200997 priv->quirks = quirks;
Marek Vasutcb0b6b02018-04-13 23:51:33 +0200998 ret = tmio_sd_probe(dev, quirks);
Marek Vasutd34bd2d2018-06-13 08:02:55 +0200999
1000 renesas_sdhi_filter_caps(dev);
1001
Marek Vasut50aa1d92018-06-13 08:02:55 +02001002#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
1003 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1004 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
Marek Vasut52e17962018-10-28 15:30:06 +01001005 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
Marek Vasut65186972018-08-30 15:27:26 +02001006 renesas_sdhi_reset_tuning(priv);
Marek Vasutf63968b2018-04-08 19:09:17 +02001007#endif
1008 return ret;
Marek Vasutc769e602018-04-08 17:45:23 +02001009}
1010
Marek Vasute94cad92018-04-08 15:22:58 +02001011U_BOOT_DRIVER(renesas_sdhi) = {
1012 .name = "renesas-sdhi",
1013 .id = UCLASS_MMC,
1014 .of_match = renesas_sdhi_match,
Marek Vasutcb0b6b02018-04-13 23:51:33 +02001015 .bind = tmio_sd_bind,
Marek Vasutc769e602018-04-08 17:45:23 +02001016 .probe = renesas_sdhi_probe,
Simon Glass41575d82020-12-03 16:55:17 -07001017 .priv_auto = sizeof(struct tmio_sd_priv),
Simon Glasscaa4daa2020-12-03 16:55:18 -07001018 .plat_auto = sizeof(struct tmio_sd_plat),
Marek Vasute94cad92018-04-08 15:22:58 +02001019 .ops = &renesas_sdhi_ops,
1020};