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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkfe7eb5d2005-09-25 02:00:47 +020027 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk3d3befa2004-03-14 15:06:13 +000028 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#include <common.h>
Ben Warren10efa022008-08-31 20:37:00 -070037#include <netdev.h>
38
Wolfgang Denkd87080b2006-03-31 18:32:53 +020039DECLARE_GLOBAL_DATA_PTR;
40
wdenk3d3befa2004-03-14 15:06:13 +000041void peripheral_power_enable (void);
42
43#if defined(CONFIG_SHOW_BOOT_PROGRESS)
44void show_boot_progress(int progress)
45{
Wolfgang Denk716c1dc2005-09-25 18:49:35 +020046 printf("Boot reached stage %d\n", progress);
wdenk3d3befa2004-03-14 15:06:13 +000047}
48#endif
49
50#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
51
wdenk3d3befa2004-03-14 15:06:13 +000052/*
53 * Miscellaneous platform dependent initialisations
54 */
55
56int board_init (void)
57{
wdenk3d3befa2004-03-14 15:06:13 +000058 /* arch number of Integrator Board */
Jean-Christophe PLAGNIOL-VILLARD576afd42009-05-17 00:58:37 +020059#ifdef CONFIG_ARCH_CINTEGRATOR
60 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
61#else
wdenk731215e2004-10-10 18:41:04 +000062 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
Jean-Christophe PLAGNIOL-VILLARD576afd42009-05-17 00:58:37 +020063#endif
wdenk3d3befa2004-03-14 15:06:13 +000064
65 /* adress of boot parameters */
66 gd->bd->bi_boot_params = 0x00000100;
67
wdenkbc54f302004-07-11 18:10:30 +000068 gd->flags = 0;
69
Wolfgang Denk0148e8c2005-09-25 16:22:14 +020070#ifdef CONFIG_CM_REMAP
71extern void cm_remap(void);
72 cm_remap(); /* remaps writeable memory to 0x00000000 */
73#endif
Wolfgang Denk716c1dc2005-09-25 18:49:35 +020074
wdenk3d3befa2004-03-14 15:06:13 +000075 icache_enable ();
76
wdenk3d3befa2004-03-14 15:06:13 +000077 return 0;
78}
79
wdenk3d3befa2004-03-14 15:06:13 +000080int misc_init_r (void)
81{
82#ifdef CONFIG_PCI
83 pci_init();
84#endif
85 setenv("verify", "n");
86 return (0);
87}
88
wdenk3d3befa2004-03-14 15:06:13 +000089/******************************
90 Routine:
91 Description:
92******************************/
93int dram_init (void)
94{
Wolfgang Denk0148e8c2005-09-25 16:22:14 +020095 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Wolfgang Denk716c1dc2005-09-25 18:49:35 +020096 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
Wolfgang Denk0148e8c2005-09-25 16:22:14 +020097
98#ifdef CONFIG_CM_SPD_DETECT
99 {
100extern void dram_query(void);
101 unsigned long cm_reg_sdram;
102 unsigned long sdram_shift;
103
104 dram_query(); /* Assembler accesses to CM registers */
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200105 /* Queries the SPD values */
Wolfgang Denk0148e8c2005-09-25 16:22:14 +0200106
107 /* Obtain the SDRAM size from the CM SDRAM register */
108
109 cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200110 /* Register SDRAM size
Wolfgang Denk0148e8c2005-09-25 16:22:14 +0200111 *
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200112 * 0xXXXXXXbbb000bb 16 MB
113 * 0xXXXXXXbbb001bb 32 MB
114 * 0xXXXXXXbbb010bb 64 MB
115 * 0xXXXXXXbbb011bb 128 MB
116 * 0xXXXXXXbbb100bb 256 MB
117 *
Wolfgang Denk0148e8c2005-09-25 16:22:14 +0200118 */
Wolfgang Denk716c1dc2005-09-25 18:49:35 +0200119 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
120 gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
Wolfgang Denk0148e8c2005-09-25 16:22:14 +0200121
122 }
123#endif /* CM_SPD_DETECT */
124
wdenk3d3befa2004-03-14 15:06:13 +0000125 return 0;
126}
Wolfgang Denk74f43042005-09-25 01:48:28 +0200127
Ben Warren7194ab82009-10-04 22:37:03 -0700128#ifdef CONFIG_CMD_NET
Ben Warren10efa022008-08-31 20:37:00 -0700129int board_eth_init(bd_t *bis)
130{
Ben Warren7194ab82009-10-04 22:37:03 -0700131 int rc = 0;
132#ifdef CONFIG_SMC91111
133 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
134#endif
Ben Warren7194ab82009-10-04 22:37:03 -0700135 rc += pci_eth_init(bis);
Ben Warren7194ab82009-10-04 22:37:03 -0700136 return rc;
Ben Warren10efa022008-08-31 20:37:00 -0700137}
Jean-Christophe PLAGNIOL-VILLARD576afd42009-05-17 00:58:37 +0200138#endif