Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * board.c |
| 3 | * |
| 4 | * Common board functions for AM33XX based boards |
| 5 | * |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <common.h> |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 20 | #include <errno.h> |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 21 | #include <asm/arch/cpu.h> |
| 22 | #include <asm/arch/hardware.h> |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 23 | #include <asm/arch/omap.h> |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 24 | #include <asm/arch/ddr_defs.h> |
| 25 | #include <asm/arch/clock.h> |
Steve Sakoman | 3b97152 | 2012-06-04 05:35:34 +0000 | [diff] [blame] | 26 | #include <asm/arch/gpio.h> |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 27 | #include <asm/arch/mmc_host_def.h> |
Tom Rini | db7dd81 | 2012-07-31 10:50:01 -0700 | [diff] [blame^] | 28 | #include <asm/arch/sys_proto.h> |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 29 | #include <asm/io.h> |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 30 | #include <asm/omap_common.h> |
Tom Rini | fda35eb | 2012-07-03 08:51:34 -0700 | [diff] [blame] | 31 | #include <asm/emif.h> |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 32 | #include <asm/gpio.h> |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 33 | #include <i2c.h> |
| 34 | #include <miiphy.h> |
| 35 | #include <cpsw.h> |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 36 | |
| 37 | DECLARE_GLOBAL_DATA_PTR; |
| 38 | |
| 39 | struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
Chandan Nath | fb072a3 | 2012-01-09 20:38:56 +0000 | [diff] [blame] | 40 | struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 41 | struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; |
| 42 | |
Steve Sakoman | 3b97152 | 2012-06-04 05:35:34 +0000 | [diff] [blame] | 43 | static const struct gpio_bank gpio_bank_am33xx[4] = { |
| 44 | { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, |
| 45 | { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, |
| 46 | { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, |
| 47 | { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, |
| 48 | }; |
| 49 | |
| 50 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; |
| 51 | |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 52 | /* MII mode defines */ |
| 53 | #define MII_MODE_ENABLE 0x0 |
| 54 | #define RGMII_MODE_ENABLE 0xA |
| 55 | |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 56 | /* GPIO that controls power to DDR on EVM-SK */ |
| 57 | #define GPIO_DDR_VTT_EN 7 |
| 58 | |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 59 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
| 60 | |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 61 | static struct am335x_baseboard_id __attribute__((section (".data"))) header; |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 62 | |
| 63 | static inline int board_is_bone(void) |
| 64 | { |
Tom Rini | db7dd81 | 2012-07-31 10:50:01 -0700 | [diff] [blame^] | 65 | return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 66 | } |
| 67 | |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 68 | static inline int board_is_evm_sk(void) |
| 69 | { |
Tom Rini | db7dd81 | 2012-07-31 10:50:01 -0700 | [diff] [blame^] | 70 | return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 71 | } |
| 72 | |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 73 | /* |
| 74 | * Read header information from EEPROM into global structure. |
| 75 | */ |
| 76 | static int read_eeprom(void) |
| 77 | { |
| 78 | /* Check if baseboard eeprom is available */ |
Tom Rini | 726c05d | 2012-07-31 09:37:08 -0700 | [diff] [blame] | 79 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 80 | puts("Could not probe the EEPROM; something fundamentally " |
| 81 | "wrong on the I2C bus.\n"); |
| 82 | return -ENODEV; |
| 83 | } |
| 84 | |
| 85 | /* read the eeprom using i2c */ |
Tom Rini | 726c05d | 2012-07-31 09:37:08 -0700 | [diff] [blame] | 86 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 87 | sizeof(header))) { |
| 88 | puts("Could not read the EEPROM; something fundamentally" |
| 89 | " wrong on the I2C bus.\n"); |
| 90 | return -EIO; |
| 91 | } |
| 92 | |
| 93 | if (header.magic != 0xEE3355AA) { |
| 94 | /* |
| 95 | * read the eeprom using i2c again, |
| 96 | * but use only a 1 byte address |
| 97 | */ |
Tom Rini | 726c05d | 2012-07-31 09:37:08 -0700 | [diff] [blame] | 98 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, |
| 99 | (uchar *)&header, sizeof(header))) { |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 100 | puts("Could not read the EEPROM; something " |
| 101 | "fundamentally wrong on the I2C bus.\n"); |
| 102 | return -EIO; |
| 103 | } |
| 104 | |
| 105 | if (header.magic != 0xEE3355AA) { |
| 106 | printf("Incorrect magic number (0x%x) in EEPROM\n", |
| 107 | header.magic); |
| 108 | return -EINVAL; |
| 109 | } |
| 110 | } |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 115 | /* UART Defines */ |
| 116 | #ifdef CONFIG_SPL_BUILD |
| 117 | #define UART_RESET (0x1 << 1) |
| 118 | #define UART_CLK_RUNNING_MASK 0x1 |
| 119 | #define UART_SMART_IDLE_EN (0x1 << 0x3) |
| 120 | #endif |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 121 | |
Tom Rini | 2ab2810 | 2012-05-14 12:38:18 +0000 | [diff] [blame] | 122 | #ifdef CONFIG_SPL_BUILD |
| 123 | /* Initialize timer */ |
| 124 | static void init_timer(void) |
| 125 | { |
| 126 | /* Reset the Timer */ |
| 127 | writel(0x2, (&timer_base->tscir)); |
| 128 | |
| 129 | /* Wait until the reset is done */ |
| 130 | while (readl(&timer_base->tiocp_cfg) & 1) |
| 131 | ; |
| 132 | |
| 133 | /* Start the Timer */ |
| 134 | writel(0x1, (&timer_base->tclr)); |
| 135 | } |
| 136 | #endif |
| 137 | |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 138 | /* |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 139 | * Determine what type of DDR we have. |
| 140 | */ |
| 141 | static short inline board_memory_type(void) |
| 142 | { |
| 143 | /* The following boards are known to use DDR3. */ |
| 144 | if (board_is_evm_sk()) |
| 145 | return EMIF_REG_SDRAM_TYPE_DDR3; |
| 146 | |
| 147 | return EMIF_REG_SDRAM_TYPE_DDR2; |
| 148 | } |
| 149 | |
| 150 | /* |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 151 | * early system init of muxing and clocks. |
| 152 | */ |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 153 | void s_init(void) |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 154 | { |
| 155 | /* WDT1 is already running when the bootloader gets control |
| 156 | * Disable it to avoid "random" resets |
| 157 | */ |
| 158 | writel(0xAAAA, &wdtimer->wdtwspr); |
| 159 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 160 | ; |
| 161 | writel(0x5555, &wdtimer->wdtwspr); |
| 162 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 163 | ; |
| 164 | |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 165 | #ifdef CONFIG_SPL_BUILD |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 166 | /* Setup the PLLs and the clocks for the peripherals */ |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 167 | pll_init(); |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 168 | |
| 169 | /* UART softreset */ |
| 170 | u32 regVal; |
| 171 | |
| 172 | enable_uart0_pin_mux(); |
| 173 | |
| 174 | regVal = readl(&uart_base->uartsyscfg); |
| 175 | regVal |= UART_RESET; |
| 176 | writel(regVal, &uart_base->uartsyscfg); |
| 177 | while ((readl(&uart_base->uartsyssts) & |
| 178 | UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) |
| 179 | ; |
| 180 | |
| 181 | /* Disable smart idle */ |
| 182 | regVal = readl(&uart_base->uartsyscfg); |
| 183 | regVal |= UART_SMART_IDLE_EN; |
| 184 | writel(regVal, &uart_base->uartsyscfg); |
| 185 | |
| 186 | /* Initialize the Timer */ |
| 187 | init_timer(); |
| 188 | |
| 189 | preloader_console_init(); |
| 190 | |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 191 | /* Initalize the board header */ |
| 192 | enable_i2c0_pin_mux(); |
| 193 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 194 | if (read_eeprom() < 0) |
| 195 | puts("Could not get board ID.\n"); |
| 196 | |
Tom Rini | db7dd81 | 2012-07-31 10:50:01 -0700 | [diff] [blame^] | 197 | enable_board_pin_mux(&header); |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 198 | if (board_is_evm_sk()) { |
| 199 | /* |
| 200 | * EVM SK 1.2A and later use gpio0_7 to enable DDR3. |
| 201 | * This is safe enough to do on older revs. |
| 202 | */ |
Tom Rini | 65d750b | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 203 | gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
| 204 | gpio_direction_output(GPIO_DDR_VTT_EN, 1); |
| 205 | } |
| 206 | |
| 207 | config_ddr(board_memory_type()); |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 208 | #endif |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Chandan Nath | 876bdd6 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 211 | #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) |
| 212 | int board_mmc_init(bd_t *bis) |
| 213 | { |
Jonathan Solnit | bbbc1ae | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 214 | return omap_mmc_init(0, 0, 0); |
Chandan Nath | 876bdd6 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 215 | } |
| 216 | #endif |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 217 | |
| 218 | void setup_clocks_for_console(void) |
| 219 | { |
| 220 | /* Not yet implemented */ |
| 221 | return; |
| 222 | } |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 223 | |
| 224 | /* |
Tom Rini | db7dd81 | 2012-07-31 10:50:01 -0700 | [diff] [blame^] | 225 | * Basic board specific setup. Pinmux has been handled already. |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 226 | */ |
| 227 | int board_init(void) |
| 228 | { |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 229 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 230 | if (read_eeprom() < 0) |
| 231 | puts("Could not get board ID.\n"); |
| 232 | |
| 233 | gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; |
| 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 239 | static void cpsw_control(int enabled) |
| 240 | { |
| 241 | /* VTP can be added here */ |
| 242 | |
| 243 | return; |
| 244 | } |
| 245 | |
| 246 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 247 | { |
| 248 | .slave_reg_ofs = 0x208, |
| 249 | .sliver_reg_ofs = 0xd80, |
| 250 | .phy_id = 0, |
| 251 | }, |
| 252 | { |
| 253 | .slave_reg_ofs = 0x308, |
| 254 | .sliver_reg_ofs = 0xdc0, |
| 255 | .phy_id = 1, |
| 256 | }, |
| 257 | }; |
| 258 | |
| 259 | static struct cpsw_platform_data cpsw_data = { |
| 260 | .mdio_base = AM335X_CPSW_MDIO_BASE, |
| 261 | .cpsw_base = AM335X_CPSW_BASE, |
| 262 | .mdio_div = 0xff, |
| 263 | .channels = 8, |
| 264 | .cpdma_reg_ofs = 0x800, |
| 265 | .slaves = 1, |
| 266 | .slave_data = cpsw_slaves, |
| 267 | .ale_reg_ofs = 0xd00, |
| 268 | .ale_entries = 1024, |
| 269 | .host_port_reg_ofs = 0x108, |
| 270 | .hw_stats_reg_ofs = 0x900, |
| 271 | .mac_control = (1 << 5), |
| 272 | .control = cpsw_control, |
| 273 | .host_port_num = 0, |
| 274 | .version = CPSW_CTRL_VERSION_2, |
| 275 | }; |
| 276 | |
| 277 | int board_eth_init(bd_t *bis) |
| 278 | { |
| 279 | uint8_t mac_addr[6]; |
| 280 | uint32_t mac_hi, mac_lo; |
| 281 | |
| 282 | if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { |
| 283 | debug("<ethaddr> not set. Reading from E-fuse\n"); |
| 284 | /* try reading mac address from efuse */ |
| 285 | mac_lo = readl(&cdev->macid0l); |
| 286 | mac_hi = readl(&cdev->macid0h); |
| 287 | mac_addr[0] = mac_hi & 0xFF; |
| 288 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 289 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 290 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 291 | mac_addr[4] = mac_lo & 0xFF; |
| 292 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 293 | |
| 294 | if (is_valid_ether_addr(mac_addr)) |
| 295 | eth_setenv_enetaddr("ethaddr", mac_addr); |
| 296 | else |
| 297 | return -1; |
| 298 | } |
| 299 | |
| 300 | if (board_is_bone()) { |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 301 | writel(MII_MODE_ENABLE, &cdev->miisel); |
| 302 | cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
| 303 | PHY_INTERFACE_MODE_MII; |
| 304 | } else { |
Tom Rini | 973b663 | 2012-07-30 16:13:10 -0700 | [diff] [blame] | 305 | writel(RGMII_MODE_ENABLE, &cdev->miisel); |
| 306 | cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
| 307 | PHY_INTERFACE_MODE_RGMII; |
| 308 | } |
| 309 | |
| 310 | return cpsw_register(&cpsw_data); |
| 311 | } |
| 312 | #endif |