Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * board.c |
| 3 | * |
| 4 | * Common board functions for AM33XX based boards |
| 5 | * |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <common.h> |
| 20 | #include <asm/arch/cpu.h> |
| 21 | #include <asm/arch/hardware.h> |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 22 | #include <asm/arch/omap.h> |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 23 | #include <asm/arch/ddr_defs.h> |
| 24 | #include <asm/arch/clock.h> |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 25 | #include <asm/arch/mmc_host_def.h> |
| 26 | #include <asm/arch/common_def.h> |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 27 | #include <asm/io.h> |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 28 | #include <asm/omap_common.h> |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 29 | |
| 30 | DECLARE_GLOBAL_DATA_PTR; |
| 31 | |
| 32 | struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
Chandan Nath | fb072a3 | 2012-01-09 20:38:56 +0000 | [diff] [blame] | 33 | struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 34 | struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; |
| 35 | |
| 36 | /* UART Defines */ |
| 37 | #ifdef CONFIG_SPL_BUILD |
| 38 | #define UART_RESET (0x1 << 1) |
| 39 | #define UART_CLK_RUNNING_MASK 0x1 |
| 40 | #define UART_SMART_IDLE_EN (0x1 << 0x3) |
| 41 | #endif |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 42 | |
Tom Rini | 2ab2810 | 2012-05-14 12:38:18 +0000 | [diff] [blame^] | 43 | #ifdef CONFIG_SPL_BUILD |
| 44 | /* Initialize timer */ |
| 45 | static void init_timer(void) |
| 46 | { |
| 47 | /* Reset the Timer */ |
| 48 | writel(0x2, (&timer_base->tscir)); |
| 49 | |
| 50 | /* Wait until the reset is done */ |
| 51 | while (readl(&timer_base->tiocp_cfg) & 1) |
| 52 | ; |
| 53 | |
| 54 | /* Start the Timer */ |
| 55 | writel(0x1, (&timer_base->tclr)); |
| 56 | } |
| 57 | #endif |
| 58 | |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 59 | /* |
| 60 | * early system init of muxing and clocks. |
| 61 | */ |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 62 | void s_init(void) |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 63 | { |
| 64 | /* WDT1 is already running when the bootloader gets control |
| 65 | * Disable it to avoid "random" resets |
| 66 | */ |
| 67 | writel(0xAAAA, &wdtimer->wdtwspr); |
| 68 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 69 | ; |
| 70 | writel(0x5555, &wdtimer->wdtwspr); |
| 71 | while (readl(&wdtimer->wdtwwps) != 0x0) |
| 72 | ; |
| 73 | |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 74 | #ifdef CONFIG_SPL_BUILD |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 75 | /* Setup the PLLs and the clocks for the peripherals */ |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 76 | pll_init(); |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 77 | |
| 78 | /* UART softreset */ |
| 79 | u32 regVal; |
| 80 | |
| 81 | enable_uart0_pin_mux(); |
| 82 | |
| 83 | regVal = readl(&uart_base->uartsyscfg); |
| 84 | regVal |= UART_RESET; |
| 85 | writel(regVal, &uart_base->uartsyscfg); |
| 86 | while ((readl(&uart_base->uartsyssts) & |
| 87 | UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) |
| 88 | ; |
| 89 | |
| 90 | /* Disable smart idle */ |
| 91 | regVal = readl(&uart_base->uartsyscfg); |
| 92 | regVal |= UART_SMART_IDLE_EN; |
| 93 | writel(regVal, &uart_base->uartsyscfg); |
| 94 | |
| 95 | /* Initialize the Timer */ |
| 96 | init_timer(); |
| 97 | |
| 98 | preloader_console_init(); |
| 99 | |
| 100 | config_ddr(); |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 101 | #endif |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 102 | |
| 103 | /* Enable MMC0 */ |
| 104 | enable_mmc0_pin_mux(); |
Chandan Nath | 5289e83 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 105 | } |
| 106 | |
Chandan Nath | 876bdd6 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 107 | #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) |
| 108 | int board_mmc_init(bd_t *bis) |
| 109 | { |
Jonathan Solnit | bbbc1ae | 2012-02-24 11:30:18 +0000 | [diff] [blame] | 110 | return omap_mmc_init(0, 0, 0); |
Chandan Nath | 876bdd6 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 111 | } |
| 112 | #endif |
Chandan Nath | 8a8f084 | 2012-01-09 20:38:59 +0000 | [diff] [blame] | 113 | |
| 114 | void setup_clocks_for_console(void) |
| 115 | { |
| 116 | /* Not yet implemented */ |
| 117 | return; |
| 118 | } |