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Dinh Nguyen3da42852015-06-02 22:52:49 -05001/*
2 * Copyright Altera Corporation (C) 2012-2015
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/sdram.h>
Marek Vasut04372fb2015-07-18 02:46:56 +020010#include <errno.h>
Dinh Nguyen3da42852015-06-02 22:52:49 -050011#include "sequencer.h"
12#include "sequencer_auto.h"
13#include "sequencer_auto_ac_init.h"
14#include "sequencer_auto_inst_init.h"
15#include "sequencer_defines.h"
16
Dinh Nguyen3da42852015-06-02 22:52:49 -050017static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
Marek Vasut6afb4fe2015-07-12 18:46:52 +020018 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
Dinh Nguyen3da42852015-06-02 22:52:49 -050019
20static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
Marek Vasut6afb4fe2015-07-12 18:46:52 +020021 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
Dinh Nguyen3da42852015-06-02 22:52:49 -050022
23static struct socfpga_sdr_reg_file *sdr_reg_file =
Marek Vasuta1c654a2015-07-12 18:31:05 +020024 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050025
26static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
Marek Vasute79025a2015-07-12 18:42:34 +020027 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
Dinh Nguyen3da42852015-06-02 22:52:49 -050028
29static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
Marek Vasut1bc6f142015-07-12 18:54:37 +020030 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050031
32static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
Marek Vasut1bc6f142015-07-12 18:54:37 +020033 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
Dinh Nguyen3da42852015-06-02 22:52:49 -050034
35static struct socfpga_data_mgr *data_mgr =
Marek Vasutc4815f72015-07-12 19:03:33 +020036 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -050037
Marek Vasut6cb9f162015-07-12 20:49:39 +020038static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
40
Dinh Nguyen3da42852015-06-02 22:52:49 -050041#define DELTA_D 1
Dinh Nguyen3da42852015-06-02 22:52:49 -050042
43/*
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
47 *
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
53 */
54
55#define DLEVEL 0
56#define STATIC_IN_RTL_SIM 0
57#define STATIC_SKIP_DELAY_LOOPS 0
58
59#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
61
62/* calibration steps requested by the rtl */
63uint16_t dyn_calib_steps;
64
65/*
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
69 *
70 * The mask is set to include all bits when not-skipping, but is
71 * zero when skipping
72 */
73
74uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
75
76#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
78
79struct gbl_type *gbl;
80struct param_type *param;
81uint32_t curr_shadow_reg;
82
83static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
86
Dinh Nguyen3da42852015-06-02 22:52:49 -050087static void set_failing_group_stage(uint32_t group, uint32_t stage,
88 uint32_t substage)
89{
90 /*
91 * Only set the global stage if there was not been any other
92 * failing group
93 */
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
98 }
99}
100
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200101static void reg_file_set_group(u16 set_group)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500102{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500104}
105
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200106static void reg_file_set_stage(u8 set_stage)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500107{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500109}
110
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200111static void reg_file_set_sub_stage(u8 set_sub_stage)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500112{
Marek Vasut2c0d2d92015-07-12 21:10:24 +0200113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500115}
116
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200117/**
118 * phy_mgr_initialize() - Initialize PHY Manager
119 *
120 * Initialize PHY Manager.
121 */
Marek Vasut9fa9c902015-07-17 01:12:07 +0200122static void phy_mgr_initialize(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500123{
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200124 u32 ratio;
125
Dinh Nguyen3da42852015-06-02 22:52:49 -0500126 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200127 /* Calibration has control over path to memory */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500128 /*
129 * In Hard PHY this is a 2-bit control:
130 * 0: AFI Mux Select
131 * 1: DDIO Mux Select
132 */
Marek Vasut1273dd92015-07-12 21:05:08 +0200133 writel(0x3, &phy_mgr_cfg->mux_sel);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500134
135 /* USER memory clock is not stable we begin initialization */
Marek Vasut1273dd92015-07-12 21:05:08 +0200136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500137
138 /* USER calibration status all set to zero */
Marek Vasut1273dd92015-07-12 21:05:08 +0200139 writel(0, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500140
Marek Vasut1273dd92015-07-12 21:05:08 +0200141 writel(0, &phy_mgr_cfg->cal_debug_info);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500142
Marek Vasut7c89c2d2015-07-17 01:36:32 +0200143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
145 return;
146
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500156}
157
Marek Vasut080bf642015-07-20 08:15:57 +0200158/**
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
160 * @rank: Rank mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
162 *
163 * Set Rank and ODT mask (On-Die Termination).
164 */
Marek Vasutb2dfd102015-07-20 08:03:11 +0200165static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500166{
Marek Vasutb2dfd102015-07-20 08:03:11 +0200167 u32 odt_mask_0 = 0;
168 u32 odt_mask_1 = 0;
169 u32 cs_and_odt_mask;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500170
Marek Vasutb2dfd102015-07-20 08:03:11 +0200171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
172 odt_mask_0 = 0x0;
173 odt_mask_1 = 0x0;
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
Marek Vasut287cdf62015-07-20 08:09:05 +0200175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
176 case 1: /* 1 Rank */
177 /* Read: ODT = 0 ; Write: ODT = 1 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500178 odt_mask_0 = 0x0;
179 odt_mask_1 = 0x1;
Marek Vasut287cdf62015-07-20 08:09:05 +0200180 break;
181 case 2: /* 2 Ranks */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
Marek Vasut080bf642015-07-20 08:15:57 +0200183 /*
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
185 * OR
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
187 *
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
191 *
Dinh Nguyen3da42852015-06-02 22:52:49 -0500192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
194 */
195 odt_mask_0 = 0x3 & ~(1 << rank);
196 odt_mask_1 = 0x3;
197 } else {
198 /*
Marek Vasut080bf642015-07-20 08:15:57 +0200199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
200 *
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
Dinh Nguyen3da42852015-06-02 22:52:49 -0500203 */
204 odt_mask_0 = 0x0;
205 odt_mask_1 = 0x3 & (1 << rank);
206 }
Marek Vasut287cdf62015-07-20 08:09:05 +0200207 break;
208 case 4: /* 4 Ranks */
209 /* Read:
Dinh Nguyen3da42852015-06-02 22:52:49 -0500210 * ----------+-----------------------+
Dinh Nguyen3da42852015-06-02 22:52:49 -0500211 * | ODT |
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
220 *
221 * Write:
222 * ----------+-----------------------+
Dinh Nguyen3da42852015-06-02 22:52:49 -0500223 * | ODT |
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
232 */
233 switch (rank) {
234 case 0:
235 odt_mask_0 = 0x4;
236 odt_mask_1 = 0x5;
237 break;
238 case 1:
239 odt_mask_0 = 0x8;
240 odt_mask_1 = 0xA;
241 break;
242 case 2:
243 odt_mask_0 = 0x1;
244 odt_mask_1 = 0x5;
245 break;
246 case 3:
247 odt_mask_0 = 0x2;
248 odt_mask_1 = 0xA;
249 break;
250 }
Marek Vasut287cdf62015-07-20 08:09:05 +0200251 break;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500252 }
Dinh Nguyen3da42852015-06-02 22:52:49 -0500253 }
254
Marek Vasutb2dfd102015-07-20 08:03:11 +0200255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
Marek Vasut1273dd92015-07-12 21:05:08 +0200258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500260}
261
Marek Vasutc76976d2015-07-12 22:28:33 +0200262/**
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
267 *
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
269 */
270static void scc_mgr_set(u32 off, u32 grp, u32 val)
271{
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
273}
274
Marek Vasute893f4d2015-07-20 07:16:42 +0200275/**
276 * scc_mgr_initialize() - Initialize SCC Manager registers
277 *
278 * Initialize SCC Manager registers.
279 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500280static void scc_mgr_initialize(void)
281{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500282 /*
Marek Vasute893f4d2015-07-20 07:16:42 +0200283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500287 */
Marek Vasutc76976d2015-07-12 22:28:33 +0200288 int i;
Marek Vasute893f4d2015-07-20 07:16:42 +0200289
Dinh Nguyen3da42852015-06-02 22:52:49 -0500290 for (i = 0; i < 16; i++) {
Marek Vasut7ac40d22015-06-26 18:56:54 +0200291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -0500292 __func__, __LINE__, i);
Marek Vasutc76976d2015-07-12 22:28:33 +0200293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500294 }
295}
296
Marek Vasut5ff825b2015-07-12 22:11:55 +0200297static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
298{
Marek Vasutc76976d2015-07-12 22:28:33 +0200299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200300}
301
302static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500303{
Marek Vasutc76976d2015-07-12 22:28:33 +0200304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500305}
306
Dinh Nguyen3da42852015-06-02 22:52:49 -0500307static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
308{
Marek Vasutc76976d2015-07-12 22:28:33 +0200309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500310}
311
Marek Vasut5ff825b2015-07-12 22:11:55 +0200312static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
313{
Marek Vasutc76976d2015-07-12 22:28:33 +0200314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200315}
316
Marek Vasut32675242015-07-17 06:07:13 +0200317static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200318{
Marek Vasutc76976d2015-07-12 22:28:33 +0200319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
320 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200321}
322
323static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
324{
Marek Vasutc76976d2015-07-12 22:28:33 +0200325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200326}
327
328static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
329{
Marek Vasutc76976d2015-07-12 22:28:33 +0200330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200331}
332
Marek Vasut32675242015-07-17 06:07:13 +0200333static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200334{
Marek Vasutc76976d2015-07-12 22:28:33 +0200335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
336 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200337}
338
339static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
340{
Marek Vasutc76976d2015-07-12 22:28:33 +0200341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
343 delay);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200344}
345
346/* load up dqs config settings */
347static void scc_mgr_load_dqs(uint32_t dqs)
348{
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
350}
351
352/* load up dqs io config settings */
353static void scc_mgr_load_dqs_io(void)
354{
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
356}
357
358/* load up dq config settings */
359static void scc_mgr_load_dq(uint32_t dq_in_group)
360{
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
362}
363
364/* load up dm config settings */
365static void scc_mgr_load_dm(uint32_t dm)
366{
367 writel(dm, &sdr_scc_mgr->dm_ena);
368}
369
Marek Vasut0b69b802015-07-12 23:25:21 +0200370/**
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
376 *
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
379 */
380static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
381 const int update)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500382{
Marek Vasut0b69b802015-07-12 23:25:21 +0200383 u32 r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500384
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
Marek Vasut0b69b802015-07-12 23:25:21 +0200387 scc_mgr_set(off, grp, val);
Marek Vasut162d60e2015-07-12 23:14:33 +0200388
Marek Vasut0b69b802015-07-12 23:25:21 +0200389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
Marek Vasut1273dd92015-07-12 21:05:08 +0200391 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500392 }
393 }
394}
395
Marek Vasut0b69b802015-07-12 23:25:21 +0200396static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
397{
398 /*
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
404 * once to sr0.
405 */
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
408}
409
Dinh Nguyen3da42852015-06-02 22:52:49 -0500410static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
411 uint32_t phase)
412{
Marek Vasut0b69b802015-07-12 23:25:21 +0200413 /*
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
419 * once to sr0.
420 */
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500423}
424
Dinh Nguyen3da42852015-06-02 22:52:49 -0500425static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
426 uint32_t delay)
427{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500428 /*
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
434 * set to 0.
435 */
Marek Vasut0b69b802015-07-12 23:25:21 +0200436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
Marek Vasut1273dd92015-07-12 21:05:08 +0200438 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500439}
440
Marek Vasut5be355c2015-07-12 23:39:06 +0200441/**
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
445 *
446 * This function sets the OCT output delay in SCC manager.
447 */
448static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500449{
Marek Vasut5be355c2015-07-12 23:39:06 +0200450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
453 int i;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500454 /*
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
460 */
Marek Vasut5be355c2015-07-12 23:39:06 +0200461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500463}
464
Marek Vasut37a37ca2015-07-19 01:32:55 +0200465/**
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
467 *
468 * Load the fixed setting in the SCC manager HHP extras.
469 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500470static void scc_mgr_set_hhp_extras(void)
471{
472 /*
473 * Load the fixed setting in the SCC manager
Marek Vasut37a37ca2015-07-19 01:32:55 +0200474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
Dinh Nguyen3da42852015-06-02 22:52:49 -0500480 */
Marek Vasut37a37ca2015-07-19 01:32:55 +0200481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500486
Marek Vasut37a37ca2015-07-19 01:32:55 +0200487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
488 __func__, __LINE__);
489 writel(value, addr);
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
491 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500492}
493
Marek Vasutf42af352015-07-20 04:41:53 +0200494/**
495 * scc_mgr_zero_all() - Zero all DQS config
496 *
497 * Zero all DQS config.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500498 */
499static void scc_mgr_zero_all(void)
500{
Marek Vasutf42af352015-07-20 04:41:53 +0200501 int i, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500502
503 /*
504 * USER Zero all DQS config settings, across all groups and all
505 * shadow registers
506 */
Marek Vasutf42af352015-07-20 04:41:53 +0200507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
Dinh Nguyen3da42852015-06-02 22:52:49 -0500509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
510 /*
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
514 */
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
518 }
519
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
Marek Vasutf42af352015-07-20 04:41:53 +0200522 /* Arria V/Cyclone V don't have out2. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
524 }
525 }
526
Marek Vasutf42af352015-07-20 04:41:53 +0200527 /* Multicast to all DQS group enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500530}
531
Marek Vasutc5c5f532015-07-17 02:06:20 +0200532/**
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
535 *
536 * Set bypass mode and trigger SCC update.
537 */
538static void scc_set_bypass_mode(const u32 write_group)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500539{
Marek Vasutc5c5f532015-07-17 02:06:20 +0200540 /* Multicast to all DQ enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500543
Marek Vasutc5c5f532015-07-17 02:06:20 +0200544 /* Update current DQS IO enable. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200545 writel(0, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500546
Marek Vasutc5c5f532015-07-17 02:06:20 +0200547 /* Update the DQS logic. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200548 writel(write_group, &sdr_scc_mgr->dqs_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500549
Marek Vasutc5c5f532015-07-17 02:06:20 +0200550 /* Hit update. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200551 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500552}
553
Marek Vasut5e837892015-07-13 00:30:09 +0200554/**
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
557 *
558 * Load DQS settings for Write Group, do not trigger SCC update.
559 */
560static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
Marek Vasut5ff825b2015-07-12 22:11:55 +0200561{
Marek Vasut5e837892015-07-13 00:30:09 +0200562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
565 int i;
Marek Vasut5ff825b2015-07-12 22:11:55 +0200566 /*
Marek Vasut5e837892015-07-13 00:30:09 +0200567 * Load the setting in the SCC manager
Marek Vasut5ff825b2015-07-12 22:11:55 +0200568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
Marek Vasut5e837892015-07-13 00:30:09 +0200571 * the setting must be set multiple times.
Marek Vasut5ff825b2015-07-12 22:11:55 +0200572 */
Marek Vasut5e837892015-07-13 00:30:09 +0200573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
Marek Vasut5ff825b2015-07-12 22:11:55 +0200575}
576
Marek Vasutd41ea932015-07-20 08:41:04 +0200577/**
578 * scc_mgr_zero_group() - Zero all configs for a group
579 *
580 * Zero DQ, DM, DQS and OCT configs for a group.
581 */
582static void scc_mgr_zero_group(const u32 write_group, const int out_only)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500583{
Marek Vasutd41ea932015-07-20 08:41:04 +0200584 int i, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500585
Marek Vasutd41ea932015-07-20 08:41:04 +0200586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200590 scc_mgr_set_dq_out1_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500591 if (!out_only)
Marek Vasut07aee5b2015-07-12 22:07:33 +0200592 scc_mgr_set_dq_in_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500593 }
594
Marek Vasutd41ea932015-07-20 08:41:04 +0200595 /* Multicast to all DQ enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200596 writel(0xff, &sdr_scc_mgr->dq_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500597
Marek Vasutd41ea932015-07-20 08:41:04 +0200598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
Marek Vasut07aee5b2015-07-12 22:07:33 +0200600 scc_mgr_set_dm_out1_delay(i, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500601
Marek Vasutd41ea932015-07-20 08:41:04 +0200602 /* Multicast to all DM enables. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200603 writel(0xff, &sdr_scc_mgr->dm_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500604
Marek Vasutd41ea932015-07-20 08:41:04 +0200605 /* Zero all DQS IO settings. */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500606 if (!out_only)
Marek Vasut32675242015-07-17 06:07:13 +0200607 scc_mgr_set_dqs_io_in_delay(0);
Marek Vasutd41ea932015-07-20 08:41:04 +0200608
609 /* Arria V/Cyclone V don't have out2. */
Marek Vasut32675242015-07-17 06:07:13 +0200610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
613
Marek Vasutd41ea932015-07-20 08:41:04 +0200614 /* Multicast to all DQS IO enables (only 1 in total). */
Marek Vasut1273dd92015-07-12 21:05:08 +0200615 writel(0, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500616
Marek Vasutd41ea932015-07-20 08:41:04 +0200617 /* Hit update to zero everything. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200618 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500619 }
620}
621
Dinh Nguyen3da42852015-06-02 22:52:49 -0500622/*
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
625 */
Marek Vasut32675242015-07-17 06:07:13 +0200626static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500627{
628 uint32_t i, p;
629
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200631 scc_mgr_set_dq_in_delay(p, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500632 scc_mgr_load_dq(p);
633 }
634}
635
Marek Vasut300c2e62015-07-17 05:42:49 +0200636/**
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
639 *
640 * Apply and load a particular output delay for the DQ pins in a group.
641 */
642static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500643{
Marek Vasut300c2e62015-07-17 05:42:49 +0200644 int i;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500645
Marek Vasut300c2e62015-07-17 05:42:49 +0200646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500648 scc_mgr_load_dq(i);
649 }
650}
651
652/* apply and load a particular output delay for the DM pins in a group */
Marek Vasut32675242015-07-17 06:07:13 +0200653static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500654{
655 uint32_t i;
656
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
Marek Vasut07aee5b2015-07-12 22:07:33 +0200658 scc_mgr_set_dm_out1_delay(i, delay1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500659 scc_mgr_load_dm(i);
660 }
661}
662
663
664/* apply and load delay on both DQS and OCT out1 */
665static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
666 uint32_t delay)
667{
Marek Vasut32675242015-07-17 06:07:13 +0200668 scc_mgr_set_dqs_out1_delay(delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500669 scc_mgr_load_dqs_io();
670
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
673}
674
Marek Vasut5cb1b502015-07-17 05:33:28 +0200675/**
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
679 *
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
681 */
Marek Vasut8eccde32015-07-17 05:30:14 +0200682static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
Marek Vasut8eccde32015-07-17 05:30:14 +0200683 const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500684{
Marek Vasut8eccde32015-07-17 05:30:14 +0200685 u32 i, new_delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500686
Marek Vasut8eccde32015-07-17 05:30:14 +0200687 /* DQ shift */
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500689 scc_mgr_load_dq(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500690
Marek Vasut8eccde32015-07-17 05:30:14 +0200691 /* DM shift */
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500693 scc_mgr_load_dm(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500694
Marek Vasut5cb1b502015-07-17 05:33:28 +0200695 /* DQS shift */
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
Dinh Nguyen3da42852015-06-02 22:52:49 -0500702 new_delay - IO_IO_OUT2_DELAY_MAX);
Marek Vasut5cb1b502015-07-17 05:33:28 +0200703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500705 }
706
707 scc_mgr_load_dqs_io();
708
Marek Vasut5cb1b502015-07-17 05:33:28 +0200709 /* OCT shift */
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
Dinh Nguyen3da42852015-06-02 22:52:49 -0500716 new_delay - IO_IO_OUT2_DELAY_MAX);
Marek Vasut5cb1b502015-07-17 05:33:28 +0200717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500719 }
720
721 scc_mgr_load_dqs_for_write_group(write_group);
722}
723
Marek Vasutf51a7d32015-07-19 02:18:21 +0200724/**
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
728 *
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500730 */
Marek Vasutf51a7d32015-07-19 02:18:21 +0200731static void
732scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
733 const u32 delay)
Dinh Nguyen3da42852015-06-02 22:52:49 -0500734{
Marek Vasutf51a7d32015-07-19 02:18:21 +0200735 int r;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500736
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
Marek Vasutf51a7d32015-07-19 02:18:21 +0200738 r += NUM_RANKS_PER_SHADOW_REG) {
Marek Vasut5cb1b502015-07-17 05:33:28 +0200739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
Marek Vasut1273dd92015-07-12 21:05:08 +0200740 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500741 }
742}
743
Marek Vasutf936f942015-07-26 11:07:19 +0200744/**
745 * set_jump_as_return() - Return instruction optimization
746 *
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
749 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500750static void set_jump_as_return(void)
751{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500752 /*
Marek Vasutf936f942015-07-26 11:07:19 +0200753 * To save space, we replace return with jump to special shared
Dinh Nguyen3da42852015-06-02 22:52:49 -0500754 * RETURN instruction so we set the counter to large value so that
Marek Vasutf936f942015-07-26 11:07:19 +0200755 * we always jump.
Dinh Nguyen3da42852015-06-02 22:52:49 -0500756 */
Marek Vasut1273dd92015-07-12 21:05:08 +0200757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500759}
760
761/*
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
764 */
765static void delay_for_n_mem_clocks(const uint32_t clocks)
766{
767 uint32_t afi_clocks;
768 uint8_t inner = 0;
769 uint8_t outer = 0;
770 uint16_t c_loop = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -0500771
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
773
774
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
777
778 /*
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
784 */
785 if (afi_clocks == 0) {
786 ;
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
789 outer = 0;
790 c_loop = 0;
791 } else if (afi_clocks <= 0x10000) {
792 inner = 0xff;
793 outer = (afi_clocks-1) >> 8;
794 c_loop = 0;
795 } else {
796 inner = 0xff;
797 outer = 0xff;
798 c_loop = (afi_clocks-1) >> 16;
799 }
800
801 /*
802 * rom instructions are structured as follows:
803 *
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
806 * return
807 *
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
810 *
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
813 *
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
816 * overhead
817 */
818 if (afi_clocks <= 0x100) {
Marek Vasut1273dd92015-07-12 21:05:08 +0200819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500821
Marek Vasut1273dd92015-07-12 21:05:08 +0200822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500824
Marek Vasut1273dd92015-07-12 21:05:08 +0200825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500827 } else {
Marek Vasut1273dd92015-07-12 21:05:08 +0200828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500830
Marek Vasut1273dd92015-07-12 21:05:08 +0200831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500833
Marek Vasut1273dd92015-07-12 21:05:08 +0200834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500836
Marek Vasut1273dd92015-07-12 21:05:08 +0200837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500839
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
Marek Vasut1273dd92015-07-12 21:05:08 +0200843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500845 } else {
846 do {
Marek Vasut1273dd92015-07-12 21:05:08 +0200847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500850 } while (c_loop-- != 0);
851 }
852 }
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
854}
855
Marek Vasut944fe712015-07-13 00:44:30 +0200856/**
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
862 *
863 * Load instruction registers.
864 */
865static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
866{
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
869
870 /* Load counters */
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
877
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
882
883 /* Execute count instruction */
884 writel(jump, grpaddr);
885}
886
Marek Vasutecd23342015-07-13 00:51:05 +0200887/**
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
892 *
893 * Load user calibration values and optionally precharge the banks.
894 */
895static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
896 const int precharge)
897{
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
900 u32 r;
901
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
905 continue;
906 }
907
908 /* set rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
910
911 /* precharge all banks ... */
912 if (precharge)
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
914
915 /*
916 * USER Use Mirror-ed commands for odd ranks if address
917 * mirrorring is on
918 */
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
931 } else {
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
942 }
943
944 if (precharge)
945 continue;
946
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
949
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
952 }
953}
954
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200955/**
956 * rw_mgr_mem_initialize() - Initialize RW Manager
957 *
958 * Initialize RW Manager.
959 */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500960static void rw_mgr_mem_initialize(void)
961{
Dinh Nguyen3da42852015-06-02 22:52:49 -0500962 debug("%s:%d\n", __func__, __LINE__);
963
964 /* The reset / cke part of initialization is broadcasted to all ranks */
Marek Vasut1273dd92015-07-12 21:05:08 +0200965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500967
968 /*
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
975 * significant bits
976 */
977
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200978 /* Start with memory RESET activated */
Dinh Nguyen3da42852015-06-02 22:52:49 -0500979
980 /* tINIT = 200us */
981
982 /*
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
989 * b = 6A
990 */
Marek Vasut944fe712015-07-13 00:44:30 +0200991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
992 SEQ_TINIT_CNTR2_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500994
Marek Vasut8e9d7d02015-07-26 10:57:06 +0200995 /* Indicate that memory is stable. */
Marek Vasut1273dd92015-07-12 21:05:08 +0200996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
Dinh Nguyen3da42852015-06-02 22:52:49 -0500997
998 /*
999 * transition the RESET to high
1000 * Wait for 500us
1001 */
1002
1003 /*
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010 * b = FF
1011 */
Marek Vasut944fe712015-07-13 00:44:30 +02001012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001015
Marek Vasut8e9d7d02015-07-26 10:57:06 +02001016 /* Bring up clock enable. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001017
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1020
Marek Vasutecd23342015-07-13 00:51:05 +02001021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001023}
1024
1025/*
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1028 */
1029static void rw_mgr_mem_handoff(void)
1030{
Marek Vasutecd23342015-07-13 00:51:05 +02001031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032 /*
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1036 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001037}
1038
Marek Vasutd844c7d2015-07-18 03:55:07 +02001039/**
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1044 *
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
Dinh Nguyen3da42852015-06-02 22:52:49 -05001047 */
Marek Vasutd844c7d2015-07-18 03:55:07 +02001048static int
1049rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001051{
Marek Vasutd844c7d2015-07-18 03:55:07 +02001052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001062
Marek Vasutd844c7d2015-07-18 03:55:07 +02001063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064 int vg, r;
1065 int ret = 0;
1066
1067 bit_chk = param->read_correct_mask;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001068
1069 for (r = rank_bgn; r < rank_end; r++) {
Marek Vasutd844c7d2015-07-18 03:55:07 +02001070 /* Request to skip the rank */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001071 if (param->skip_ranks[r])
Dinh Nguyen3da42852015-06-02 22:52:49 -05001072 continue;
1073
Marek Vasutd844c7d2015-07-18 03:55:07 +02001074 /* Set rank */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077 /* Load up a constant bursts of read commands */
Marek Vasut1273dd92015-07-12 21:05:08 +02001078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001081
Marek Vasut1273dd92015-07-12 21:05:08 +02001082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001085
1086 tmp_bit_chk = 0;
Marek Vasutd844c7d2015-07-18 03:55:07 +02001087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088 vg >= 0; vg--) {
1089 /* Reset the FIFOs to get pointers to known state. */
Marek Vasut1273dd92015-07-12 21:05:08 +02001090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Marek Vasutd844c7d2015-07-18 03:55:07 +02001093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001095
Marek Vasut1273dd92015-07-12 21:05:08 +02001096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
Marek Vasutd844c7d2015-07-18 03:55:07 +02001097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001099 }
Marek Vasutd844c7d2015-07-18 03:55:07 +02001100
1101 bit_chk &= tmp_bit_chk;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001102 }
1103
Marek Vasut17fdc912015-07-12 20:05:54 +02001104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001105
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
Marek Vasutd844c7d2015-07-18 03:55:07 +02001107
1108 if (bit_chk != param->read_correct_mask)
1109 ret = -EIO;
1110
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1115
1116 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001117}
1118
Marek Vasutb6cb7f92015-07-18 03:34:22 +02001119/**
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1123 *
1124 * Load up the patterns we are going to use during a read test.
1125 */
1126static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001128{
Marek Vasutb6cb7f92015-07-18 03:34:22 +02001129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132 u32 r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001133
1134 debug("%s:%d\n", __func__, __LINE__);
Marek Vasutb6cb7f92015-07-18 03:34:22 +02001135
Dinh Nguyen3da42852015-06-02 22:52:49 -05001136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1139 continue;
1140
1141 /* set rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144 /* Load up a constant bursts */
Marek Vasut1273dd92015-07-12 21:05:08 +02001145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001146
Marek Vasut1273dd92015-07-12 21:05:08 +02001147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001149
Marek Vasut1273dd92015-07-12 21:05:08 +02001150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001151
Marek Vasut1273dd92015-07-12 21:05:08 +02001152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001154
Marek Vasut1273dd92015-07-12 21:05:08 +02001155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001156
Marek Vasut1273dd92015-07-12 21:05:08 +02001157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001159
Marek Vasut1273dd92015-07-12 21:05:08 +02001160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001161
Marek Vasut1273dd92015-07-12 21:05:08 +02001162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001164
Marek Vasut1273dd92015-07-12 21:05:08 +02001165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001167 }
1168
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170}
1171
Marek Vasut783fcf52015-07-20 03:26:05 +02001172/**
1173 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1174 * @rank_bgn: Rank number
1175 * @group: Read/Write group
1176 * @num_tries: Number of retries of the test
1177 * @all_correct: All bits must be correct in the mask
1178 * @bit_chk: Resulting bit mask after the test
1179 * @all_groups: Test all R/W groups
1180 * @all_ranks: Test all ranks
1181 *
1182 * Try a read and see if it returns correct data back. Test has dummy reads
1183 * inserted into the mix used to align DQS enable. Test has more thorough
1184 * checks than the regular read test.
Dinh Nguyen3da42852015-06-02 22:52:49 -05001185 */
Marek Vasut3cb8bf32015-07-19 07:48:58 +02001186static int
1187rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1188 const u32 num_tries, const u32 all_correct,
1189 u32 *bit_chk,
1190 const u32 all_groups, const u32 all_ranks)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001191{
Marek Vasut3cb8bf32015-07-19 07:48:58 +02001192 const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
Dinh Nguyen3da42852015-06-02 22:52:49 -05001193 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
Marek Vasut3cb8bf32015-07-19 07:48:58 +02001194 const u32 quick_read_mode =
1195 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1196 ENABLE_SUPER_QUICK_CALIBRATION);
1197 u32 correct_mask_vg = param->read_correct_mask_vg;
1198 u32 tmp_bit_chk;
1199 u32 base_rw_mgr;
1200 u32 addr;
1201
1202 int r, vg, ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001203
1204 *bit_chk = param->read_correct_mask;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001205
1206 for (r = rank_bgn; r < rank_end; r++) {
1207 if (param->skip_ranks[r])
1208 /* request to skip the rank */
1209 continue;
1210
1211 /* set rank */
1212 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1213
Marek Vasut1273dd92015-07-12 21:05:08 +02001214 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001215
Marek Vasut1273dd92015-07-12 21:05:08 +02001216 writel(RW_MGR_READ_B2B_WAIT1,
1217 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001218
Marek Vasut1273dd92015-07-12 21:05:08 +02001219 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1220 writel(RW_MGR_READ_B2B_WAIT2,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001222
Dinh Nguyen3da42852015-06-02 22:52:49 -05001223 if (quick_read_mode)
Marek Vasut1273dd92015-07-12 21:05:08 +02001224 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001225 /* need at least two (1+1) reads to capture failures */
1226 else if (all_groups)
Marek Vasut1273dd92015-07-12 21:05:08 +02001227 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001228 else
Marek Vasut1273dd92015-07-12 21:05:08 +02001229 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001230
Marek Vasut1273dd92015-07-12 21:05:08 +02001231 writel(RW_MGR_READ_B2B,
1232 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001233 if (all_groups)
1234 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1235 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
Marek Vasut1273dd92015-07-12 21:05:08 +02001236 &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001237 else
Marek Vasut1273dd92015-07-12 21:05:08 +02001238 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001239
Marek Vasut1273dd92015-07-12 21:05:08 +02001240 writel(RW_MGR_READ_B2B,
1241 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001242
1243 tmp_bit_chk = 0;
Marek Vasut7ce23bb2015-07-19 07:51:17 +02001244 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1245 vg--) {
Marek Vasutba522c72015-07-19 07:57:28 +02001246 /* Reset the FIFOs to get pointers to known state. */
Marek Vasut1273dd92015-07-12 21:05:08 +02001247 writel(0, &phy_mgr_cmd->fifo_reset);
1248 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1249 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001250
Marek Vasutba522c72015-07-19 07:57:28 +02001251 if (all_groups) {
1252 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1253 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1254 } else {
1255 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1256 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1257 }
Marek Vasutc4815f72015-07-12 19:03:33 +02001258
Marek Vasut17fdc912015-07-12 20:05:54 +02001259 writel(RW_MGR_READ_B2B, addr +
Dinh Nguyen3da42852015-06-02 22:52:49 -05001260 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1261 vg) << 2));
1262
Marek Vasut1273dd92015-07-12 21:05:08 +02001263 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
Marek Vasutba522c72015-07-19 07:57:28 +02001264 tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1265 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1266 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001267 }
Marek Vasut7ce23bb2015-07-19 07:51:17 +02001268
Dinh Nguyen3da42852015-06-02 22:52:49 -05001269 *bit_chk &= tmp_bit_chk;
1270 }
1271
Marek Vasutc4815f72015-07-12 19:03:33 +02001272 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02001273 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001274
Marek Vasut3853d652015-07-19 07:44:21 +02001275 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1276
Dinh Nguyen3da42852015-06-02 22:52:49 -05001277 if (all_correct) {
Marek Vasut3853d652015-07-19 07:44:21 +02001278 ret = (*bit_chk == param->read_correct_mask);
1279 debug_cond(DLEVEL == 2,
1280 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1281 __func__, __LINE__, group, all_groups, *bit_chk,
1282 param->read_correct_mask, ret);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001283 } else {
Marek Vasut3853d652015-07-19 07:44:21 +02001284 ret = (*bit_chk != 0x00);
1285 debug_cond(DLEVEL == 2,
1286 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1287 __func__, __LINE__, group, all_groups, *bit_chk,
1288 0, ret);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001289 }
Marek Vasut3853d652015-07-19 07:44:21 +02001290
1291 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001292}
1293
Marek Vasut96df6032015-07-19 07:35:36 +02001294/**
1295 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1296 * @grp: Read/Write group
1297 * @num_tries: Number of retries of the test
1298 * @all_correct: All bits must be correct in the mask
1299 * @all_groups: Test all R/W groups
1300 *
1301 * Perform a READ test across all memory ranks.
1302 */
1303static int
1304rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1305 const u32 all_correct,
1306 const u32 all_groups)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001307{
Marek Vasut96df6032015-07-19 07:35:36 +02001308 u32 bit_chk;
1309 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1310 &bit_chk, all_groups, 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001311}
1312
Marek Vasut60bb8a82015-07-19 06:25:27 +02001313/**
1314 * rw_mgr_incr_vfifo() - Increase VFIFO value
1315 * @grp: Read/Write group
Marek Vasut60bb8a82015-07-19 06:25:27 +02001316 *
1317 * Increase VFIFO value.
1318 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001319static void rw_mgr_incr_vfifo(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001320{
Marek Vasut1273dd92015-07-12 21:05:08 +02001321 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001322}
1323
Marek Vasut60bb8a82015-07-19 06:25:27 +02001324/**
1325 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1326 * @grp: Read/Write group
Marek Vasut60bb8a82015-07-19 06:25:27 +02001327 *
1328 * Decrease VFIFO value.
1329 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001330static void rw_mgr_decr_vfifo(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001331{
Marek Vasut60bb8a82015-07-19 06:25:27 +02001332 u32 i;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001333
Marek Vasut60bb8a82015-07-19 06:25:27 +02001334 for (i = 0; i < VFIFO_SIZE - 1; i++)
Marek Vasut8c887b62015-07-19 06:37:51 +02001335 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001336}
1337
Marek Vasutd145ca92015-07-19 06:45:43 +02001338/**
1339 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1340 * @grp: Read/Write group
1341 *
1342 * Push VFIFO until a failing read happens.
1343 */
1344static int find_vfifo_failing_read(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001345{
Marek Vasut96df6032015-07-19 07:35:36 +02001346 u32 v, ret, fail_cnt = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001347
Marek Vasut8c887b62015-07-19 06:37:51 +02001348 for (v = 0; v < VFIFO_SIZE; v++) {
Marek Vasutd145ca92015-07-19 06:45:43 +02001349 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -05001350 __func__, __LINE__, v);
Marek Vasutd145ca92015-07-19 06:45:43 +02001351 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Marek Vasut96df6032015-07-19 07:35:36 +02001352 PASS_ONE_BIT, 0);
Marek Vasutd145ca92015-07-19 06:45:43 +02001353 if (!ret) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05001354 fail_cnt++;
1355
1356 if (fail_cnt == 2)
Marek Vasutd145ca92015-07-19 06:45:43 +02001357 return v;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001358 }
1359
Marek Vasutd145ca92015-07-19 06:45:43 +02001360 /* Fiddle with FIFO. */
Marek Vasut8c887b62015-07-19 06:37:51 +02001361 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001362 }
1363
Marek Vasutd145ca92015-07-19 06:45:43 +02001364 /* No failing read found! Something must have gone wrong. */
1365 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1366 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001367}
1368
Marek Vasut192d6f92015-07-19 05:26:49 +02001369/**
Marek Vasut52e8f212015-07-19 07:27:06 +02001370 * sdr_find_phase_delay() - Find DQS enable phase or delay
1371 * @working: If 1, look for working phase/delay, if 0, look for non-working
1372 * @delay: If 1, look for delay, if 0, look for phase
1373 * @grp: Read/Write group
1374 * @work: Working window position
1375 * @work_inc: Working window increment
1376 * @pd: DQS Phase/Delay Iterator
1377 *
1378 * Find working or non-working DQS enable phase setting.
1379 */
1380static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1381 u32 *work, const u32 work_inc, u32 *pd)
1382{
1383 const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
Marek Vasut96df6032015-07-19 07:35:36 +02001384 u32 ret;
Marek Vasut52e8f212015-07-19 07:27:06 +02001385
1386 for (; *pd <= max; (*pd)++) {
1387 if (delay)
1388 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1389 else
1390 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1391
1392 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Marek Vasut96df6032015-07-19 07:35:36 +02001393 PASS_ONE_BIT, 0);
Marek Vasut52e8f212015-07-19 07:27:06 +02001394 if (!working)
1395 ret = !ret;
1396
1397 if (ret)
1398 return 0;
1399
1400 if (work)
1401 *work += work_inc;
1402 }
1403
1404 return -EINVAL;
1405}
1406/**
Marek Vasut192d6f92015-07-19 05:26:49 +02001407 * sdr_find_phase() - Find DQS enable phase
1408 * @working: If 1, look for working phase, if 0, look for non-working phase
1409 * @grp: Read/Write group
Marek Vasut192d6f92015-07-19 05:26:49 +02001410 * @work: Working window position
1411 * @i: Iterator
1412 * @p: DQS Phase Iterator
Marek Vasut192d6f92015-07-19 05:26:49 +02001413 *
1414 * Find working or non-working DQS enable phase setting.
1415 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001416static int sdr_find_phase(int working, const u32 grp, u32 *work,
Marek Vasut86a39dc2015-07-19 05:35:40 +02001417 u32 *i, u32 *p)
Marek Vasut192d6f92015-07-19 05:26:49 +02001418{
Marek Vasut192d6f92015-07-19 05:26:49 +02001419 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
Marek Vasut52e8f212015-07-19 07:27:06 +02001420 int ret;
Marek Vasut192d6f92015-07-19 05:26:49 +02001421
1422 for (; *i < end; (*i)++) {
1423 if (working)
1424 *p = 0;
1425
Marek Vasut52e8f212015-07-19 07:27:06 +02001426 ret = sdr_find_phase_delay(working, 0, grp, work,
1427 IO_DELAY_PER_OPA_TAP, p);
1428 if (!ret)
1429 return 0;
Marek Vasut192d6f92015-07-19 05:26:49 +02001430
1431 if (*p > IO_DQS_EN_PHASE_MAX) {
1432 /* Fiddle with FIFO. */
Marek Vasut8c887b62015-07-19 06:37:51 +02001433 rw_mgr_incr_vfifo(grp);
Marek Vasut192d6f92015-07-19 05:26:49 +02001434 if (!working)
1435 *p = 0;
1436 }
1437 }
1438
1439 return -EINVAL;
1440}
1441
Marek Vasut4c5e5842015-07-19 06:04:00 +02001442/**
1443 * sdr_working_phase() - Find working DQS enable phase
1444 * @grp: Read/Write group
1445 * @work_bgn: Working window start position
Marek Vasut4c5e5842015-07-19 06:04:00 +02001446 * @d: dtaps output value
1447 * @p: DQS Phase Iterator
1448 * @i: Iterator
1449 *
1450 * Find working DQS enable phase setting.
1451 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001452static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
Marek Vasut4c5e5842015-07-19 06:04:00 +02001453 u32 *p, u32 *i)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001454{
Marek Vasut35ee8672015-07-19 05:40:06 +02001455 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1456 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Marek Vasut192d6f92015-07-19 05:26:49 +02001457 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001458
Marek Vasut192d6f92015-07-19 05:26:49 +02001459 *work_bgn = 0;
1460
1461 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1462 *i = 0;
Marek Vasut521fe392015-07-19 04:34:12 +02001463 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
Marek Vasut8c887b62015-07-19 06:37:51 +02001464 ret = sdr_find_phase(1, grp, work_bgn, i, p);
Marek Vasut192d6f92015-07-19 05:26:49 +02001465 if (!ret)
1466 return 0;
1467 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001468 }
1469
Marek Vasut38ed6922015-07-19 05:01:12 +02001470 /* Cannot find working solution */
Marek Vasut192d6f92015-07-19 05:26:49 +02001471 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1472 __func__, __LINE__);
1473 return -EINVAL;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001474}
1475
Marek Vasut4c5e5842015-07-19 06:04:00 +02001476/**
1477 * sdr_backup_phase() - Find DQS enable backup phase
1478 * @grp: Read/Write group
1479 * @work_bgn: Working window start position
Marek Vasut4c5e5842015-07-19 06:04:00 +02001480 * @p: DQS Phase Iterator
1481 *
1482 * Find DQS enable backup phase setting.
1483 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001484static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001485{
Marek Vasut96df6032015-07-19 07:35:36 +02001486 u32 tmp_delay, d;
Marek Vasut4c5e5842015-07-19 06:04:00 +02001487 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001488
1489 /* Special case code for backing up a phase */
1490 if (*p == 0) {
1491 *p = IO_DQS_EN_PHASE_MAX;
Marek Vasut8c887b62015-07-19 06:37:51 +02001492 rw_mgr_decr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001493 } else {
1494 (*p)--;
1495 }
1496 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
Marek Vasut521fe392015-07-19 04:34:12 +02001497 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001498
Marek Vasut49891df62015-07-19 05:48:30 +02001499 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1500 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001501
Marek Vasut4c5e5842015-07-19 06:04:00 +02001502 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Marek Vasut96df6032015-07-19 07:35:36 +02001503 PASS_ONE_BIT, 0);
Marek Vasut4c5e5842015-07-19 06:04:00 +02001504 if (ret) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05001505 *work_bgn = tmp_delay;
1506 break;
1507 }
Marek Vasut49891df62015-07-19 05:48:30 +02001508
1509 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001510 }
1511
Marek Vasut4c5e5842015-07-19 06:04:00 +02001512 /* Restore VFIFO to old state before we decremented it (if needed). */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001513 (*p)++;
1514 if (*p > IO_DQS_EN_PHASE_MAX) {
1515 *p = 0;
Marek Vasut8c887b62015-07-19 06:37:51 +02001516 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001517 }
1518
Marek Vasut521fe392015-07-19 04:34:12 +02001519 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001520}
1521
Marek Vasut4c5e5842015-07-19 06:04:00 +02001522/**
1523 * sdr_nonworking_phase() - Find non-working DQS enable phase
1524 * @grp: Read/Write group
1525 * @work_end: Working window end position
Marek Vasut4c5e5842015-07-19 06:04:00 +02001526 * @p: DQS Phase Iterator
1527 * @i: Iterator
1528 *
1529 * Find non-working DQS enable phase setting.
1530 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001531static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001532{
Marek Vasut192d6f92015-07-19 05:26:49 +02001533 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001534
1535 (*p)++;
1536 *work_end += IO_DELAY_PER_OPA_TAP;
1537 if (*p > IO_DQS_EN_PHASE_MAX) {
Marek Vasut192d6f92015-07-19 05:26:49 +02001538 /* Fiddle with FIFO. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001539 *p = 0;
Marek Vasut8c887b62015-07-19 06:37:51 +02001540 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001541 }
1542
Marek Vasut8c887b62015-07-19 06:37:51 +02001543 ret = sdr_find_phase(0, grp, work_end, i, p);
Marek Vasut192d6f92015-07-19 05:26:49 +02001544 if (ret) {
1545 /* Cannot see edge of failing read. */
1546 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1547 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001548 }
1549
Marek Vasut192d6f92015-07-19 05:26:49 +02001550 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001551}
1552
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001553/**
1554 * sdr_find_window_center() - Find center of the working DQS window.
1555 * @grp: Read/Write group
1556 * @work_bgn: First working settings
1557 * @work_end: Last working settings
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001558 *
1559 * Find center of the working DQS enable window.
1560 */
1561static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
Marek Vasut8c887b62015-07-19 06:37:51 +02001562 const u32 work_end)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001563{
Marek Vasut96df6032015-07-19 07:35:36 +02001564 u32 work_mid;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001565 int tmp_delay = 0;
Marek Vasut28fd2422015-07-19 02:56:59 +02001566 int i, p, d;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001567
Marek Vasut28fd2422015-07-19 02:56:59 +02001568 work_mid = (work_bgn + work_end) / 2;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001569
1570 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
Marek Vasut28fd2422015-07-19 02:56:59 +02001571 work_bgn, work_end, work_mid);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001572 /* Get the middle delay to be less than a VFIFO delay */
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001573 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
Marek Vasut28fd2422015-07-19 02:56:59 +02001574
Dinh Nguyen3da42852015-06-02 22:52:49 -05001575 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001576 work_mid %= tmp_delay;
Marek Vasut28fd2422015-07-19 02:56:59 +02001577 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001578
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001579 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1580 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1581 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1582 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001583
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001584 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1585
1586 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1587 if (d > IO_DQS_EN_DELAY_MAX)
1588 d = IO_DQS_EN_DELAY_MAX;
1589 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1590
Marek Vasut28fd2422015-07-19 02:56:59 +02001591 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1592
Marek Vasutcbb0b7e2015-07-19 04:04:33 +02001593 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
Marek Vasut28fd2422015-07-19 02:56:59 +02001594 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001595
1596 /*
1597 * push vfifo until we can successfully calibrate. We can do this
1598 * because the largest possible margin in 1 VFIFO cycle.
1599 */
1600 for (i = 0; i < VFIFO_SIZE; i++) {
Marek Vasut8c887b62015-07-19 06:37:51 +02001601 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
Marek Vasut28fd2422015-07-19 02:56:59 +02001602 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
Dinh Nguyen3da42852015-06-02 22:52:49 -05001603 PASS_ONE_BIT,
Marek Vasut96df6032015-07-19 07:35:36 +02001604 0)) {
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001605 debug_cond(DLEVEL == 2,
Marek Vasut8c887b62015-07-19 06:37:51 +02001606 "%s:%d center: found: ptap=%u dtap=%u\n",
1607 __func__, __LINE__, p, d);
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001608 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001609 }
1610
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001611 /* Fiddle with FIFO. */
Marek Vasut8c887b62015-07-19 06:37:51 +02001612 rw_mgr_incr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001613 }
1614
Marek Vasut0a13a0f2015-07-19 04:14:32 +02001615 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1616 __func__, __LINE__);
1617 return -EINVAL;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001618}
1619
Marek Vasut33756892015-07-20 09:11:09 +02001620/**
1621 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1622 * @grp: Read/Write Group
1623 *
1624 * Find a good DQS enable to use.
1625 */
Marek Vasut914546e2015-07-20 09:20:42 +02001626static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001627{
Marek Vasut57355402015-07-20 09:20:20 +02001628 u32 d, p, i;
1629 u32 dtaps_per_ptap;
1630 u32 work_bgn, work_end;
1631 u32 found_passing_read, found_failing_read, initial_failing_dtap;
1632 int ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001633
1634 debug("%s:%d %u\n", __func__, __LINE__, grp);
1635
1636 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1637
1638 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1639 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1640
Marek Vasut2f3589c2015-07-19 02:42:21 +02001641 /* Step 0: Determine number of delay taps for each phase tap. */
1642 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001643
Marek Vasut2f3589c2015-07-19 02:42:21 +02001644 /* Step 1: First push vfifo until we get a failing read. */
Marek Vasutd145ca92015-07-19 06:45:43 +02001645 find_vfifo_failing_read(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001646
Marek Vasut2f3589c2015-07-19 02:42:21 +02001647 /* Step 2: Find first working phase, increment in ptaps. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001648 work_bgn = 0;
Marek Vasut914546e2015-07-20 09:20:42 +02001649 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1650 if (ret)
1651 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001652
1653 work_end = work_bgn;
1654
1655 /*
Marek Vasut2f3589c2015-07-19 02:42:21 +02001656 * If d is 0 then the working window covers a phase tap and we can
1657 * follow the old procedure. Otherwise, we've found the beginning
Dinh Nguyen3da42852015-06-02 22:52:49 -05001658 * and we need to increment the dtaps until we find the end.
1659 */
1660 if (d == 0) {
Marek Vasut2f3589c2015-07-19 02:42:21 +02001661 /*
1662 * Step 3a: If we have room, back off by one and
1663 * increment in dtaps.
1664 */
Marek Vasut8c887b62015-07-19 06:37:51 +02001665 sdr_backup_phase(grp, &work_bgn, &p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001666
Marek Vasut2f3589c2015-07-19 02:42:21 +02001667 /*
1668 * Step 4a: go forward from working phase to non working
1669 * phase, increment in ptaps.
1670 */
Marek Vasut914546e2015-07-20 09:20:42 +02001671 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1672 if (ret)
1673 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001674
Marek Vasut2f3589c2015-07-19 02:42:21 +02001675 /* Step 5a: Back off one from last, increment in dtaps. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05001676
1677 /* Special case code for backing up a phase */
1678 if (p == 0) {
1679 p = IO_DQS_EN_PHASE_MAX;
Marek Vasut8c887b62015-07-19 06:37:51 +02001680 rw_mgr_decr_vfifo(grp);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001681 } else {
1682 p = p - 1;
1683 }
1684
1685 work_end -= IO_DELAY_PER_OPA_TAP;
1686 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1687
Dinh Nguyen3da42852015-06-02 22:52:49 -05001688 d = 0;
1689
Marek Vasut2f3589c2015-07-19 02:42:21 +02001690 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1691 __func__, __LINE__, p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001692 }
1693
Marek Vasut2f3589c2015-07-19 02:42:21 +02001694 /* The dtap increment to find the failing edge is done here. */
Marek Vasut52e8f212015-07-19 07:27:06 +02001695 sdr_find_phase_delay(0, 1, grp, &work_end,
1696 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001697
1698 /* Go back to working dtap */
1699 if (d != 0)
1700 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1701
Marek Vasut2f3589c2015-07-19 02:42:21 +02001702 debug_cond(DLEVEL == 2,
1703 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1704 __func__, __LINE__, p, d - 1, work_end);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001705
1706 if (work_end < work_bgn) {
1707 /* nil range */
Marek Vasut2f3589c2015-07-19 02:42:21 +02001708 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1709 __func__, __LINE__);
Marek Vasut914546e2015-07-20 09:20:42 +02001710 return -EINVAL;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001711 }
1712
Marek Vasut2f3589c2015-07-19 02:42:21 +02001713 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -05001714 __func__, __LINE__, work_bgn, work_end);
1715
Dinh Nguyen3da42852015-06-02 22:52:49 -05001716 /*
Marek Vasut2f3589c2015-07-19 02:42:21 +02001717 * We need to calculate the number of dtaps that equal a ptap.
1718 * To do that we'll back up a ptap and re-find the edge of the
1719 * window using dtaps
Dinh Nguyen3da42852015-06-02 22:52:49 -05001720 */
Marek Vasut2f3589c2015-07-19 02:42:21 +02001721 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1722 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001723
1724 /* Special case code for backing up a phase */
1725 if (p == 0) {
1726 p = IO_DQS_EN_PHASE_MAX;
Marek Vasut8c887b62015-07-19 06:37:51 +02001727 rw_mgr_decr_vfifo(grp);
Marek Vasut2f3589c2015-07-19 02:42:21 +02001728 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1729 __func__, __LINE__, p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001730 } else {
1731 p = p - 1;
Marek Vasut2f3589c2015-07-19 02:42:21 +02001732 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1733 __func__, __LINE__, p);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001734 }
1735
1736 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1737
1738 /*
1739 * Increase dtap until we first see a passing read (in case the
Marek Vasut2f3589c2015-07-19 02:42:21 +02001740 * window is smaller than a ptap), and then a failing read to
1741 * mark the edge of the window again.
Dinh Nguyen3da42852015-06-02 22:52:49 -05001742 */
1743
Marek Vasut2f3589c2015-07-19 02:42:21 +02001744 /* Find a passing read. */
1745 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
Dinh Nguyen3da42852015-06-02 22:52:49 -05001746 __func__, __LINE__);
Marek Vasut52e8f212015-07-19 07:27:06 +02001747
Dinh Nguyen3da42852015-06-02 22:52:49 -05001748 initial_failing_dtap = d;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001749
Marek Vasut52e8f212015-07-19 07:27:06 +02001750 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001751 if (found_passing_read) {
Marek Vasut2f3589c2015-07-19 02:42:21 +02001752 /* Find a failing read. */
1753 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1754 __func__, __LINE__);
Marek Vasut52e8f212015-07-19 07:27:06 +02001755 d++;
1756 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1757 &d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001758 } else {
Marek Vasut2f3589c2015-07-19 02:42:21 +02001759 debug_cond(DLEVEL == 1,
1760 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1761 __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001762 }
1763
1764 /*
1765 * The dynamically calculated dtaps_per_ptap is only valid if we
1766 * found a passing/failing read. If we didn't, it means d hit the max
1767 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1768 * statically calculated value.
1769 */
1770 if (found_passing_read && found_failing_read)
1771 dtaps_per_ptap = d - initial_failing_dtap;
1772
Marek Vasut1273dd92015-07-12 21:05:08 +02001773 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
Marek Vasut2f3589c2015-07-19 02:42:21 +02001774 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1775 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001776
Marek Vasut2f3589c2015-07-19 02:42:21 +02001777 /* Step 6: Find the centre of the window. */
Marek Vasut914546e2015-07-20 09:20:42 +02001778 ret = sdr_find_window_center(grp, work_bgn, work_end);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001779
Marek Vasut914546e2015-07-20 09:20:42 +02001780 return ret;
Dinh Nguyen3da42852015-06-02 22:52:49 -05001781}
1782
Dinh Nguyen3da42852015-06-02 22:52:49 -05001783/* per-bit deskew DQ and center */
1784static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1785 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1786 uint32_t use_read_test, uint32_t update_fom)
1787{
1788 uint32_t i, p, d, min_index;
1789 /*
1790 * Store these as signed since there are comparisons with
1791 * signed numbers.
1792 */
1793 uint32_t bit_chk;
1794 uint32_t sticky_bit_chk;
1795 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1796 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1797 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1798 int32_t mid;
1799 int32_t orig_mid_min, mid_min;
1800 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1801 final_dqs_en;
1802 int32_t dq_margin, dqs_margin;
1803 uint32_t stop;
1804 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1805 uint32_t addr;
1806
1807 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1808
Marek Vasutc4815f72015-07-12 19:03:33 +02001809 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02001810 start_dqs = readl(addr + (read_group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05001811 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
Marek Vasut17fdc912015-07-12 20:05:54 +02001812 start_dqs_en = readl(addr + ((read_group << 2)
Dinh Nguyen3da42852015-06-02 22:52:49 -05001813 - IO_DQS_EN_DELAY_OFFSET));
1814
1815 /* set the left and right edge of each bit to an illegal value */
1816 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1817 sticky_bit_chk = 0;
1818 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1819 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1820 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1821 }
1822
Dinh Nguyen3da42852015-06-02 22:52:49 -05001823 /* Search for the left edge of the window for each bit */
1824 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1825 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1826
Marek Vasut1273dd92015-07-12 21:05:08 +02001827 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001828
1829 /*
1830 * Stop searching when the read test doesn't pass AND when
1831 * we've seen a passing read on every bit.
1832 */
1833 if (use_read_test) {
1834 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1835 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1836 &bit_chk, 0, 0);
1837 } else {
1838 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1839 0, PASS_ONE_BIT,
1840 &bit_chk, 0);
1841 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1842 (read_group - (write_group *
1843 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1844 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1845 stop = (bit_chk == 0);
1846 }
1847 sticky_bit_chk = sticky_bit_chk | bit_chk;
1848 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1849 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1850 && %u", __func__, __LINE__, d,
1851 sticky_bit_chk,
1852 param->read_correct_mask, stop);
1853
1854 if (stop == 1) {
1855 break;
1856 } else {
1857 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1858 if (bit_chk & 1) {
1859 /* Remember a passing test as the
1860 left_edge */
1861 left_edge[i] = d;
1862 } else {
1863 /* If a left edge has not been seen yet,
1864 then a future passing test will mark
1865 this edge as the right edge */
1866 if (left_edge[i] ==
1867 IO_IO_IN_DELAY_MAX + 1) {
1868 right_edge[i] = -(d + 1);
1869 }
1870 }
1871 bit_chk = bit_chk >> 1;
1872 }
1873 }
1874 }
1875
1876 /* Reset DQ delay chains to 0 */
Marek Vasut32675242015-07-17 06:07:13 +02001877 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001878 sticky_bit_chk = 0;
1879 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1880 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1881 %d right_edge[%u]: %d\n", __func__, __LINE__,
1882 i, left_edge[i], i, right_edge[i]);
1883
1884 /*
1885 * Check for cases where we haven't found the left edge,
1886 * which makes our assignment of the the right edge invalid.
1887 * Reset it to the illegal value.
1888 */
1889 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1890 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1891 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1892 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1893 right_edge[%u]: %d\n", __func__, __LINE__,
1894 i, right_edge[i]);
1895 }
1896
1897 /*
1898 * Reset sticky bit (except for bits where we have seen
1899 * both the left and right edge).
1900 */
1901 sticky_bit_chk = sticky_bit_chk << 1;
1902 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1903 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1904 sticky_bit_chk = sticky_bit_chk | 1;
1905 }
1906
1907 if (i == 0)
1908 break;
1909 }
1910
Dinh Nguyen3da42852015-06-02 22:52:49 -05001911 /* Search for the right edge of the window for each bit */
1912 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1913 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1914 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1915 uint32_t delay = d + start_dqs_en;
1916 if (delay > IO_DQS_EN_DELAY_MAX)
1917 delay = IO_DQS_EN_DELAY_MAX;
1918 scc_mgr_set_dqs_en_delay(read_group, delay);
1919 }
1920 scc_mgr_load_dqs(read_group);
1921
Marek Vasut1273dd92015-07-12 21:05:08 +02001922 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05001923
1924 /*
1925 * Stop searching when the read test doesn't pass AND when
1926 * we've seen a passing read on every bit.
1927 */
1928 if (use_read_test) {
1929 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1930 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1931 &bit_chk, 0, 0);
1932 } else {
1933 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1934 0, PASS_ONE_BIT,
1935 &bit_chk, 0);
1936 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1937 (read_group - (write_group *
1938 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1939 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1940 stop = (bit_chk == 0);
1941 }
1942 sticky_bit_chk = sticky_bit_chk | bit_chk;
1943 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1944
1945 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1946 %u && %u", __func__, __LINE__, d,
1947 sticky_bit_chk, param->read_correct_mask, stop);
1948
1949 if (stop == 1) {
1950 break;
1951 } else {
1952 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1953 if (bit_chk & 1) {
1954 /* Remember a passing test as
1955 the right_edge */
1956 right_edge[i] = d;
1957 } else {
1958 if (d != 0) {
1959 /* If a right edge has not been
1960 seen yet, then a future passing
1961 test will mark this edge as the
1962 left edge */
1963 if (right_edge[i] ==
1964 IO_IO_IN_DELAY_MAX + 1) {
1965 left_edge[i] = -(d + 1);
1966 }
1967 } else {
1968 /* d = 0 failed, but it passed
1969 when testing the left edge,
1970 so it must be marginal,
1971 set it to -1 */
1972 if (right_edge[i] ==
1973 IO_IO_IN_DELAY_MAX + 1 &&
1974 left_edge[i] !=
1975 IO_IO_IN_DELAY_MAX
1976 + 1) {
1977 right_edge[i] = -1;
1978 }
1979 /* If a right edge has not been
1980 seen yet, then a future passing
1981 test will mark this edge as the
1982 left edge */
1983 else if (right_edge[i] ==
1984 IO_IO_IN_DELAY_MAX +
1985 1) {
1986 left_edge[i] = -(d + 1);
1987 }
1988 }
1989 }
1990
1991 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1992 d=%u]: ", __func__, __LINE__, d);
1993 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1994 (int)(bit_chk & 1), i, left_edge[i]);
1995 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1996 right_edge[i]);
1997 bit_chk = bit_chk >> 1;
1998 }
1999 }
2000 }
2001
2002 /* Check that all bits have a window */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002003 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2004 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2005 %d right_edge[%u]: %d", __func__, __LINE__,
2006 i, left_edge[i], i, right_edge[i]);
2007 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2008 == IO_IO_IN_DELAY_MAX + 1)) {
2009 /*
2010 * Restore delay chain settings before letting the loop
2011 * in rw_mgr_mem_calibrate_vfifo to retry different
2012 * dqs/ck relationships.
2013 */
2014 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2015 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2016 scc_mgr_set_dqs_en_delay(read_group,
2017 start_dqs_en);
2018 }
2019 scc_mgr_load_dqs(read_group);
Marek Vasut1273dd92015-07-12 21:05:08 +02002020 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002021
2022 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2023 find edge [%u]: %d %d", __func__, __LINE__,
2024 i, left_edge[i], right_edge[i]);
2025 if (use_read_test) {
2026 set_failing_group_stage(read_group *
2027 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2028 CAL_STAGE_VFIFO,
2029 CAL_SUBSTAGE_VFIFO_CENTER);
2030 } else {
2031 set_failing_group_stage(read_group *
2032 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2033 CAL_STAGE_VFIFO_AFTER_WRITES,
2034 CAL_SUBSTAGE_VFIFO_CENTER);
2035 }
2036 return 0;
2037 }
2038 }
2039
2040 /* Find middle of window for each DQ bit */
2041 mid_min = left_edge[0] - right_edge[0];
2042 min_index = 0;
2043 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2044 mid = left_edge[i] - right_edge[i];
2045 if (mid < mid_min) {
2046 mid_min = mid;
2047 min_index = i;
2048 }
2049 }
2050
2051 /*
2052 * -mid_min/2 represents the amount that we need to move DQS.
2053 * If mid_min is odd and positive we'll need to add one to
2054 * make sure the rounding in further calculations is correct
2055 * (always bias to the right), so just add 1 for all positive values.
2056 */
2057 if (mid_min > 0)
2058 mid_min++;
2059
2060 mid_min = mid_min / 2;
2061
2062 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2063 __func__, __LINE__, mid_min, min_index);
2064
2065 /* Determine the amount we can change DQS (which is -mid_min) */
2066 orig_mid_min = mid_min;
2067 new_dqs = start_dqs - mid_min;
2068 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2069 new_dqs = IO_DQS_IN_DELAY_MAX;
2070 else if (new_dqs < 0)
2071 new_dqs = 0;
2072
2073 mid_min = start_dqs - new_dqs;
2074 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2075 mid_min, new_dqs);
2076
2077 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2078 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2079 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2080 else if (start_dqs_en - mid_min < 0)
2081 mid_min += start_dqs_en - mid_min;
2082 }
2083 new_dqs = start_dqs - mid_min;
2084
2085 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2086 new_dqs=%d mid_min=%d\n", start_dqs,
2087 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2088 new_dqs, mid_min);
2089
2090 /* Initialize data for export structures */
2091 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2092 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2093
Dinh Nguyen3da42852015-06-02 22:52:49 -05002094 /* add delay to bring centre of all DQ windows to the same "level" */
2095 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2096 /* Use values before divide by 2 to reduce round off error */
2097 shift_dq = (left_edge[i] - right_edge[i] -
2098 (left_edge[min_index] - right_edge[min_index]))/2 +
2099 (orig_mid_min - mid_min);
2100
2101 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2102 shift_dq[%u]=%d\n", i, shift_dq);
2103
Marek Vasut1273dd92015-07-12 21:05:08 +02002104 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002105 temp_dq_in_delay1 = readl(addr + (p << 2));
2106 temp_dq_in_delay2 = readl(addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002107
2108 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2109 (int32_t)IO_IO_IN_DELAY_MAX) {
2110 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2111 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2112 shift_dq = -(int32_t)temp_dq_in_delay1;
2113 }
2114 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2115 shift_dq[%u]=%d\n", i, shift_dq);
2116 final_dq[i] = temp_dq_in_delay1 + shift_dq;
Marek Vasut07aee5b2015-07-12 22:07:33 +02002117 scc_mgr_set_dq_in_delay(p, final_dq[i]);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002118 scc_mgr_load_dq(p);
2119
2120 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2121 left_edge[i] - shift_dq + (-mid_min),
2122 right_edge[i] + shift_dq - (-mid_min));
2123 /* To determine values for export structures */
2124 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2125 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2126
2127 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2128 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2129 }
2130
2131 final_dqs = new_dqs;
2132 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2133 final_dqs_en = start_dqs_en - mid_min;
2134
2135 /* Move DQS-en */
2136 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2137 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2138 scc_mgr_load_dqs(read_group);
2139 }
2140
2141 /* Move DQS */
2142 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2143 scc_mgr_load_dqs(read_group);
2144 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2145 dqs_margin=%d", __func__, __LINE__,
2146 dq_margin, dqs_margin);
2147
2148 /*
2149 * Do not remove this line as it makes sure all of our decisions
2150 * have been applied. Apply the update bit.
2151 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002152 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002153
2154 return (dq_margin >= 0) && (dqs_margin >= 0);
2155}
2156
Marek Vasutbce24ef2015-07-17 03:16:45 +02002157/**
Marek Vasut04372fb2015-07-18 02:46:56 +02002158 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2159 * @rw_group: Read/Write Group
2160 * @phase: DQ/DQS phase
2161 *
2162 * Because initially no communication ca be reliably performed with the memory
2163 * device, the sequencer uses a guaranteed write mechanism to write data into
2164 * the memory device.
2165 */
2166static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2167 const u32 phase)
2168{
Marek Vasut04372fb2015-07-18 02:46:56 +02002169 int ret;
2170
2171 /* Set a particular DQ/DQS phase. */
2172 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2173
2174 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2175 __func__, __LINE__, rw_group, phase);
2176
2177 /*
2178 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2179 * Load up the patterns used by read calibration using the
2180 * current DQDQS phase.
2181 */
2182 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2183
2184 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2185 return 0;
2186
2187 /*
2188 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2189 * Back-to-Back reads of the patterns used for calibration.
2190 */
Marek Vasutd844c7d2015-07-18 03:55:07 +02002191 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2192 if (ret)
Marek Vasut04372fb2015-07-18 02:46:56 +02002193 debug_cond(DLEVEL == 1,
2194 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2195 __func__, __LINE__, rw_group, phase);
Marek Vasutd844c7d2015-07-18 03:55:07 +02002196 return ret;
Marek Vasut04372fb2015-07-18 02:46:56 +02002197}
2198
2199/**
Marek Vasutf09da112015-07-18 02:57:32 +02002200 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2201 * @rw_group: Read/Write Group
2202 * @test_bgn: Rank at which the test begins
2203 *
2204 * DQS enable calibration ensures reliable capture of the DQ signal without
2205 * glitches on the DQS line.
2206 */
2207static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2208 const u32 test_bgn)
2209{
Marek Vasutf09da112015-07-18 02:57:32 +02002210 /*
2211 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2212 * DQS and DQS Eanble Signal Relationships.
2213 */
Marek Vasut28ea8272015-07-18 04:28:42 +02002214
2215 /* We start at zero, so have one less dq to devide among */
2216 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2217 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
Marek Vasut914546e2015-07-20 09:20:42 +02002218 int ret;
Marek Vasut28ea8272015-07-18 04:28:42 +02002219 u32 i, p, d, r;
2220
2221 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2222
2223 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2224 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2225 r += NUM_RANKS_PER_SHADOW_REG) {
2226 for (i = 0, p = test_bgn, d = 0;
2227 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2228 i++, p++, d += delay_step) {
2229 debug_cond(DLEVEL == 1,
2230 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2231 __func__, __LINE__, rw_group, r, i, p, d);
2232
2233 scc_mgr_set_dq_in_delay(p, d);
2234 scc_mgr_load_dq(p);
2235 }
2236
2237 writel(0, &sdr_scc_mgr->update);
2238 }
2239
2240 /*
2241 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2242 * dq_in_delay values
2243 */
Marek Vasut914546e2015-07-20 09:20:42 +02002244 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
Marek Vasut28ea8272015-07-18 04:28:42 +02002245
2246 debug_cond(DLEVEL == 1,
2247 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
Marek Vasut914546e2015-07-20 09:20:42 +02002248 __func__, __LINE__, rw_group, !ret);
Marek Vasut28ea8272015-07-18 04:28:42 +02002249
2250 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2251 r += NUM_RANKS_PER_SHADOW_REG) {
2252 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2253 writel(0, &sdr_scc_mgr->update);
2254 }
2255
Marek Vasut914546e2015-07-20 09:20:42 +02002256 return ret;
Marek Vasutf09da112015-07-18 02:57:32 +02002257}
2258
2259/**
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002260 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2261 * @rw_group: Read/Write Group
2262 * @test_bgn: Rank at which the test begins
2263 * @use_read_test: Perform a read test
2264 * @update_fom: Update FOM
2265 *
2266 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2267 * within a group.
2268 */
2269static int
2270rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2271 const int use_read_test,
2272 const int update_fom)
2273
2274{
2275 int ret, grp_calibrated;
2276 u32 rank_bgn, sr;
2277
2278 /*
2279 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2280 * Read per-bit deskew can be done on a per shadow register basis.
2281 */
2282 grp_calibrated = 1;
2283 for (rank_bgn = 0, sr = 0;
2284 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2285 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2286 /* Check if this set of ranks should be skipped entirely. */
2287 if (param->skip_shadow_regs[sr])
2288 continue;
2289
2290 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2291 rw_group, test_bgn,
2292 use_read_test,
2293 update_fom);
2294 if (ret)
2295 continue;
2296
2297 grp_calibrated = 0;
2298 }
2299
2300 if (!grp_calibrated)
2301 return -EIO;
2302
2303 return 0;
2304}
2305
2306/**
Marek Vasutbce24ef2015-07-17 03:16:45 +02002307 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2308 * @rw_group: Read/Write Group
2309 * @test_bgn: Rank at which the test begins
Dinh Nguyen3da42852015-06-02 22:52:49 -05002310 *
Marek Vasutbce24ef2015-07-17 03:16:45 +02002311 * Stage 1: Calibrate the read valid prediction FIFO.
2312 *
2313 * This function implements UniPHY calibration Stage 1, as explained in
2314 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2315 *
2316 * - read valid prediction will consist of finding:
2317 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2318 * - DQS input phase and DQS input delay (DQ/DQS Centering)
Dinh Nguyen3da42852015-06-02 22:52:49 -05002319 * - we also do a per-bit deskew on the DQ lines.
2320 */
Marek Vasutc336ca32015-07-17 04:24:18 +02002321static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
Dinh Nguyen3da42852015-06-02 22:52:49 -05002322{
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002323 uint32_t p, d;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002324 uint32_t dtaps_per_ptap;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002325 uint32_t failed_substage;
2326
Marek Vasut04372fb2015-07-18 02:46:56 +02002327 int ret;
2328
Marek Vasutc336ca32015-07-17 04:24:18 +02002329 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002330
Marek Vasut7c0a9df2015-07-18 03:15:34 +02002331 /* Update info for sims */
2332 reg_file_set_group(rw_group);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002333 reg_file_set_stage(CAL_STAGE_VFIFO);
Marek Vasut7c0a9df2015-07-18 03:15:34 +02002334 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002335
Marek Vasut7c0a9df2015-07-18 03:15:34 +02002336 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2337
2338 /* USER Determine number of delay taps for each phase tap. */
Marek Vasutd32badb2015-07-17 03:11:06 +02002339 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2340 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002341
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002342 for (d = 0; d <= dtaps_per_ptap; d += 2) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05002343 /*
2344 * In RLDRAMX we may be messing the delay of pins in
Marek Vasutc336ca32015-07-17 04:24:18 +02002345 * the same write rw_group but outside of the current read
2346 * the rw_group, but that's ok because we haven't calibrated
Marek Vasutac70d2f2015-07-17 03:44:26 +02002347 * output side yet.
Dinh Nguyen3da42852015-06-02 22:52:49 -05002348 */
2349 if (d > 0) {
Marek Vasutf51a7d32015-07-19 02:18:21 +02002350 scc_mgr_apply_group_all_out_delay_add_all_ranks(
Marek Vasutc336ca32015-07-17 04:24:18 +02002351 rw_group, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002352 }
2353
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002354 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
Marek Vasut04372fb2015-07-18 02:46:56 +02002355 /* 1) Guaranteed Write */
2356 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2357 if (ret)
2358 break;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002359
Marek Vasutf09da112015-07-18 02:57:32 +02002360 /* 2) DQS Enable Calibration */
2361 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2362 test_bgn);
2363 if (ret) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05002364 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002365 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002366 }
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002367
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002368 /* 3) Centering DQ/DQS */
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002369 /*
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002370 * If doing read after write calibration, do not update
2371 * FOM now. Do it then.
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002372 */
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002373 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2374 test_bgn, 1, 0);
2375 if (ret) {
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002376 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002377 continue;
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002378 }
2379
Marek Vasut16cfc4b2015-07-18 03:10:31 +02002380 /* All done. */
2381 goto cal_done_ok;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002382 }
2383 }
2384
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002385 /* Calibration Stage 1 failed. */
Marek Vasutc336ca32015-07-17 04:24:18 +02002386 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002387 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002388
Marek Vasutfe2d0a22015-07-17 03:50:17 +02002389 /* Calibration Stage 1 completed OK. */
2390cal_done_ok:
Dinh Nguyen3da42852015-06-02 22:52:49 -05002391 /*
2392 * Reset the delay chains back to zero if they have moved > 1
2393 * (check for > 1 because loop will increase d even when pass in
2394 * first case).
2395 */
2396 if (d > 2)
Marek Vasutc336ca32015-07-17 04:24:18 +02002397 scc_mgr_zero_group(rw_group, 1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002398
2399 return 1;
2400}
2401
2402/* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2403static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2404 uint32_t test_bgn)
2405{
2406 uint32_t rank_bgn, sr;
2407 uint32_t grp_calibrated;
2408 uint32_t write_group;
2409
2410 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2411
2412 /* update info for sims */
2413
2414 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2415 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2416
2417 write_group = read_group;
2418
2419 /* update info for sims */
2420 reg_file_set_group(read_group);
2421
2422 grp_calibrated = 1;
2423 /* Read per-bit deskew can be done on a per shadow register basis */
2424 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2425 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2426 /* Determine if this set of ranks should be skipped entirely */
2427 if (!param->skip_shadow_regs[sr]) {
2428 /* This is the last calibration round, update FOM here */
2429 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2430 write_group,
2431 read_group,
2432 test_bgn, 0,
2433 1)) {
2434 grp_calibrated = 0;
2435 }
2436 }
2437 }
2438
2439
2440 if (grp_calibrated == 0) {
2441 set_failing_group_stage(write_group,
2442 CAL_STAGE_VFIFO_AFTER_WRITES,
2443 CAL_SUBSTAGE_VFIFO_CENTER);
2444 return 0;
2445 }
2446
2447 return 1;
2448}
2449
2450/* Calibrate LFIFO to find smallest read latency */
2451static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2452{
2453 uint32_t found_one;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002454
2455 debug("%s:%d\n", __func__, __LINE__);
2456
2457 /* update info for sims */
2458 reg_file_set_stage(CAL_STAGE_LFIFO);
2459 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2460
2461 /* Load up the patterns used by read calibration for all ranks */
2462 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2463 found_one = 0;
2464
Dinh Nguyen3da42852015-06-02 22:52:49 -05002465 do {
Marek Vasut1273dd92015-07-12 21:05:08 +02002466 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002467 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2468 __func__, __LINE__, gbl->curr_read_lat);
2469
2470 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2471 NUM_READ_TESTS,
2472 PASS_ALL_BITS,
Marek Vasut96df6032015-07-19 07:35:36 +02002473 1)) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05002474 break;
2475 }
2476
2477 found_one = 1;
2478 /* reduce read latency and see if things are working */
2479 /* correctly */
2480 gbl->curr_read_lat--;
2481 } while (gbl->curr_read_lat > 0);
2482
2483 /* reset the fifos to get pointers to known state */
2484
Marek Vasut1273dd92015-07-12 21:05:08 +02002485 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002486
2487 if (found_one) {
2488 /* add a fudge factor to the read latency that was determined */
2489 gbl->curr_read_lat += 2;
Marek Vasut1273dd92015-07-12 21:05:08 +02002490 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002491 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2492 read_lat=%u\n", __func__, __LINE__,
2493 gbl->curr_read_lat);
2494 return 1;
2495 } else {
2496 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2497 CAL_SUBSTAGE_READ_LATENCY);
2498
2499 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2500 read_lat=%u\n", __func__, __LINE__,
2501 gbl->curr_read_lat);
2502 return 0;
2503 }
2504}
2505
2506/*
2507 * issue write test command.
2508 * two variants are provided. one that just tests a write pattern and
2509 * another that tests datamask functionality.
2510 */
2511static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2512 uint32_t test_dm)
2513{
2514 uint32_t mcc_instruction;
2515 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2516 ENABLE_SUPER_QUICK_CALIBRATION);
2517 uint32_t rw_wl_nop_cycles;
2518 uint32_t addr;
2519
2520 /*
2521 * Set counter and jump addresses for the right
2522 * number of NOP cycles.
2523 * The number of supported NOP cycles can range from -1 to infinity
2524 * Three different cases are handled:
2525 *
2526 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2527 * mechanism will be used to insert the right number of NOPs
2528 *
2529 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2530 * issuing the write command will jump straight to the
2531 * micro-instruction that turns on DQS (for DDRx), or outputs write
2532 * data (for RLD), skipping
2533 * the NOP micro-instruction all together
2534 *
2535 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2536 * turned on in the same micro-instruction that issues the write
2537 * command. Then we need
2538 * to directly jump to the micro-instruction that sends out the data
2539 *
2540 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2541 * (2 and 3). One jump-counter (0) is used to perform multiple
2542 * write-read operations.
2543 * one counter left to issue this command in "multiple-group" mode
2544 */
2545
2546 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2547
2548 if (rw_wl_nop_cycles == -1) {
2549 /*
2550 * CNTR 2 - We want to execute the special write operation that
2551 * turns on DQS right away and then skip directly to the
2552 * instruction that sends out the data. We set the counter to a
2553 * large number so that the jump is always taken.
2554 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002555 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002556
2557 /* CNTR 3 - Not used */
2558 if (test_dm) {
2559 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002560 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
Marek Vasut1273dd92015-07-12 21:05:08 +02002561 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002562 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
Marek Vasut1273dd92015-07-12 21:05:08 +02002563 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002564 } else {
2565 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
Marek Vasut1273dd92015-07-12 21:05:08 +02002566 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2567 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2568 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2569 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002570 }
2571 } else if (rw_wl_nop_cycles == 0) {
2572 /*
2573 * CNTR 2 - We want to skip the NOP operation and go straight
2574 * to the DQS enable instruction. We set the counter to a large
2575 * number so that the jump is always taken.
2576 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002577 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002578
2579 /* CNTR 3 - Not used */
2580 if (test_dm) {
2581 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002582 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
Marek Vasut1273dd92015-07-12 21:05:08 +02002583 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002584 } else {
2585 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002586 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2587 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002588 }
2589 } else {
2590 /*
2591 * CNTR 2 - In this case we want to execute the next instruction
2592 * and NOT take the jump. So we set the counter to 0. The jump
2593 * address doesn't count.
2594 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002595 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2596 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002597
2598 /*
2599 * CNTR 3 - Set the nop counter to the number of cycles we
2600 * need to loop for, minus 1.
2601 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002602 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002603 if (test_dm) {
2604 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002605 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2606 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002607 } else {
2608 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
Marek Vasut1273dd92015-07-12 21:05:08 +02002609 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2610 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002611 }
2612 }
2613
Marek Vasut1273dd92015-07-12 21:05:08 +02002614 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2615 RW_MGR_RESET_READ_DATAPATH_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002616
Dinh Nguyen3da42852015-06-02 22:52:49 -05002617 if (quick_write_mode)
Marek Vasut1273dd92015-07-12 21:05:08 +02002618 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002619 else
Marek Vasut1273dd92015-07-12 21:05:08 +02002620 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002621
Marek Vasut1273dd92015-07-12 21:05:08 +02002622 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002623
2624 /*
2625 * CNTR 1 - This is used to ensure enough time elapses
2626 * for read data to come back.
2627 */
Marek Vasut1273dd92015-07-12 21:05:08 +02002628 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002629
Dinh Nguyen3da42852015-06-02 22:52:49 -05002630 if (test_dm) {
Marek Vasut1273dd92015-07-12 21:05:08 +02002631 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2632 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002633 } else {
Marek Vasut1273dd92015-07-12 21:05:08 +02002634 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2635 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002636 }
2637
Marek Vasutc4815f72015-07-12 19:03:33 +02002638 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002639 writel(mcc_instruction, addr + (group << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002640}
2641
2642/* Test writes, can check for a single bit pass or multiple bit pass */
2643static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2644 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2645 uint32_t *bit_chk, uint32_t all_ranks)
2646{
Dinh Nguyen3da42852015-06-02 22:52:49 -05002647 uint32_t r;
2648 uint32_t correct_mask_vg;
2649 uint32_t tmp_bit_chk;
2650 uint32_t vg;
2651 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2652 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2653 uint32_t addr_rw_mgr;
2654 uint32_t base_rw_mgr;
2655
2656 *bit_chk = param->write_correct_mask;
2657 correct_mask_vg = param->write_correct_mask_vg;
2658
2659 for (r = rank_bgn; r < rank_end; r++) {
2660 if (param->skip_ranks[r]) {
2661 /* request to skip the rank */
2662 continue;
2663 }
2664
2665 /* set rank */
2666 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2667
2668 tmp_bit_chk = 0;
Marek Vasuta4bfa462015-07-12 17:52:36 +02002669 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
Dinh Nguyen3da42852015-06-02 22:52:49 -05002670 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2671 /* reset the fifos to get pointers to known state */
Marek Vasut1273dd92015-07-12 21:05:08 +02002672 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002673
2674 tmp_bit_chk = tmp_bit_chk <<
2675 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2676 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2677 rw_mgr_mem_calibrate_write_test_issue(write_group *
2678 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2679 use_dm);
2680
Marek Vasut17fdc912015-07-12 20:05:54 +02002681 base_rw_mgr = readl(addr_rw_mgr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002682 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2683 if (vg == 0)
2684 break;
2685 }
2686 *bit_chk &= tmp_bit_chk;
2687 }
2688
2689 if (all_correct) {
2690 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2691 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2692 %u => %lu", write_group, use_dm,
2693 *bit_chk, param->write_correct_mask,
2694 (long unsigned int)(*bit_chk ==
2695 param->write_correct_mask));
2696 return *bit_chk == param->write_correct_mask;
2697 } else {
2698 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2699 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2700 write_group, use_dm, *bit_chk);
2701 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2702 (long unsigned int)(*bit_chk != 0));
2703 return *bit_chk != 0x00;
2704 }
2705}
2706
2707/*
2708 * center all windows. do per-bit-deskew to possibly increase size of
2709 * certain windows.
2710 */
2711static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2712 uint32_t write_group, uint32_t test_bgn)
2713{
2714 uint32_t i, p, min_index;
2715 int32_t d;
2716 /*
2717 * Store these as signed since there are comparisons with
2718 * signed numbers.
2719 */
2720 uint32_t bit_chk;
2721 uint32_t sticky_bit_chk;
2722 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2723 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2724 int32_t mid;
2725 int32_t mid_min, orig_mid_min;
2726 int32_t new_dqs, start_dqs, shift_dq;
2727 int32_t dq_margin, dqs_margin, dm_margin;
2728 uint32_t stop;
2729 uint32_t temp_dq_out1_delay;
2730 uint32_t addr;
2731
2732 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2733
2734 dm_margin = 0;
2735
Marek Vasutc4815f72015-07-12 19:03:33 +02002736 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002737 start_dqs = readl(addr +
Dinh Nguyen3da42852015-06-02 22:52:49 -05002738 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2739
2740 /* per-bit deskew */
2741
2742 /*
2743 * set the left and right edge of each bit to an illegal value
2744 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2745 */
2746 sticky_bit_chk = 0;
2747 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2748 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2749 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2750 }
2751
2752 /* Search for the left edge of the window for each bit */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002753 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
Marek Vasut300c2e62015-07-17 05:42:49 +02002754 scc_mgr_apply_group_dq_out1_delay(write_group, d);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002755
Marek Vasut1273dd92015-07-12 21:05:08 +02002756 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002757
2758 /*
2759 * Stop searching when the read test doesn't pass AND when
2760 * we've seen a passing read on every bit.
2761 */
2762 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2763 0, PASS_ONE_BIT, &bit_chk, 0);
2764 sticky_bit_chk = sticky_bit_chk | bit_chk;
2765 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2766 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2767 == %u && %u [bit_chk= %u ]\n",
2768 d, sticky_bit_chk, param->write_correct_mask,
2769 stop, bit_chk);
2770
2771 if (stop == 1) {
2772 break;
2773 } else {
2774 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2775 if (bit_chk & 1) {
2776 /*
2777 * Remember a passing test as the
2778 * left_edge.
2779 */
2780 left_edge[i] = d;
2781 } else {
2782 /*
2783 * If a left edge has not been seen
2784 * yet, then a future passing test will
2785 * mark this edge as the right edge.
2786 */
2787 if (left_edge[i] ==
2788 IO_IO_OUT1_DELAY_MAX + 1) {
2789 right_edge[i] = -(d + 1);
2790 }
2791 }
2792 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2793 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2794 (int)(bit_chk & 1), i, left_edge[i]);
2795 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2796 right_edge[i]);
2797 bit_chk = bit_chk >> 1;
2798 }
2799 }
2800 }
2801
2802 /* Reset DQ delay chains to 0 */
Marek Vasut32675242015-07-17 06:07:13 +02002803 scc_mgr_apply_group_dq_out1_delay(0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002804 sticky_bit_chk = 0;
2805 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2806 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2807 %d right_edge[%u]: %d\n", __func__, __LINE__,
2808 i, left_edge[i], i, right_edge[i]);
2809
2810 /*
2811 * Check for cases where we haven't found the left edge,
2812 * which makes our assignment of the the right edge invalid.
2813 * Reset it to the illegal value.
2814 */
2815 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2816 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2817 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2818 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2819 right_edge[%u]: %d\n", __func__, __LINE__,
2820 i, right_edge[i]);
2821 }
2822
2823 /*
2824 * Reset sticky bit (except for bits where we have
2825 * seen the left edge).
2826 */
2827 sticky_bit_chk = sticky_bit_chk << 1;
2828 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2829 sticky_bit_chk = sticky_bit_chk | 1;
2830
2831 if (i == 0)
2832 break;
2833 }
2834
2835 /* Search for the right edge of the window for each bit */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002836 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2837 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2838 d + start_dqs);
2839
Marek Vasut1273dd92015-07-12 21:05:08 +02002840 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002841
2842 /*
2843 * Stop searching when the read test doesn't pass AND when
2844 * we've seen a passing read on every bit.
2845 */
2846 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2847 0, PASS_ONE_BIT, &bit_chk, 0);
2848
2849 sticky_bit_chk = sticky_bit_chk | bit_chk;
2850 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2851
2852 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2853 %u && %u\n", d, sticky_bit_chk,
2854 param->write_correct_mask, stop);
2855
2856 if (stop == 1) {
2857 if (d == 0) {
2858 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2859 i++) {
2860 /* d = 0 failed, but it passed when
2861 testing the left edge, so it must be
2862 marginal, set it to -1 */
2863 if (right_edge[i] ==
2864 IO_IO_OUT1_DELAY_MAX + 1 &&
2865 left_edge[i] !=
2866 IO_IO_OUT1_DELAY_MAX + 1) {
2867 right_edge[i] = -1;
2868 }
2869 }
2870 }
2871 break;
2872 } else {
2873 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2874 if (bit_chk & 1) {
2875 /*
2876 * Remember a passing test as
2877 * the right_edge.
2878 */
2879 right_edge[i] = d;
2880 } else {
2881 if (d != 0) {
2882 /*
2883 * If a right edge has not
2884 * been seen yet, then a future
2885 * passing test will mark this
2886 * edge as the left edge.
2887 */
2888 if (right_edge[i] ==
2889 IO_IO_OUT1_DELAY_MAX + 1)
2890 left_edge[i] = -(d + 1);
2891 } else {
2892 /*
2893 * d = 0 failed, but it passed
2894 * when testing the left edge,
2895 * so it must be marginal, set
2896 * it to -1.
2897 */
2898 if (right_edge[i] ==
2899 IO_IO_OUT1_DELAY_MAX + 1 &&
2900 left_edge[i] !=
2901 IO_IO_OUT1_DELAY_MAX + 1)
2902 right_edge[i] = -1;
2903 /*
2904 * If a right edge has not been
2905 * seen yet, then a future
2906 * passing test will mark this
2907 * edge as the left edge.
2908 */
2909 else if (right_edge[i] ==
2910 IO_IO_OUT1_DELAY_MAX +
2911 1)
2912 left_edge[i] = -(d + 1);
2913 }
2914 }
2915 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2916 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2917 (int)(bit_chk & 1), i, left_edge[i]);
2918 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2919 right_edge[i]);
2920 bit_chk = bit_chk >> 1;
2921 }
2922 }
2923 }
2924
2925 /* Check that all bits have a window */
2926 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2927 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2928 %d right_edge[%u]: %d", __func__, __LINE__,
2929 i, left_edge[i], i, right_edge[i]);
2930 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2931 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2932 set_failing_group_stage(test_bgn + i,
2933 CAL_STAGE_WRITES,
2934 CAL_SUBSTAGE_WRITES_CENTER);
2935 return 0;
2936 }
2937 }
2938
2939 /* Find middle of window for each DQ bit */
2940 mid_min = left_edge[0] - right_edge[0];
2941 min_index = 0;
2942 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2943 mid = left_edge[i] - right_edge[i];
2944 if (mid < mid_min) {
2945 mid_min = mid;
2946 min_index = i;
2947 }
2948 }
2949
2950 /*
2951 * -mid_min/2 represents the amount that we need to move DQS.
2952 * If mid_min is odd and positive we'll need to add one to
2953 * make sure the rounding in further calculations is correct
2954 * (always bias to the right), so just add 1 for all positive values.
2955 */
2956 if (mid_min > 0)
2957 mid_min++;
2958 mid_min = mid_min / 2;
2959 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2960 __LINE__, mid_min);
2961
2962 /* Determine the amount we can change DQS (which is -mid_min) */
2963 orig_mid_min = mid_min;
2964 new_dqs = start_dqs;
2965 mid_min = 0;
2966 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2967 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2968 /* Initialize data for export structures */
2969 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2970 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2971
2972 /* add delay to bring centre of all DQ windows to the same "level" */
Dinh Nguyen3da42852015-06-02 22:52:49 -05002973 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2974 /* Use values before divide by 2 to reduce round off error */
2975 shift_dq = (left_edge[i] - right_edge[i] -
2976 (left_edge[min_index] - right_edge[min_index]))/2 +
2977 (orig_mid_min - mid_min);
2978
2979 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2980 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2981
Marek Vasut1273dd92015-07-12 21:05:08 +02002982 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
Marek Vasut17fdc912015-07-12 20:05:54 +02002983 temp_dq_out1_delay = readl(addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05002984 if (shift_dq + (int32_t)temp_dq_out1_delay >
2985 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2986 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2987 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2988 shift_dq = -(int32_t)temp_dq_out1_delay;
2989 }
2990 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2991 i, shift_dq);
Marek Vasut07aee5b2015-07-12 22:07:33 +02002992 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
Dinh Nguyen3da42852015-06-02 22:52:49 -05002993 scc_mgr_load_dq(i);
2994
2995 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2996 left_edge[i] - shift_dq + (-mid_min),
2997 right_edge[i] + shift_dq - (-mid_min));
2998 /* To determine values for export structures */
2999 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
3000 dq_margin = left_edge[i] - shift_dq + (-mid_min);
3001
3002 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
3003 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
3004 }
3005
3006 /* Move DQS */
3007 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
Marek Vasut1273dd92015-07-12 21:05:08 +02003008 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003009
3010 /* Centre DM */
3011 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3012
3013 /*
3014 * set the left and right edge of each bit to an illegal value,
3015 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3016 */
3017 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3018 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3019 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3020 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3021 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3022 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3023 int32_t win_best = 0;
3024
3025 /* Search for the/part of the window with DM shift */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003026 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
Marek Vasut32675242015-07-17 06:07:13 +02003027 scc_mgr_apply_group_dm_out1_delay(d);
Marek Vasut1273dd92015-07-12 21:05:08 +02003028 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003029
3030 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3031 PASS_ALL_BITS, &bit_chk,
3032 0)) {
3033 /* USE Set current end of the window */
3034 end_curr = -d;
3035 /*
3036 * If a starting edge of our window has not been seen
3037 * this is our current start of the DM window.
3038 */
3039 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3040 bgn_curr = -d;
3041
3042 /*
3043 * If current window is bigger than best seen.
3044 * Set best seen to be current window.
3045 */
3046 if ((end_curr-bgn_curr+1) > win_best) {
3047 win_best = end_curr-bgn_curr+1;
3048 bgn_best = bgn_curr;
3049 end_best = end_curr;
3050 }
3051 } else {
3052 /* We just saw a failing test. Reset temp edge */
3053 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3054 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3055 }
3056 }
3057
3058
3059 /* Reset DM delay chains to 0 */
Marek Vasut32675242015-07-17 06:07:13 +02003060 scc_mgr_apply_group_dm_out1_delay(0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003061
3062 /*
3063 * Check to see if the current window nudges up aganist 0 delay.
3064 * If so we need to continue the search by shifting DQS otherwise DQS
3065 * search begins as a new search. */
3066 if (end_curr != 0) {
3067 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3068 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3069 }
3070
3071 /* Search for the/part of the window with DQS shifts */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003072 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3073 /*
3074 * Note: This only shifts DQS, so are we limiting ourselve to
3075 * width of DQ unnecessarily.
3076 */
3077 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3078 d + new_dqs);
3079
Marek Vasut1273dd92015-07-12 21:05:08 +02003080 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003081 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3082 PASS_ALL_BITS, &bit_chk,
3083 0)) {
3084 /* USE Set current end of the window */
3085 end_curr = d;
3086 /*
3087 * If a beginning edge of our window has not been seen
3088 * this is our current begin of the DM window.
3089 */
3090 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3091 bgn_curr = d;
3092
3093 /*
3094 * If current window is bigger than best seen. Set best
3095 * seen to be current window.
3096 */
3097 if ((end_curr-bgn_curr+1) > win_best) {
3098 win_best = end_curr-bgn_curr+1;
3099 bgn_best = bgn_curr;
3100 end_best = end_curr;
3101 }
3102 } else {
3103 /* We just saw a failing test. Reset temp edge */
3104 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3105 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3106
3107 /* Early exit optimization: if ther remaining delay
3108 chain space is less than already seen largest window
3109 we can exit */
3110 if ((win_best-1) >
3111 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3112 break;
3113 }
3114 }
3115 }
3116
3117 /* assign left and right edge for cal and reporting; */
3118 left_edge[0] = -1*bgn_best;
3119 right_edge[0] = end_best;
3120
3121 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3122 __LINE__, left_edge[0], right_edge[0]);
3123
3124 /* Move DQS (back to orig) */
3125 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3126
3127 /* Move DM */
3128
3129 /* Find middle of window for the DM bit */
3130 mid = (left_edge[0] - right_edge[0]) / 2;
3131
3132 /* only move right, since we are not moving DQS/DQ */
3133 if (mid < 0)
3134 mid = 0;
3135
3136 /* dm_marign should fail if we never find a window */
3137 if (win_best == 0)
3138 dm_margin = -1;
3139 else
3140 dm_margin = left_edge[0] - mid;
3141
Marek Vasut32675242015-07-17 06:07:13 +02003142 scc_mgr_apply_group_dm_out1_delay(mid);
Marek Vasut1273dd92015-07-12 21:05:08 +02003143 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003144
3145 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3146 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3147 right_edge[0], mid, dm_margin);
3148 /* Export values */
3149 gbl->fom_out += dq_margin + dqs_margin;
3150
3151 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3152 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3153 dq_margin, dqs_margin, dm_margin);
3154
3155 /*
3156 * Do not remove this line as it makes sure all of our
3157 * decisions have been applied.
3158 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003159 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003160 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3161}
3162
3163/* calibrate the write operations */
3164static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3165 uint32_t test_bgn)
3166{
3167 /* update info for sims */
3168 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3169
3170 reg_file_set_stage(CAL_STAGE_WRITES);
3171 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3172
3173 reg_file_set_group(g);
3174
3175 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3176 set_failing_group_stage(g, CAL_STAGE_WRITES,
3177 CAL_SUBSTAGE_WRITES_CENTER);
3178 return 0;
3179 }
3180
3181 return 1;
3182}
3183
Marek Vasut4b0ac262015-07-20 07:33:33 +02003184/**
3185 * mem_precharge_and_activate() - Precharge all banks and activate
3186 *
3187 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3188 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003189static void mem_precharge_and_activate(void)
3190{
Marek Vasut4b0ac262015-07-20 07:33:33 +02003191 int r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003192
3193 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
Marek Vasut4b0ac262015-07-20 07:33:33 +02003194 /* Test if the rank should be skipped. */
3195 if (param->skip_ranks[r])
Dinh Nguyen3da42852015-06-02 22:52:49 -05003196 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003197
Marek Vasut4b0ac262015-07-20 07:33:33 +02003198 /* Set rank. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003199 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3200
Marek Vasut4b0ac262015-07-20 07:33:33 +02003201 /* Precharge all banks. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003202 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3203 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003204
Marek Vasut1273dd92015-07-12 21:05:08 +02003205 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3206 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3207 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003208
Marek Vasut1273dd92015-07-12 21:05:08 +02003209 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3210 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3211 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003212
Marek Vasut4b0ac262015-07-20 07:33:33 +02003213 /* Activate rows. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003214 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3215 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003216 }
3217}
3218
Marek Vasut16502a02015-07-17 01:57:41 +02003219/**
3220 * mem_init_latency() - Configure memory RLAT and WLAT settings
3221 *
3222 * Configure memory RLAT and WLAT parameters.
3223 */
3224static void mem_init_latency(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -05003225{
Marek Vasut16502a02015-07-17 01:57:41 +02003226 /*
3227 * For AV/CV, LFIFO is hardened and always runs at full rate
3228 * so max latency in AFI clocks, used here, is correspondingly
3229 * smaller.
3230 */
3231 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3232 u32 rlat, wlat;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003233
3234 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut16502a02015-07-17 01:57:41 +02003235
3236 /*
3237 * Read in write latency.
3238 * WL for Hard PHY does not include additive latency.
3239 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003240 wlat = readl(&data_mgr->t_wl_add);
3241 wlat += readl(&data_mgr->mem_t_add);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003242
Marek Vasut16502a02015-07-17 01:57:41 +02003243 gbl->rw_wl_nop_cycles = wlat - 1;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003244
Marek Vasut16502a02015-07-17 01:57:41 +02003245 /* Read in readl latency. */
Marek Vasut1273dd92015-07-12 21:05:08 +02003246 rlat = readl(&data_mgr->t_rl_add);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003247
Marek Vasut16502a02015-07-17 01:57:41 +02003248 /* Set a pretty high read latency initially. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003249 gbl->curr_read_lat = rlat + 16;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003250 if (gbl->curr_read_lat > max_latency)
3251 gbl->curr_read_lat = max_latency;
3252
Marek Vasut1273dd92015-07-12 21:05:08 +02003253 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003254
Marek Vasut16502a02015-07-17 01:57:41 +02003255 /* Advertise write latency. */
3256 writel(wlat, &phy_mgr_cfg->afi_wlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003257}
3258
Marek Vasut51cea0b2015-07-26 10:54:15 +02003259/**
3260 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3261 *
3262 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3263 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003264static void mem_skip_calibrate(void)
3265{
3266 uint32_t vfifo_offset;
3267 uint32_t i, j, r;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003268
3269 debug("%s:%d\n", __func__, __LINE__);
3270 /* Need to update every shadow register set used by the interface */
3271 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
Marek Vasut51cea0b2015-07-26 10:54:15 +02003272 r += NUM_RANKS_PER_SHADOW_REG) {
Dinh Nguyen3da42852015-06-02 22:52:49 -05003273 /*
3274 * Set output phase alignment settings appropriate for
3275 * skip calibration.
3276 */
3277 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3278 scc_mgr_set_dqs_en_phase(i, 0);
3279#if IO_DLL_CHAIN_LENGTH == 6
3280 scc_mgr_set_dqdqs_output_phase(i, 6);
3281#else
3282 scc_mgr_set_dqdqs_output_phase(i, 7);
3283#endif
3284 /*
3285 * Case:33398
3286 *
3287 * Write data arrives to the I/O two cycles before write
3288 * latency is reached (720 deg).
3289 * -> due to bit-slip in a/c bus
3290 * -> to allow board skew where dqs is longer than ck
3291 * -> how often can this happen!?
3292 * -> can claim back some ptaps for high freq
3293 * support if we can relax this, but i digress...
3294 *
3295 * The write_clk leads mem_ck by 90 deg
3296 * The minimum ptap of the OPA is 180 deg
3297 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3298 * The write_clk is always delayed by 2 ptaps
3299 *
3300 * Hence, to make DQS aligned to CK, we need to delay
3301 * DQS by:
3302 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3303 *
3304 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3305 * gives us the number of ptaps, which simplies to:
3306 *
3307 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3308 */
Marek Vasut51cea0b2015-07-26 10:54:15 +02003309 scc_mgr_set_dqdqs_output_phase(i,
3310 1.25 * IO_DLL_CHAIN_LENGTH - 2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003311 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003312 writel(0xff, &sdr_scc_mgr->dqs_ena);
3313 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003314
Dinh Nguyen3da42852015-06-02 22:52:49 -05003315 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
Marek Vasut1273dd92015-07-12 21:05:08 +02003316 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3317 SCC_MGR_GROUP_COUNTER_OFFSET);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003318 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003319 writel(0xff, &sdr_scc_mgr->dq_ena);
3320 writel(0xff, &sdr_scc_mgr->dm_ena);
3321 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003322 }
3323
3324 /* Compensate for simulation model behaviour */
3325 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3326 scc_mgr_set_dqs_bus_in_delay(i, 10);
3327 scc_mgr_load_dqs(i);
3328 }
Marek Vasut1273dd92015-07-12 21:05:08 +02003329 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003330
3331 /*
3332 * ArriaV has hard FIFOs that can only be initialized by incrementing
3333 * in sequencer.
3334 */
3335 vfifo_offset = CALIB_VFIFO_OFFSET;
Marek Vasut51cea0b2015-07-26 10:54:15 +02003336 for (j = 0; j < vfifo_offset; j++)
Marek Vasut1273dd92015-07-12 21:05:08 +02003337 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
Marek Vasut1273dd92015-07-12 21:05:08 +02003338 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003339
3340 /*
Marek Vasut51cea0b2015-07-26 10:54:15 +02003341 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3342 * setting from generation-time constant.
Dinh Nguyen3da42852015-06-02 22:52:49 -05003343 */
3344 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
Marek Vasut1273dd92015-07-12 21:05:08 +02003345 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003346}
3347
Marek Vasut3589fbf2015-07-20 04:34:51 +02003348/**
3349 * mem_calibrate() - Memory calibration entry point.
3350 *
3351 * Perform memory calibration.
3352 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003353static uint32_t mem_calibrate(void)
3354{
3355 uint32_t i;
3356 uint32_t rank_bgn, sr;
3357 uint32_t write_group, write_test_bgn;
3358 uint32_t read_group, read_test_bgn;
3359 uint32_t run_groups, current_run;
3360 uint32_t failing_groups = 0;
3361 uint32_t group_failed = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003362
Marek Vasut33c42bb2015-07-17 02:21:47 +02003363 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3364 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3365
Dinh Nguyen3da42852015-06-02 22:52:49 -05003366 debug("%s:%d\n", __func__, __LINE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003367
Marek Vasut16502a02015-07-17 01:57:41 +02003368 /* Initialize the data settings */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003369 gbl->error_substage = CAL_SUBSTAGE_NIL;
3370 gbl->error_stage = CAL_STAGE_NIL;
3371 gbl->error_group = 0xff;
3372 gbl->fom_in = 0;
3373 gbl->fom_out = 0;
3374
Marek Vasut16502a02015-07-17 01:57:41 +02003375 /* Initialize WLAT and RLAT. */
3376 mem_init_latency();
3377
3378 /* Initialize bit slips. */
3379 mem_precharge_and_activate();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003380
Dinh Nguyen3da42852015-06-02 22:52:49 -05003381 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
Marek Vasut1273dd92015-07-12 21:05:08 +02003382 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3383 SCC_MGR_GROUP_COUNTER_OFFSET);
Marek Vasutfa5d8212015-07-19 01:34:43 +02003384 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3385 if (i == 0)
3386 scc_mgr_set_hhp_extras();
3387
Marek Vasutc5c5f532015-07-17 02:06:20 +02003388 scc_set_bypass_mode(i);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003389 }
3390
Marek Vasut722c9682015-07-17 02:07:12 +02003391 /* Calibration is skipped. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003392 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3393 /*
3394 * Set VFIFO and LFIFO to instant-on settings in skip
3395 * calibration mode.
3396 */
3397 mem_skip_calibrate();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003398
Marek Vasut722c9682015-07-17 02:07:12 +02003399 /*
3400 * Do not remove this line as it makes sure all of our
3401 * decisions have been applied.
3402 */
3403 writel(0, &sdr_scc_mgr->update);
3404 return 1;
3405 }
Dinh Nguyen3da42852015-06-02 22:52:49 -05003406
Marek Vasut722c9682015-07-17 02:07:12 +02003407 /* Calibration is not skipped. */
3408 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3409 /*
3410 * Zero all delay chain/phase settings for all
3411 * groups and all shadow register sets.
3412 */
3413 scc_mgr_zero_all();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003414
Marek Vasut722c9682015-07-17 02:07:12 +02003415 run_groups = ~param->skip_groups;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003416
Marek Vasut722c9682015-07-17 02:07:12 +02003417 for (write_group = 0, write_test_bgn = 0; write_group
3418 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3419 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
Marek Vasutc452dcd2015-07-17 02:50:56 +02003420
3421 /* Initialize the group failure */
Marek Vasut722c9682015-07-17 02:07:12 +02003422 group_failed = 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003423
Marek Vasut722c9682015-07-17 02:07:12 +02003424 current_run = run_groups & ((1 <<
3425 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3426 run_groups = run_groups >>
3427 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003428
Marek Vasut722c9682015-07-17 02:07:12 +02003429 if (current_run == 0)
3430 continue;
3431
3432 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3433 SCC_MGR_GROUP_COUNTER_OFFSET);
3434 scc_mgr_zero_group(write_group, 0);
3435
Marek Vasut33c42bb2015-07-17 02:21:47 +02003436 for (read_group = write_group * rwdqs_ratio,
3437 read_test_bgn = 0;
Marek Vasutc452dcd2015-07-17 02:50:56 +02003438 read_group < (write_group + 1) * rwdqs_ratio;
Marek Vasut33c42bb2015-07-17 02:21:47 +02003439 read_group++,
3440 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3441 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3442 continue;
Marek Vasut722c9682015-07-17 02:07:12 +02003443
Marek Vasut33c42bb2015-07-17 02:21:47 +02003444 /* Calibrate the VFIFO */
3445 if (rw_mgr_mem_calibrate_vfifo(read_group,
3446 read_test_bgn))
3447 continue;
3448
Marek Vasutc452dcd2015-07-17 02:50:56 +02003449 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3450 return 0;
3451
3452 /* The group failed, we're done. */
3453 goto grp_failed;
3454 }
3455
3456 /* Calibrate the output side */
3457 for (rank_bgn = 0, sr = 0;
3458 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3459 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3460 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3461 continue;
3462
3463 /* Not needed in quick mode! */
3464 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3465 continue;
3466
3467 /*
3468 * Determine if this set of ranks
3469 * should be skipped entirely.
3470 */
3471 if (param->skip_shadow_regs[sr])
3472 continue;
3473
3474 /* Calibrate WRITEs */
3475 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3476 write_group, write_test_bgn))
3477 continue;
3478
Marek Vasut33c42bb2015-07-17 02:21:47 +02003479 group_failed = 1;
3480 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3481 return 0;
Marek Vasut722c9682015-07-17 02:07:12 +02003482 }
3483
Marek Vasutc452dcd2015-07-17 02:50:56 +02003484 /* Some group failed, we're done. */
3485 if (group_failed)
3486 goto grp_failed;
Marek Vasut4ac21612015-07-17 02:31:04 +02003487
Marek Vasutc452dcd2015-07-17 02:50:56 +02003488 for (read_group = write_group * rwdqs_ratio,
3489 read_test_bgn = 0;
3490 read_group < (write_group + 1) * rwdqs_ratio;
3491 read_group++,
3492 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3493 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3494 continue;
Marek Vasut4ac21612015-07-17 02:31:04 +02003495
Marek Vasutc452dcd2015-07-17 02:50:56 +02003496 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3497 read_test_bgn))
3498 continue;
Marek Vasut4ac21612015-07-17 02:31:04 +02003499
Marek Vasutc452dcd2015-07-17 02:50:56 +02003500 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3501 return 0;
Marek Vasut4ac21612015-07-17 02:31:04 +02003502
Marek Vasutc452dcd2015-07-17 02:50:56 +02003503 /* The group failed, we're done. */
3504 goto grp_failed;
Marek Vasut722c9682015-07-17 02:07:12 +02003505 }
3506
Marek Vasutc452dcd2015-07-17 02:50:56 +02003507 /* No group failed, continue as usual. */
3508 continue;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003509
Marek Vasutc452dcd2015-07-17 02:50:56 +02003510grp_failed: /* A group failed, increment the counter. */
3511 failing_groups++;
Marek Vasut722c9682015-07-17 02:07:12 +02003512 }
Dinh Nguyen3da42852015-06-02 22:52:49 -05003513
Marek Vasut722c9682015-07-17 02:07:12 +02003514 /*
3515 * USER If there are any failing groups then report
3516 * the failure.
3517 */
3518 if (failing_groups != 0)
3519 return 0;
3520
Marek Vasutc50ae302015-07-17 02:40:21 +02003521 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3522 continue;
3523
3524 /*
3525 * If we're skipping groups as part of debug,
3526 * don't calibrate LFIFO.
3527 */
3528 if (param->skip_groups != 0)
3529 continue;
3530
Marek Vasut722c9682015-07-17 02:07:12 +02003531 /* Calibrate the LFIFO */
Marek Vasutc50ae302015-07-17 02:40:21 +02003532 if (!rw_mgr_mem_calibrate_lfifo())
3533 return 0;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003534 }
3535
3536 /*
3537 * Do not remove this line as it makes sure all of our decisions
3538 * have been applied.
3539 */
Marek Vasut1273dd92015-07-12 21:05:08 +02003540 writel(0, &sdr_scc_mgr->update);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003541 return 1;
3542}
3543
Marek Vasut23a040c2015-07-17 01:20:21 +02003544/**
3545 * run_mem_calibrate() - Perform memory calibration
3546 *
3547 * This function triggers the entire memory calibration procedure.
3548 */
3549static int run_mem_calibrate(void)
Dinh Nguyen3da42852015-06-02 22:52:49 -05003550{
Marek Vasut23a040c2015-07-17 01:20:21 +02003551 int pass;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003552
3553 debug("%s:%d\n", __func__, __LINE__);
3554
3555 /* Reset pass/fail status shown on afi_cal_success/fail */
Marek Vasut1273dd92015-07-12 21:05:08 +02003556 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003557
Marek Vasut23a040c2015-07-17 01:20:21 +02003558 /* Stop tracking manager. */
3559 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003560
Marek Vasut9fa9c902015-07-17 01:12:07 +02003561 phy_mgr_initialize();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003562 rw_mgr_mem_initialize();
3563
Marek Vasut23a040c2015-07-17 01:20:21 +02003564 /* Perform the actual memory calibration. */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003565 pass = mem_calibrate();
3566
3567 mem_precharge_and_activate();
Marek Vasut1273dd92015-07-12 21:05:08 +02003568 writel(0, &phy_mgr_cmd->fifo_reset);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003569
Marek Vasut23a040c2015-07-17 01:20:21 +02003570 /* Handoff. */
3571 rw_mgr_mem_handoff();
Dinh Nguyen3da42852015-06-02 22:52:49 -05003572 /*
Marek Vasut23a040c2015-07-17 01:20:21 +02003573 * In Hard PHY this is a 2-bit control:
3574 * 0: AFI Mux Select
3575 * 1: DDIO Mux Select
Dinh Nguyen3da42852015-06-02 22:52:49 -05003576 */
Marek Vasut23a040c2015-07-17 01:20:21 +02003577 writel(0x2, &phy_mgr_cfg->mux_sel);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003578
Marek Vasut23a040c2015-07-17 01:20:21 +02003579 /* Start tracking manager. */
3580 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3581
3582 return pass;
3583}
3584
3585/**
3586 * debug_mem_calibrate() - Report result of memory calibration
3587 * @pass: Value indicating whether calibration passed or failed
3588 *
3589 * This function reports the results of the memory calibration
3590 * and writes debug information into the register file.
3591 */
3592static void debug_mem_calibrate(int pass)
3593{
3594 uint32_t debug_info;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003595
3596 if (pass) {
3597 printf("%s: CALIBRATION PASSED\n", __FILE__);
3598
3599 gbl->fom_in /= 2;
3600 gbl->fom_out /= 2;
3601
3602 if (gbl->fom_in > 0xff)
3603 gbl->fom_in = 0xff;
3604
3605 if (gbl->fom_out > 0xff)
3606 gbl->fom_out = 0xff;
3607
3608 /* Update the FOM in the register file */
3609 debug_info = gbl->fom_in;
3610 debug_info |= gbl->fom_out << 8;
Marek Vasut1273dd92015-07-12 21:05:08 +02003611 writel(debug_info, &sdr_reg_file->fom);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003612
Marek Vasut1273dd92015-07-12 21:05:08 +02003613 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3614 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003615 } else {
3616 printf("%s: CALIBRATION FAILED\n", __FILE__);
3617
3618 debug_info = gbl->error_stage;
3619 debug_info |= gbl->error_substage << 8;
3620 debug_info |= gbl->error_group << 16;
3621
Marek Vasut1273dd92015-07-12 21:05:08 +02003622 writel(debug_info, &sdr_reg_file->failing_stage);
3623 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3624 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003625
3626 /* Update the failing group/stage in the register file */
3627 debug_info = gbl->error_stage;
3628 debug_info |= gbl->error_substage << 8;
3629 debug_info |= gbl->error_group << 16;
Marek Vasut1273dd92015-07-12 21:05:08 +02003630 writel(debug_info, &sdr_reg_file->failing_stage);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003631 }
3632
Marek Vasut23a040c2015-07-17 01:20:21 +02003633 printf("%s: Calibration complete\n", __FILE__);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003634}
3635
Marek Vasutbb064342015-07-19 06:12:42 +02003636/**
3637 * hc_initialize_rom_data() - Initialize ROM data
3638 *
3639 * Initialize ROM data.
3640 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003641static void hc_initialize_rom_data(void)
3642{
Marek Vasutbb064342015-07-19 06:12:42 +02003643 u32 i, addr;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003644
Marek Vasutc4815f72015-07-12 19:03:33 +02003645 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
Marek Vasutbb064342015-07-19 06:12:42 +02003646 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3647 writel(inst_rom_init[i], addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003648
Marek Vasutc4815f72015-07-12 19:03:33 +02003649 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
Marek Vasutbb064342015-07-19 06:12:42 +02003650 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3651 writel(ac_rom_init[i], addr + (i << 2));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003652}
3653
Marek Vasut9c1ab2c2015-07-19 06:13:37 +02003654/**
3655 * initialize_reg_file() - Initialize SDR register file
3656 *
3657 * Initialize SDR register file.
3658 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003659static void initialize_reg_file(void)
3660{
Dinh Nguyen3da42852015-06-02 22:52:49 -05003661 /* Initialize the register file with the correct data */
Marek Vasut1273dd92015-07-12 21:05:08 +02003662 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3663 writel(0, &sdr_reg_file->debug_data_addr);
3664 writel(0, &sdr_reg_file->cur_stage);
3665 writel(0, &sdr_reg_file->fom);
3666 writel(0, &sdr_reg_file->failing_stage);
3667 writel(0, &sdr_reg_file->debug1);
3668 writel(0, &sdr_reg_file->debug2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003669}
3670
Marek Vasut2ca151f2015-07-19 06:14:04 +02003671/**
3672 * initialize_hps_phy() - Initialize HPS PHY
3673 *
3674 * Initialize HPS PHY.
3675 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003676static void initialize_hps_phy(void)
3677{
3678 uint32_t reg;
Dinh Nguyen3da42852015-06-02 22:52:49 -05003679 /*
3680 * Tracking also gets configured here because it's in the
3681 * same register.
3682 */
3683 uint32_t trk_sample_count = 7500;
3684 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3685 /*
3686 * Format is number of outer loops in the 16 MSB, sample
3687 * count in 16 LSB.
3688 */
3689
3690 reg = 0;
3691 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3692 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3693 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3694 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3695 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3696 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3697 /*
3698 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3699 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3700 */
3701 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3702 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3703 trk_sample_count);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003704 writel(reg, &sdr_ctrl->phy_ctrl0);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003705
3706 reg = 0;
3707 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3708 trk_sample_count >>
3709 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3710 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3711 trk_long_idle_sample_count);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003712 writel(reg, &sdr_ctrl->phy_ctrl1);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003713
3714 reg = 0;
3715 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3716 trk_long_idle_sample_count >>
3717 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
Marek Vasut6cb9f162015-07-12 20:49:39 +02003718 writel(reg, &sdr_ctrl->phy_ctrl2);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003719}
3720
Marek Vasut880e46f2015-07-17 00:45:11 +02003721/**
3722 * initialize_tracking() - Initialize tracking
3723 *
3724 * Initialize the register file with usable initial data.
3725 */
Dinh Nguyen3da42852015-06-02 22:52:49 -05003726static void initialize_tracking(void)
3727{
Marek Vasut880e46f2015-07-17 00:45:11 +02003728 /*
3729 * Initialize the register file with the correct data.
3730 * Compute usable version of value in case we skip full
3731 * computation later.
3732 */
3733 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3734 &sdr_reg_file->dtaps_per_ptap);
3735
3736 /* trk_sample_count */
3737 writel(7500, &sdr_reg_file->trk_sample_count);
3738
3739 /* longidle outer loop [15:0] */
3740 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003741
3742 /*
Marek Vasut880e46f2015-07-17 00:45:11 +02003743 * longidle sample count [31:24]
3744 * trfc, worst case of 933Mhz 4Gb [23:16]
3745 * trcd, worst case [15:8]
3746 * vfifo wait [7:0]
Dinh Nguyen3da42852015-06-02 22:52:49 -05003747 */
Marek Vasut880e46f2015-07-17 00:45:11 +02003748 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3749 &sdr_reg_file->delays);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003750
Marek Vasut880e46f2015-07-17 00:45:11 +02003751 /* mux delay */
3752 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3753 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3754 &sdr_reg_file->trk_rw_mgr_addr);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003755
Marek Vasut880e46f2015-07-17 00:45:11 +02003756 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3757 &sdr_reg_file->trk_read_dqs_width);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003758
Marek Vasut880e46f2015-07-17 00:45:11 +02003759 /* trefi [7:0] */
3760 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3761 &sdr_reg_file->trk_rfsh);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003762}
3763
3764int sdram_calibration_full(void)
3765{
3766 struct param_type my_param;
3767 struct gbl_type my_gbl;
3768 uint32_t pass;
Marek Vasut84e0b0c2015-07-17 01:05:36 +02003769
3770 memset(&my_param, 0, sizeof(my_param));
3771 memset(&my_gbl, 0, sizeof(my_gbl));
Dinh Nguyen3da42852015-06-02 22:52:49 -05003772
3773 param = &my_param;
3774 gbl = &my_gbl;
3775
Dinh Nguyen3da42852015-06-02 22:52:49 -05003776 /* Set the calibration enabled by default */
3777 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3778 /*
3779 * Only sweep all groups (regardless of fail state) by default
3780 * Set enabled read test by default.
3781 */
3782#if DISABLE_GUARANTEED_READ
3783 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3784#endif
3785 /* Initialize the register file */
3786 initialize_reg_file();
3787
3788 /* Initialize any PHY CSR */
3789 initialize_hps_phy();
3790
3791 scc_mgr_initialize();
3792
3793 initialize_tracking();
3794
Dinh Nguyen3da42852015-06-02 22:52:49 -05003795 printf("%s: Preparing to start memory calibration\n", __FILE__);
3796
3797 debug("%s:%d\n", __func__, __LINE__);
Marek Vasut23f62b32015-07-13 01:05:27 +02003798 debug_cond(DLEVEL == 1,
3799 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3800 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3801 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3802 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3803 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3804 debug_cond(DLEVEL == 1,
3805 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3806 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3807 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3808 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3809 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3810 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3811 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3812 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3813 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3814 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3815 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3816 IO_IO_OUT2_DELAY_MAX);
3817 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3818 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003819
3820 hc_initialize_rom_data();
3821
3822 /* update info for sims */
3823 reg_file_set_stage(CAL_STAGE_NIL);
3824 reg_file_set_group(0);
3825
3826 /*
3827 * Load global needed for those actions that require
3828 * some dynamic calibration support.
3829 */
3830 dyn_calib_steps = STATIC_CALIB_STEPS;
3831 /*
3832 * Load global to allow dynamic selection of delay loop settings
3833 * based on calibration mode.
3834 */
3835 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3836 skip_delay_mask = 0xff;
3837 else
3838 skip_delay_mask = 0x0;
3839
3840 pass = run_mem_calibrate();
Marek Vasut23a040c2015-07-17 01:20:21 +02003841 debug_mem_calibrate(pass);
Dinh Nguyen3da42852015-06-02 22:52:49 -05003842 return pass;
3843}