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Jens Scharsig98250e82010-02-03 22:47:35 +01001/*
2 * See file CREDITS for list of people who contributed to this
3 * project.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef __AT91RM9200_H__
22#define __AT91RM9200_H__
23
Andreas Bießmannd7033552011-06-12 01:49:13 +000024#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
25#define CONFIG_ARM920T /* it's an ARM920T Core */
Andreas Bießmann6a372e92011-06-12 01:49:12 +000026#define CONFIG_ARCH_CPU_INIT /* we need arch_cpu_init() for hw timers */
Andreas Bießmannd7033552011-06-12 01:49:13 +000027#define CONFIG_AT91_GPIO /* and require always gpio features */
Jens Scharsig80733992011-02-19 06:17:02 +000028
Jens Scharsig98250e82010-02-03 22:47:35 +010029/* Periperial Identifiers */
30
Jens Scharsig80733992011-02-19 06:17:02 +000031#define ATMEL_ID_SYS 1 /* System Peripheral */
32#define ATMEL_ID_PIOA 2 /* PIO port A */
33#define ATMEL_ID_PIOB 3 /* PIO port B */
34#define ATMEL_ID_PIOC 4 /* PIO port C */
35#define ATMEL_ID_PIOD 5 /* PIO port D BGA only */
36#define ATMEL_ID_USART0 6 /* USART 0 */
37#define ATMEL_ID_USART1 7 /* USART 1 */
38#define ATMEL_ID_USART2 8 /* USART 2 */
39#define ATMEL_ID_USART3 9 /* USART 3 */
40#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */
41#define ATMEL_ID_UDP 11 /* USB Device Port */
42#define ATMEL_ID_TWI 12 /* Two Wire Interface */
43#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */
44#define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */
45#define ATMEL_ID_SSC1 15 /* Synch. Serial Controller 1 */
46#define ATMEL_ID_SSC2 16 /* Synch. Serial Controller 2 */
47#define ATMEL_ID_TC0 17 /* Timer Counter 0 */
48#define ATMEL_ID_TC1 18 /* Timer Counter 1 */
49#define ATMEL_ID_TC2 19 /* Timer Counter 2 */
50#define ATMEL_ID_TC3 20 /* Timer Counter 3 */
51#define ATMEL_ID_TC4 21 /* Timer Counter 4 */
52#define ATMEL_ID_TC5 22 /* Timer Counter 5 */
53#define ATMEL_ID_UHP 23 /* OHCI USB Host Port */
54#define ATMEL_ID_EMAC 24 /* Ethernet MAC */
55#define ATMEL_ID_IRQ0 25 /* Advanced Interrupt Controller */
56#define ATMEL_ID_IRQ1 26 /* Advanced Interrupt Controller */
57#define ATMEL_ID_IRQ2 27 /* Advanced Interrupt Controller */
58#define ATMEL_ID_IRQ3 28 /* Advanced Interrupt Controller */
59#define ATMEL_ID_IRQ4 29 /* Advanced Interrupt Controller */
60#define ATMEL_ID_IRQ5 30 /* Advanced Interrupt Controller */
61#define ATMEL_ID_IRQ6 31 /* Advanced Interrupt Controller */
Jens Scharsig98250e82010-02-03 22:47:35 +010062
Jens Scharsig80733992011-02-19 06:17:02 +000063#define ATMEL_USB_HOST_BASE 0x00300000
Jens Scharsig98250e82010-02-03 22:47:35 +010064
Jens Scharsig80733992011-02-19 06:17:02 +000065#define ATMEL_BASE_TC 0xFFFA0000
66#define ATMEL_BASE_UDP 0xFFFB0000
67#define ATMEL_BASE_MCI 0xFFFB4000
68#define ATMEL_BASE_TWI 0xFFFB8000
69#define ATMEL_BASE_EMAC 0xFFFBC000
70#define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */
71#define ATMEL_BASE_USART0 ATMEL_BASE_USART
72#define ATMEL_BASE_USART1 (ATMEL_BASE_USART + 0x4000)
73#define ATMEL_BASE_USART2 (ATMEL_BASE_USART + 0x8000)
74#define ATMEL_BASE_USART3 (ATMEL_BASE_USART + 0xC000)
Jens Scharsig98250e82010-02-03 22:47:35 +010075
Jens Scharsig80733992011-02-19 06:17:02 +000076#define ATMEL_BASE_SCC 0xFFFD0000 /* 4x 0x4000 Offset */
77#define ATMEL_BASE_SPI 0xFFFE0000
Jens Scharsig98250e82010-02-03 22:47:35 +010078
Jens Scharsig80733992011-02-19 06:17:02 +000079#define ATMEL_BASE_AIC 0xFFFFF000
80#define ATMEL_BASE_DBGU 0xFFFFF200
81#define ATMEL_BASE_PIO 0xFFFFF400 /* 4x 0x200 Offset */
Andreas Bießmannd7033552011-06-12 01:49:13 +000082#define ATMEL_BASE_PIOA 0xFFFFF400
83#define ATMEL_BASE_PIOB 0xFFFFF600
84#define ATMEL_BASE_PIOC 0xFFFFF800
85#define ATMEL_BASE_PIOD 0xFFFFFA00
Jens Scharsig80733992011-02-19 06:17:02 +000086#define ATMEL_BASE_PMC 0xFFFFFC00
87#define ATMEL_BASE_ST 0xFFFFFD00
88#define ATMEL_BASE_RTC 0xFFFFFE00
89#define ATMEL_BASE_MC 0xFFFFFF00
90
91#define AT91_PIO_BASE ATMEL_BASE_PIO
Jens Scharsig98250e82010-02-03 22:47:35 +010092
93/* AT91RM9200 Periperial Multiplexing A */
94/* Port A */
Jens Scharsig80733992011-02-19 06:17:02 +000095#define ATMEL_PMX_AA_EREFCK 0x00000080
96#define ATMEL_PMX_AA_ETXCK 0x00000080
97#define ATMEL_PMX_AA_ETXEN 0x00000100
98#define ATMEL_PMX_AA_ETX0 0x00000200
99#define ATMEL_PMX_AA_ETX1 0x00000400
100#define ATMEL_PMX_AA_ECRS 0x00000800
101#define ATMEL_PMX_AA_ECRSDV 0x00000800
102#define ATMEL_PMX_AA_ERX0 0x00001000
103#define ATMEL_PMX_AA_ERX1 0x00002000
104#define ATMEL_PMX_AA_ERXER 0x00004000
105#define ATMEL_PMX_AA_EMDC 0x00008000
106#define ATMEL_PMX_AA_EMDIO 0x00010000
Jens Scharsig98250e82010-02-03 22:47:35 +0100107
Andreas Bießmann876ef432011-06-12 01:25:16 +0000108#define ATMEL_PMX_AA_TXD2 0x00800000
Jens Scharsig98250e82010-02-03 22:47:35 +0100109
Jens Scharsig80733992011-02-19 06:17:02 +0000110#define ATMEL_PMX_AA_TWD 0x02000000
111#define ATMEL_PMX_AA_TWCK 0x04000000
Jens Scharsig98250e82010-02-03 22:47:35 +0100112
113/* Port B */
Jens Scharsig80733992011-02-19 06:17:02 +0000114#define ATMEL_PMX_BA_ERXCK 0x00080000
115#define ATMEL_PMX_BA_ECOL 0x00040000
116#define ATMEL_PMX_BA_ERXDV 0x00020000
117#define ATMEL_PMX_BA_ERX3 0x00010000
118#define ATMEL_PMX_BA_ERX2 0x00008000
119#define ATMEL_PMX_BA_ETXER 0x00004000
120#define ATMEL_PMX_BA_ETX3 0x00002000
121#define ATMEL_PMX_BA_ETX2 0x00001000
Jens Scharsig98250e82010-02-03 22:47:35 +0100122
123/* Port B */
124
Jens Scharsig80733992011-02-19 06:17:02 +0000125#define ATMEL_PMX_CA_BFCK 0x00000001
126#define ATMEL_PMX_CA_BFRDY 0x00000002
127#define ATMEL_PMX_CA_SMOE 0x00000002
128#define ATMEL_PMX_CA_BFAVD 0x00000004
129#define ATMEL_PMX_CA_BFBAA 0x00000008
130#define ATMEL_PMX_CA_SMWE 0x00000008
131#define ATMEL_PMX_CA_BFOE 0x00000010
132#define ATMEL_PMX_CA_BFWE 0x00000020
133#define ATMEL_PMX_CA_NWAIT 0x00000040
134#define ATMEL_PMX_CA_A23 0x00000080
135#define ATMEL_PMX_CA_A24 0x00000100
136#define ATMEL_PMX_CA_A25 0x00000200
137#define ATMEL_PMX_CA_CFRNW 0x00000200
138#define ATMEL_PMX_CA_NCS4 0x00000400
139#define ATMEL_PMX_CA_CFCS 0x00000400
140#define ATMEL_PMX_CA_NCS5 0x00000800
141#define ATMEL_PMX_CA_CFCE1 0x00001000
142#define ATMEL_PMX_CA_NCS6 0x00001000
143#define ATMEL_PMX_CA_CFCE2 0x00002000
144#define ATMEL_PMX_CA_NCS7 0x00002000
145#define ATMEL_PMX_CA_D16_31 0xFFFF0000
Jens Scharsig98250e82010-02-03 22:47:35 +0100146
Jens Scharsig80733992011-02-19 06:17:02 +0000147#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */
148#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP
149
150#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200"
Jens Scharsig98250e82010-02-03 22:47:35 +0100151
152#endif