| commit | d94c2dbd0a55d742ab6ed9bd0c51b27ceed4084e | [log] [tgz] |
|---|---|---|
| author | Tom Warren <twarren@nvidia.com> | Wed Apr 03 14:39:30 2013 -0700 |
| committer | Tom Warren <twarren@nvidia.com> | Mon Apr 15 11:01:38 2013 -0700 |
| tree | 5bdef44cb41f3818fec6d5741654bba1348ef19a | |
| parent | b40f734af9fdc47a0993f1f94f32d40a86f30587 [diff] |
Tegra: Fix MSELECT clock divisors for T30/T114. A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>