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wdenk12f34242003-09-02 22:48:03 +00001/*
wdenk180d3f72004-01-04 16:28:35 +00002 * (C) Copyright 2003
3 * DAVE Srl
4 * http://www.dave-tech.it
5 * http://www.wawnet.biz
6 * mailto:info@wawnet.biz
wdenk12f34242003-09-02 22:48:03 +00007 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk12f34242003-09-02 22:48:03 +00009 */
10
11#include <common.h>
12#include <asm/processor.h>
13#include <command.h>
14#include <malloc.h>
15
Wolfgang Denkd87080b2006-03-31 18:32:53 +020016DECLARE_GLOBAL_DATA_PTR;
17
wdenk12f34242003-09-02 22:48:03 +000018/* ------------------------------------------------------------------------- */
19
wdenkc837dcb2004-01-20 23:12:12 +000020int board_early_init_f (void)
wdenk12f34242003-09-02 22:48:03 +000021{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022 out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
23 out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
wdenk12f34242003-09-02 22:48:03 +000024
25 /*
26 * IRQ 0-15 405GP internally generated; active high; level sensitive
27 * IRQ 16 405GP internally generated; active low; level sensitive
28 * IRQ 17-24 RESERVED
wdenke55ca7e2004-07-01 21:40:08 +000029 * IRQ 25 (EXT IRQ 0)
30 * IRQ 26 (EXT IRQ 1)
31 * IRQ 27 (EXT IRQ 2)
32 * IRQ 28 (EXT IRQ 3)
33 * IRQ 29 (EXT IRQ 4)
34 * IRQ 30 (EXT IRQ 5)
35 * IRQ 31 (EXT IRQ 6)
wdenk12f34242003-09-02 22:48:03 +000036 */
Stefan Roese952e7762009-09-24 09:55:50 +020037 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
38 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
39 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
40 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
41 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
42 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
43 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
wdenk12f34242003-09-02 22:48:03 +000044
45 /*
46 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
47 */
48#if 1 /* test-only */
Stefan Roesed1c3b272009-09-09 16:25:29 +020049 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
wdenk12f34242003-09-02 22:48:03 +000050#else
Stefan Roesed1c3b272009-09-09 16:25:29 +020051 mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
wdenk12f34242003-09-02 22:48:03 +000052#endif
wdenk12f34242003-09-02 22:48:03 +000053 return 0;
54}
55
wdenk12f34242003-09-02 22:48:03 +000056/* ------------------------------------------------------------------------- */
57
58int misc_init_f (void)
59{
60 return 0; /* dummy implementation */
61}
62
wdenk46a414d2004-06-17 18:50:45 +000063extern flash_info_t flash_info[]; /* info for FLASH chips */
wdenk12f34242003-09-02 22:48:03 +000064
65int misc_init_r (void)
66{
wdenk46a414d2004-06-17 18:50:45 +000067 /* adjust flash start and size as well as the offset */
68 gd->bd->bi_flashstart = 0 - flash_info[0].size;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069 gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
wdenk12f34242003-09-02 22:48:03 +000070#if 0
71 volatile unsigned short *fpga_mode =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
wdenk12f34242003-09-02 22:48:03 +000073 volatile unsigned char *duart0_mcr =
74 (unsigned char *)((ulong)DUART0_BA + 4);
75 volatile unsigned char *duart1_mcr =
76 (unsigned char *)((ulong)DUART1_BA + 4);
77
78 bd_t *bd = gd->bd;
79 char * tmp; /* Temporary char pointer */
80 unsigned char *dst;
81 ulong len = sizeof(fpgadata);
82 int status;
83 int index;
84 int i;
Stefan Roesed1c3b272009-09-09 16:25:29 +020085 unsigned long CPC0_CR0Reg;
wdenk12f34242003-09-02 22:48:03 +000086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
88 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
wdenk12f34242003-09-02 22:48:03 +000089 printf ("GUNZIP ERROR - must RESET board to recover\n");
90 do_reset (NULL, 0, 0, NULL);
91 }
92
93 status = fpga_boot(dst, len);
94 if (status != 0) {
95 printf("\nFPGA: Booting failed ");
96 switch (status) {
97 case ERROR_FPGA_PRG_INIT_LOW:
98 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
99 break;
100 case ERROR_FPGA_PRG_INIT_HIGH:
101 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
102 break;
103 case ERROR_FPGA_PRG_DONE:
104 printf("(Timeout: DONE not high after programming FPGA)\n ");
105 break;
106 }
107
108 /* display infos on fpgaimage */
109 index = 15;
110 for (i=0; i<4; i++) {
111 len = dst[index];
112 printf("FPGA: %s\n", &(dst[index+1]));
113 index += len+3;
114 }
115 putc ('\n');
116 /* delayed reboot */
117 for (i=20; i>0; i--) {
118 printf("Rebooting in %2d seconds \r",i);
119 for (index=0;index<1000;index++)
120 udelay(1000);
121 }
122 putc ('\n');
123 do_reset(NULL, 0, 0, NULL);
124 }
125
126 puts("FPGA: ");
127
128 /* display infos on fpgaimage */
129 index = 15;
130 for (i=0; i<4; i++) {
131 len = dst[index];
132 printf("%s ", &(dst[index+1]));
133 index += len+3;
134 }
135 putc ('\n');
136
137 free(dst);
138
139 /*
140 * Reset FPGA via FPGA_DATA pin
141 */
142 SET_FPGA(FPGA_PRG | FPGA_CLK);
143 udelay(1000); /* wait 1ms */
144 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
145 udelay(1000); /* wait 1ms */
wdenk12f34242003-09-02 22:48:03 +0000146#endif
147
148#if 0
149 /*
150 * Enable power on PS/2 interface
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
wdenk12f34242003-09-02 22:48:03 +0000153
154 /*
155 * Enable interrupts in exar duart mcr[3]
156 */
157 *duart0_mcr = 0x08;
158 *duart1_mcr = 0x08;
159#endif
wdenk12f34242003-09-02 22:48:03 +0000160 return (0);
161}
162
wdenk12f34242003-09-02 22:48:03 +0000163/*
164 * Check Board Identity:
165 */
166
167int checkboard (void)
168{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200169 char str[64];
Wolfgang Denkcdb74972010-07-24 21:55:43 +0200170 int i = getenv_f("serial#", str, sizeof(str));
wdenk12f34242003-09-02 22:48:03 +0000171
172 puts ("Board: ");
173
174 if (i == -1) {
175 puts ("### No HW ID - assuming PPChameleonEVB");
176 } else {
177 puts(str);
178 }
179
180 putc ('\n');
181
182 return 0;
183}
184
185/* ------------------------------------------------------------------------- */
186
wdenk12f34242003-09-02 22:48:03 +0000187int testdram (void)
188{
189 /* TODO: XXX XXX XXX */
190 printf ("test: 16 MB - ok\n");
191
192 return (0);
193}
194
195/* ------------------------------------------------------------------------- */
196
wdenke55ca7e2004-07-01 21:40:08 +0000197#ifdef CONFIG_CFB_CONSOLE
198# ifdef CONFIG_CONSOLE_EXTRA_INFO
199# include <video_fb.h>
200extern GraphicDevice smi;
201
202void video_get_info_str (int line_number, char *info)
203{
204 uint pvr = get_pvr ();
205
206 /* init video info strings for graphic console */
207 switch (line_number) {
208 case 1:
209 switch (pvr) {
210 case PVR_405EP_RB:
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200211 sprintf (info, " AMCC PowerPC 405EP Rev. B");
wdenke55ca7e2004-07-01 21:40:08 +0000212 break;
213 default:
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200214 sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
wdenke55ca7e2004-07-01 21:40:08 +0000215 break;
216 }
217 return;
218 case 2:
219 sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
220 return;
221 case 3:
222 sprintf (info, " %s", smi.modeIdent);
223 return;
224 }
225
226 /* no more info lines */
227 *info = 0;
228 return;
229}
230# endif /* CONFIG_CONSOLE_EXTRA_INFO */
231#endif /* CONFIG_CFB_CONSOLE */