wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 1 | /* |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 2 | * (C) Copyright 2003 |
| 3 | * DAVE Srl |
| 4 | * http://www.dave-tech.it |
| 5 | * http://www.wawnet.biz |
| 6 | * mailto:info@wawnet.biz |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 7 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <asm/processor.h> |
| 13 | #include <command.h> |
| 14 | #include <malloc.h> |
| 15 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 18 | /* ------------------------------------------------------------------------- */ |
| 19 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 20 | int board_early_init_f (void) |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 21 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 22 | out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */ |
| 23 | out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */ |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * IRQ 0-15 405GP internally generated; active high; level sensitive |
| 27 | * IRQ 16 405GP internally generated; active low; level sensitive |
| 28 | * IRQ 17-24 RESERVED |
wdenk | e55ca7e | 2004-07-01 21:40:08 +0000 | [diff] [blame] | 29 | * IRQ 25 (EXT IRQ 0) |
| 30 | * IRQ 26 (EXT IRQ 1) |
| 31 | * IRQ 27 (EXT IRQ 2) |
| 32 | * IRQ 28 (EXT IRQ 3) |
| 33 | * IRQ 29 (EXT IRQ 4) |
| 34 | * IRQ 30 (EXT IRQ 5) |
| 35 | * IRQ 31 (EXT IRQ 6) |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 36 | */ |
Stefan Roese | 952e776 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 37 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
| 38 | mtdcr(UIC0ER, 0x00000000); /* disable all ints */ |
| 39 | mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ |
| 40 | mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ |
| 41 | mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ |
| 42 | mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
| 43 | mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
| 47 | */ |
| 48 | #if 1 /* test-only */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 49 | mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 50 | #else |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 51 | mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */ |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 52 | #endif |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 53 | return 0; |
| 54 | } |
| 55 | |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 56 | /* ------------------------------------------------------------------------- */ |
| 57 | |
| 58 | int misc_init_f (void) |
| 59 | { |
| 60 | return 0; /* dummy implementation */ |
| 61 | } |
| 62 | |
wdenk | 46a414d | 2004-06-17 18:50:45 +0000 | [diff] [blame] | 63 | extern flash_info_t flash_info[]; /* info for FLASH chips */ |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 64 | |
| 65 | int misc_init_r (void) |
| 66 | { |
wdenk | 46a414d | 2004-06-17 18:50:45 +0000 | [diff] [blame] | 67 | /* adjust flash start and size as well as the offset */ |
| 68 | gd->bd->bi_flashstart = 0 - flash_info[0].size; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN; |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 70 | #if 0 |
| 71 | volatile unsigned short *fpga_mode = |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 73 | volatile unsigned char *duart0_mcr = |
| 74 | (unsigned char *)((ulong)DUART0_BA + 4); |
| 75 | volatile unsigned char *duart1_mcr = |
| 76 | (unsigned char *)((ulong)DUART1_BA + 4); |
| 77 | |
| 78 | bd_t *bd = gd->bd; |
| 79 | char * tmp; /* Temporary char pointer */ |
| 80 | unsigned char *dst; |
| 81 | ulong len = sizeof(fpgadata); |
| 82 | int status; |
| 83 | int index; |
| 84 | int i; |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 85 | unsigned long CPC0_CR0Reg; |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 86 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
| 88 | if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 89 | printf ("GUNZIP ERROR - must RESET board to recover\n"); |
| 90 | do_reset (NULL, 0, 0, NULL); |
| 91 | } |
| 92 | |
| 93 | status = fpga_boot(dst, len); |
| 94 | if (status != 0) { |
| 95 | printf("\nFPGA: Booting failed "); |
| 96 | switch (status) { |
| 97 | case ERROR_FPGA_PRG_INIT_LOW: |
| 98 | printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
| 99 | break; |
| 100 | case ERROR_FPGA_PRG_INIT_HIGH: |
| 101 | printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
| 102 | break; |
| 103 | case ERROR_FPGA_PRG_DONE: |
| 104 | printf("(Timeout: DONE not high after programming FPGA)\n "); |
| 105 | break; |
| 106 | } |
| 107 | |
| 108 | /* display infos on fpgaimage */ |
| 109 | index = 15; |
| 110 | for (i=0; i<4; i++) { |
| 111 | len = dst[index]; |
| 112 | printf("FPGA: %s\n", &(dst[index+1])); |
| 113 | index += len+3; |
| 114 | } |
| 115 | putc ('\n'); |
| 116 | /* delayed reboot */ |
| 117 | for (i=20; i>0; i--) { |
| 118 | printf("Rebooting in %2d seconds \r",i); |
| 119 | for (index=0;index<1000;index++) |
| 120 | udelay(1000); |
| 121 | } |
| 122 | putc ('\n'); |
| 123 | do_reset(NULL, 0, 0, NULL); |
| 124 | } |
| 125 | |
| 126 | puts("FPGA: "); |
| 127 | |
| 128 | /* display infos on fpgaimage */ |
| 129 | index = 15; |
| 130 | for (i=0; i<4; i++) { |
| 131 | len = dst[index]; |
| 132 | printf("%s ", &(dst[index+1])); |
| 133 | index += len+3; |
| 134 | } |
| 135 | putc ('\n'); |
| 136 | |
| 137 | free(dst); |
| 138 | |
| 139 | /* |
| 140 | * Reset FPGA via FPGA_DATA pin |
| 141 | */ |
| 142 | SET_FPGA(FPGA_PRG | FPGA_CLK); |
| 143 | udelay(1000); /* wait 1ms */ |
| 144 | SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); |
| 145 | udelay(1000); /* wait 1ms */ |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 146 | #endif |
| 147 | |
| 148 | #if 0 |
| 149 | /* |
| 150 | * Enable power on PS/2 interface |
| 151 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET; |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * Enable interrupts in exar duart mcr[3] |
| 156 | */ |
| 157 | *duart0_mcr = 0x08; |
| 158 | *duart1_mcr = 0x08; |
| 159 | #endif |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 160 | return (0); |
| 161 | } |
| 162 | |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 163 | /* |
| 164 | * Check Board Identity: |
| 165 | */ |
| 166 | |
| 167 | int checkboard (void) |
| 168 | { |
Wolfgang Denk | 77ddac9 | 2005-10-13 16:45:02 +0200 | [diff] [blame] | 169 | char str[64]; |
Wolfgang Denk | cdb7497 | 2010-07-24 21:55:43 +0200 | [diff] [blame] | 170 | int i = getenv_f("serial#", str, sizeof(str)); |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 171 | |
| 172 | puts ("Board: "); |
| 173 | |
| 174 | if (i == -1) { |
| 175 | puts ("### No HW ID - assuming PPChameleonEVB"); |
| 176 | } else { |
| 177 | puts(str); |
| 178 | } |
| 179 | |
| 180 | putc ('\n'); |
| 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
| 185 | /* ------------------------------------------------------------------------- */ |
| 186 | |
wdenk | 12f3424 | 2003-09-02 22:48:03 +0000 | [diff] [blame] | 187 | int testdram (void) |
| 188 | { |
| 189 | /* TODO: XXX XXX XXX */ |
| 190 | printf ("test: 16 MB - ok\n"); |
| 191 | |
| 192 | return (0); |
| 193 | } |
| 194 | |
| 195 | /* ------------------------------------------------------------------------- */ |
| 196 | |
wdenk | e55ca7e | 2004-07-01 21:40:08 +0000 | [diff] [blame] | 197 | #ifdef CONFIG_CFB_CONSOLE |
| 198 | # ifdef CONFIG_CONSOLE_EXTRA_INFO |
| 199 | # include <video_fb.h> |
| 200 | extern GraphicDevice smi; |
| 201 | |
| 202 | void video_get_info_str (int line_number, char *info) |
| 203 | { |
| 204 | uint pvr = get_pvr (); |
| 205 | |
| 206 | /* init video info strings for graphic console */ |
| 207 | switch (line_number) { |
| 208 | case 1: |
| 209 | switch (pvr) { |
| 210 | case PVR_405EP_RB: |
Wolfgang Denk | 0c8721a | 2005-09-23 11:05:55 +0200 | [diff] [blame] | 211 | sprintf (info, " AMCC PowerPC 405EP Rev. B"); |
wdenk | e55ca7e | 2004-07-01 21:40:08 +0000 | [diff] [blame] | 212 | break; |
| 213 | default: |
Wolfgang Denk | 0c8721a | 2005-09-23 11:05:55 +0200 | [diff] [blame] | 214 | sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>"); |
wdenk | e55ca7e | 2004-07-01 21:40:08 +0000 | [diff] [blame] | 215 | break; |
| 216 | } |
| 217 | return; |
| 218 | case 2: |
| 219 | sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it"); |
| 220 | return; |
| 221 | case 3: |
| 222 | sprintf (info, " %s", smi.modeIdent); |
| 223 | return; |
| 224 | } |
| 225 | |
| 226 | /* no more info lines */ |
| 227 | *info = 0; |
| 228 | return; |
| 229 | } |
| 230 | # endif /* CONFIG_CONSOLE_EXTRA_INFO */ |
| 231 | #endif /* CONFIG_CFB_CONSOLE */ |