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wdenk12f34242003-09-02 22:48:03 +00001/*
wdenk180d3f72004-01-04 16:28:35 +00002 * (C) Copyright 2003
3 * DAVE Srl
4 * http://www.dave-tech.it
5 * http://www.wawnet.biz
6 * mailto:info@wawnet.biz
wdenk12f34242003-09-02 22:48:03 +00007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <asm/processor.h>
29#include <command.h>
30#include <malloc.h>
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
wdenk12f34242003-09-02 22:48:03 +000034/* ------------------------------------------------------------------------- */
35
wdenk12f34242003-09-02 22:48:03 +000036/* Prototypes */
wdenkeedcd072004-09-08 22:03:11 +000037int gunzip(void *, int, unsigned char *, unsigned long *);
wdenk12f34242003-09-02 22:48:03 +000038
wdenkc837dcb2004-01-20 23:12:12 +000039int board_early_init_f (void)
wdenk12f34242003-09-02 22:48:03 +000040{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
42 out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
wdenk12f34242003-09-02 22:48:03 +000043
44 /*
45 * IRQ 0-15 405GP internally generated; active high; level sensitive
46 * IRQ 16 405GP internally generated; active low; level sensitive
47 * IRQ 17-24 RESERVED
wdenke55ca7e2004-07-01 21:40:08 +000048 * IRQ 25 (EXT IRQ 0)
49 * IRQ 26 (EXT IRQ 1)
50 * IRQ 27 (EXT IRQ 2)
51 * IRQ 28 (EXT IRQ 3)
52 * IRQ 29 (EXT IRQ 4)
53 * IRQ 30 (EXT IRQ 5)
54 * IRQ 31 (EXT IRQ 6)
wdenk12f34242003-09-02 22:48:03 +000055 */
56 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
57 mtdcr(uicer, 0x00000000); /* disable all ints */
58 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
wdenk4654af22003-10-22 09:00:28 +000059 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
wdenk12f34242003-09-02 22:48:03 +000060 mtdcr(uictr, 0x10000000); /* set int trigger levels */
61 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
62 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
63
64 /*
65 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
66 */
67#if 1 /* test-only */
Stefan Roesed1c3b272009-09-09 16:25:29 +020068 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
wdenk12f34242003-09-02 22:48:03 +000069#else
Stefan Roesed1c3b272009-09-09 16:25:29 +020070 mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
wdenk12f34242003-09-02 22:48:03 +000071#endif
wdenk12f34242003-09-02 22:48:03 +000072 return 0;
73}
74
wdenk12f34242003-09-02 22:48:03 +000075/* ------------------------------------------------------------------------- */
76
77int misc_init_f (void)
78{
79 return 0; /* dummy implementation */
80}
81
wdenk46a414d2004-06-17 18:50:45 +000082extern flash_info_t flash_info[]; /* info for FLASH chips */
wdenk12f34242003-09-02 22:48:03 +000083
84int misc_init_r (void)
85{
wdenk46a414d2004-06-17 18:50:45 +000086 /* adjust flash start and size as well as the offset */
87 gd->bd->bi_flashstart = 0 - flash_info[0].size;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088 gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
wdenk12f34242003-09-02 22:48:03 +000089#if 0
90 volatile unsigned short *fpga_mode =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
wdenk12f34242003-09-02 22:48:03 +000092 volatile unsigned char *duart0_mcr =
93 (unsigned char *)((ulong)DUART0_BA + 4);
94 volatile unsigned char *duart1_mcr =
95 (unsigned char *)((ulong)DUART1_BA + 4);
96
97 bd_t *bd = gd->bd;
98 char * tmp; /* Temporary char pointer */
99 unsigned char *dst;
100 ulong len = sizeof(fpgadata);
101 int status;
102 int index;
103 int i;
Stefan Roesed1c3b272009-09-09 16:25:29 +0200104 unsigned long CPC0_CR0Reg;
wdenk12f34242003-09-02 22:48:03 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
107 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
wdenk12f34242003-09-02 22:48:03 +0000108 printf ("GUNZIP ERROR - must RESET board to recover\n");
109 do_reset (NULL, 0, 0, NULL);
110 }
111
112 status = fpga_boot(dst, len);
113 if (status != 0) {
114 printf("\nFPGA: Booting failed ");
115 switch (status) {
116 case ERROR_FPGA_PRG_INIT_LOW:
117 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
118 break;
119 case ERROR_FPGA_PRG_INIT_HIGH:
120 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
121 break;
122 case ERROR_FPGA_PRG_DONE:
123 printf("(Timeout: DONE not high after programming FPGA)\n ");
124 break;
125 }
126
127 /* display infos on fpgaimage */
128 index = 15;
129 for (i=0; i<4; i++) {
130 len = dst[index];
131 printf("FPGA: %s\n", &(dst[index+1]));
132 index += len+3;
133 }
134 putc ('\n');
135 /* delayed reboot */
136 for (i=20; i>0; i--) {
137 printf("Rebooting in %2d seconds \r",i);
138 for (index=0;index<1000;index++)
139 udelay(1000);
140 }
141 putc ('\n');
142 do_reset(NULL, 0, 0, NULL);
143 }
144
145 puts("FPGA: ");
146
147 /* display infos on fpgaimage */
148 index = 15;
149 for (i=0; i<4; i++) {
150 len = dst[index];
151 printf("%s ", &(dst[index+1]));
152 index += len+3;
153 }
154 putc ('\n');
155
156 free(dst);
157
158 /*
159 * Reset FPGA via FPGA_DATA pin
160 */
161 SET_FPGA(FPGA_PRG | FPGA_CLK);
162 udelay(1000); /* wait 1ms */
163 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
164 udelay(1000); /* wait 1ms */
wdenk12f34242003-09-02 22:48:03 +0000165#endif
166
167#if 0
168 /*
169 * Enable power on PS/2 interface
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
wdenk12f34242003-09-02 22:48:03 +0000172
173 /*
174 * Enable interrupts in exar duart mcr[3]
175 */
176 *duart0_mcr = 0x08;
177 *duart1_mcr = 0x08;
178#endif
wdenk12f34242003-09-02 22:48:03 +0000179 return (0);
180}
181
wdenk12f34242003-09-02 22:48:03 +0000182/*
183 * Check Board Identity:
184 */
185
186int checkboard (void)
187{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200188 char str[64];
wdenk12f34242003-09-02 22:48:03 +0000189 int i = getenv_r ("serial#", str, sizeof(str));
190
191 puts ("Board: ");
192
193 if (i == -1) {
194 puts ("### No HW ID - assuming PPChameleonEVB");
195 } else {
196 puts(str);
197 }
198
199 putc ('\n');
200
201 return 0;
202}
203
204/* ------------------------------------------------------------------------- */
205
wdenk12f34242003-09-02 22:48:03 +0000206int testdram (void)
207{
208 /* TODO: XXX XXX XXX */
209 printf ("test: 16 MB - ok\n");
210
211 return (0);
212}
213
214/* ------------------------------------------------------------------------- */
215
wdenke55ca7e2004-07-01 21:40:08 +0000216#ifdef CONFIG_CFB_CONSOLE
217# ifdef CONFIG_CONSOLE_EXTRA_INFO
218# include <video_fb.h>
219extern GraphicDevice smi;
220
221void video_get_info_str (int line_number, char *info)
222{
223 uint pvr = get_pvr ();
224
225 /* init video info strings for graphic console */
226 switch (line_number) {
227 case 1:
228 switch (pvr) {
229 case PVR_405EP_RB:
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200230 sprintf (info, " AMCC PowerPC 405EP Rev. B");
wdenke55ca7e2004-07-01 21:40:08 +0000231 break;
232 default:
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200233 sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
wdenke55ca7e2004-07-01 21:40:08 +0000234 break;
235 }
236 return;
237 case 2:
238 sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
239 return;
240 case 3:
241 sprintf (info, " %s", smi.modeIdent);
242 return;
243 }
244
245 /* no more info lines */
246 *info = 0;
247 return;
248}
249# endif /* CONFIG_CONSOLE_EXTRA_INFO */
250#endif /* CONFIG_CFB_CONSOLE */