blob: febfbcef532614600db62070a9017c79b8813c8e [file] [log] [blame]
Dave Liu7737d5c2006-11-03 12:11:15 -06001/*
Haiying Wange8efef72009-06-04 16:12:42 -04002 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
Dave Liu7737d5c2006-11-03 12:11:15 -06003 *
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __UEC_H__
24#define __UEC_H__
25
Anton Vorontsovd77c7792009-09-16 23:21:55 +040026#include "qe.h"
27#include "uccf.h"
28
Dave Liu7737d5c2006-11-03 12:11:15 -060029#define MAX_TX_THREADS 8
30#define MAX_RX_THREADS 8
31#define MAX_TX_QUEUES 8
32#define MAX_RX_QUEUES 8
33#define MAX_PREFETCHED_BDS 4
34#define MAX_IPH_OFFSET_ENTRY 8
35#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
36#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
37
38/* UEC UPSMR (Protocol Specific Mode Register)
39 */
40#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
41#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
42#define UPSMR_PRO 0x00400000 /* Promiscuous */
43#define UPSMR_CAP 0x00200000 /* CAM polarity */
44#define UPSMR_RSH 0x00100000 /* Receive Short Frames */
45#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
46#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
47#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
48#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
49#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
50#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
51#define UPSMR_BRO 0x00000200 /* Broadcast Address */
52#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
Haiying Wange8efef72009-06-04 16:12:42 -040053#define UPSMR_SGMM 0x00000020 /* SGMII mode */
Dave Liu7737d5c2006-11-03 12:11:15 -060054
55#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
56
57/* UEC MACCFG1 (MAC Configuration 1 Register)
58 */
59#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
60#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
61#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
62#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
63#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
64#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
65
66#define MACCFG1_INIT_VALUE (0)
67
68/* UEC MACCFG2 (MAC Configuration 2 Register)
69 */
70#define MACCFG2_PREL 0x00007000
71#define MACCFG2_PREL_SHIFT (31 - 19)
72#define MACCFG2_PREL_MASK 0x0000f000
73#define MACCFG2_SRP 0x00000080
74#define MACCFG2_STP 0x00000040
75#define MACCFG2_RESERVED_1 0x00000020 /* must be set */
76#define MACCFG2_LC 0x00000010 /* Length Check */
77#define MACCFG2_MPE 0x00000008
78#define MACCFG2_FDX 0x00000001 /* Full Duplex */
79#define MACCFG2_FDX_MASK 0x00000001
80#define MACCFG2_PAD_CRC 0x00000004
81#define MACCFG2_CRC_EN 0x00000002
82#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
83#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
84#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
85#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
86#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
87#define MACCFG2_INTERFACE_MODE_MASK 0x00000300
88
89#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
90 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
91
92/* UEC Event Register
93*/
94#define UCCE_MPD 0x80000000
95#define UCCE_SCAR 0x40000000
96#define UCCE_GRA 0x20000000
97#define UCCE_CBPR 0x10000000
98#define UCCE_BSY 0x08000000
99#define UCCE_RXC 0x04000000
100#define UCCE_TXC 0x02000000
101#define UCCE_TXE 0x01000000
102#define UCCE_TXB7 0x00800000
103#define UCCE_TXB6 0x00400000
104#define UCCE_TXB5 0x00200000
105#define UCCE_TXB4 0x00100000
106#define UCCE_TXB3 0x00080000
107#define UCCE_TXB2 0x00040000
108#define UCCE_TXB1 0x00020000
109#define UCCE_TXB0 0x00010000
110#define UCCE_RXB7 0x00008000
111#define UCCE_RXB6 0x00004000
112#define UCCE_RXB5 0x00002000
113#define UCCE_RXB4 0x00001000
114#define UCCE_RXB3 0x00000800
115#define UCCE_RXB2 0x00000400
116#define UCCE_RXB1 0x00000200
117#define UCCE_RXB0 0x00000100
118#define UCCE_RXF7 0x00000080
119#define UCCE_RXF6 0x00000040
120#define UCCE_RXF5 0x00000020
121#define UCCE_RXF4 0x00000010
122#define UCCE_RXF3 0x00000008
123#define UCCE_RXF2 0x00000004
124#define UCCE_RXF1 0x00000002
125#define UCCE_RXF0 0x00000001
126
127#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
128 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
129#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
130 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
131#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
132 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
133#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
134 UCCE_RXC | UCCE_TXC | UCCE_TXE)
135
136/* UEC TEMODR Register
137*/
138#define TEMODER_SCHEDULER_ENABLE 0x2000
139#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
140#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
141#define TEMODER_RMON_STATISTICS 0x0100
142#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
143
144#define TEMODER_INIT_VALUE 0xc000
145
146/* UEC REMODR Register
147*/
148#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
149#define REMODER_RX_EXTENDED_FEATURES 0x80000000
150#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
151#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
152#define REMODER_RX_QOS_MODE_SHIFT (31-15)
153#define REMODER_RMON_STATISTICS 0x00001000
154#define REMODER_RX_EXTENDED_FILTERING 0x00000800
155#define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
156#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
157#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
158#define REMODER_IP_CHECKSUM_CHECK 0x00000002
159#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
160
161#define REMODER_INIT_VALUE 0
162
163/* BMRx - Bus Mode Register */
164#define BMR_GLB 0x20
165#define BMR_BO_BE 0x10
166#define BMR_DTB_SECONDARY_BUS 0x02
167#define BMR_BDB_SECONDARY_BUS 0x01
168
169#define BMR_SHIFT 24
170#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
171
172/* UEC UCCS (Ethernet Status Register)
173 */
174#define UCCS_BPR 0x02
175#define UCCS_PAU 0x02
176#define UCCS_MPD 0x01
177
178/* UEC MIIMCFG (MII Management Configuration Register)
179 */
180#define MIIMCFG_RESET_MANAGEMENT 0x80000000
181#define MIIMCFG_NO_PREAMBLE 0x00000010
182#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
183#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
184#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
185#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
186#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
187#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
188#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
189#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
190#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
191
192#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
193 MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
194
195/* UEC MIIMCOM (MII Management Command Register)
196 */
197#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
198#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
199
200/* UEC MIIMADD (MII Management Address Register)
201 */
202#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
203#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
204
205/* UEC MIIMCON (MII Management Control Register)
206 */
207#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
208#define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
209
210/* UEC MIIMIND (MII Management Indicator Register)
211 */
212#define MIIMIND_NOT_VALID 0x00000004
213#define MIIMIND_SCAN 0x00000002
214#define MIIMIND_BUSY 0x00000001
215
216/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
217 */
218#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
219#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
220
221/* UEC UESCR (Ethernet Statistics Control Register)
222 */
223#define UESCR_AUTOZ 0x8000
224#define UESCR_CLRCNT 0x4000
225#define UESCR_MAXCOV_SHIFT (15 - 7)
226#define UESCR_SCOV_SHIFT (15 - 15)
227
228/****** Tx data struct collection ******/
229/* Tx thread data, each Tx thread has one this struct.
230*/
231typedef struct uec_thread_data_tx {
232 u8 res0[136];
233} __attribute__ ((packed)) uec_thread_data_tx_t;
234
235/* Tx thread parameter, each Tx thread has one this struct.
236*/
237typedef struct uec_thread_tx_pram {
238 u8 res0[64];
239} __attribute__ ((packed)) uec_thread_tx_pram_t;
240
241/* Send queue queue-descriptor, each Tx queue has one this QD
242*/
243typedef struct uec_send_queue_qd {
244 u32 bd_ring_base; /* pointer to BD ring base address */
245 u8 res0[0x8];
246 u32 last_bd_completed_address; /* last entry in BD ring */
247 u8 res1[0x30];
248} __attribute__ ((packed)) uec_send_queue_qd_t;
249
250/* Send queue memory region */
251typedef struct uec_send_queue_mem_region {
252 uec_send_queue_qd_t sqqd[MAX_TX_QUEUES];
253} __attribute__ ((packed)) uec_send_queue_mem_region_t;
254
255/* Scheduler struct
256*/
257typedef struct uec_scheduler {
258 u16 cpucount0; /* CPU packet counter */
259 u16 cpucount1; /* CPU packet counter */
260 u16 cecount0; /* QE packet counter */
261 u16 cecount1; /* QE packet counter */
262 u16 cpucount2; /* CPU packet counter */
263 u16 cpucount3; /* CPU packet counter */
264 u16 cecount2; /* QE packet counter */
265 u16 cecount3; /* QE packet counter */
266 u16 cpucount4; /* CPU packet counter */
267 u16 cpucount5; /* CPU packet counter */
268 u16 cecount4; /* QE packet counter */
269 u16 cecount5; /* QE packet counter */
270 u16 cpucount6; /* CPU packet counter */
271 u16 cpucount7; /* CPU packet counter */
272 u16 cecount6; /* QE packet counter */
273 u16 cecount7; /* QE packet counter */
274 u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
275 u32 rtsrshadow; /* temporary variable handled by QE */
276 u32 time; /* temporary variable handled by QE */
277 u32 ttl; /* temporary variable handled by QE */
278 u32 mblinterval; /* max burst length interval */
279 u16 nortsrbytetime; /* normalized value of byte time in tsr units */
280 u8 fracsiz;
281 u8 res0[1];
282 u8 strictpriorityq; /* Strict Priority Mask register */
283 u8 txasap; /* Transmit ASAP register */
284 u8 extrabw; /* Extra BandWidth register */
285 u8 oldwfqmask; /* temporary variable handled by QE */
286 u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
287 u32 minw; /* temporary variable handled by QE */
288 u8 res1[0x70-0x64];
289} __attribute__ ((packed)) uec_scheduler_t;
290
291/* Tx firmware counters
292*/
293typedef struct uec_tx_firmware_statistics_pram {
294 u32 sicoltx; /* single collision */
295 u32 mulcoltx; /* multiple collision */
296 u32 latecoltxfr; /* late collision */
297 u32 frabortduecol; /* frames aborted due to tx collision */
298 u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
299 u32 carriersenseertx; /* carrier sense error */
300 u32 frtxok; /* frames transmitted OK */
301 u32 txfrexcessivedefer;
302 u32 txpkts256; /* total packets(including bad) 256~511 B */
303 u32 txpkts512; /* total packets(including bad) 512~1023B */
304 u32 txpkts1024; /* total packets(including bad) 1024~1518B */
305 u32 txpktsjumbo; /* total packets(including bad) >1024 */
306} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
307
308/* Tx global parameter table
309*/
310typedef struct uec_tx_global_pram {
311 u16 temoder;
312 u8 res0[0x38-0x02];
313 u32 sqptr;
314 u32 schedulerbasepointer;
315 u32 txrmonbaseptr;
316 u32 tstate;
317 u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
318 u32 vtagtable[0x8];
319 u32 tqptr;
320 u8 res2[0x80-0x74];
321} __attribute__ ((packed)) uec_tx_global_pram_t;
322
323
324/****** Rx data struct collection ******/
325/* Rx thread data, each Rx thread has one this struct.
326*/
327typedef struct uec_thread_data_rx {
328 u8 res0[40];
329} __attribute__ ((packed)) uec_thread_data_rx_t;
330
331/* Rx thread parameter, each Rx thread has one this struct.
332*/
333typedef struct uec_thread_rx_pram {
334 u8 res0[128];
335} __attribute__ ((packed)) uec_thread_rx_pram_t;
336
337/* Rx firmware counters
338*/
339typedef struct uec_rx_firmware_statistics_pram {
340 u32 frrxfcser; /* frames with crc error */
341 u32 fraligner; /* frames with alignment error */
342 u32 inrangelenrxer; /* in range length error */
343 u32 outrangelenrxer; /* out of range length error */
344 u32 frtoolong; /* frame too long */
345 u32 runt; /* runt */
346 u32 verylongevent; /* very long event */
347 u32 symbolerror; /* symbol error */
348 u32 dropbsy; /* drop because of BD not ready */
349 u8 res0[0x8];
350 u32 mismatchdrop; /* drop because of MAC filtering */
351 u32 underpkts; /* total frames less than 64 octets */
352 u32 pkts256; /* total frames(including bad)256~511 B */
353 u32 pkts512; /* total frames(including bad)512~1023 B */
354 u32 pkts1024; /* total frames(including bad)1024~1518 B */
355 u32 pktsjumbo; /* total frames(including bad) >1024 B */
356 u32 frlossinmacer;
357 u32 pausefr; /* pause frames */
358 u8 res1[0x4];
359 u32 removevlan;
360 u32 replacevlan;
361 u32 insertvlan;
362} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
363
364/* Rx interrupt coalescing entry, each Rx queue has one this entry.
365*/
366typedef struct uec_rx_interrupt_coalescing_entry {
367 u32 maxvalue;
368 u32 counter;
369} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
370
371typedef struct uec_rx_interrupt_coalescing_table {
372 uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES];
373} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
374
375/* RxBD queue entry, each Rx queue has one this entry.
376*/
377typedef struct uec_rx_bd_queues_entry {
378 u32 bdbaseptr; /* BD base pointer */
379 u32 bdptr; /* BD pointer */
380 u32 externalbdbaseptr; /* external BD base pointer */
381 u32 externalbdptr; /* external BD pointer */
382} __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
383
384/* Rx global paramter table
385*/
386typedef struct uec_rx_global_pram {
387 u32 remoder; /* ethernet mode reg. */
388 u32 rqptr; /* base pointer to the Rx Queues */
389 u32 res0[0x1];
390 u8 res1[0x20-0xC];
391 u16 typeorlen;
392 u8 res2[0x1];
393 u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
394 u32 rxrmonbaseptr; /* Rx RMON statistics base */
395 u8 res3[0x30-0x28];
396 u32 intcoalescingptr; /* Interrupt coalescing table pointer */
397 u8 res4[0x36-0x34];
398 u8 rstate;
399 u8 res5[0x46-0x37];
400 u16 mrblr; /* max receive buffer length reg. */
401 u32 rbdqptr; /* RxBD parameter table description */
402 u16 mflr; /* max frame length reg. */
403 u16 minflr; /* min frame length reg. */
404 u16 maxd1; /* max dma1 length reg. */
405 u16 maxd2; /* max dma2 length reg. */
406 u32 ecamptr; /* external CAM address */
407 u32 l2qt; /* VLAN priority mapping table. */
408 u32 l3qt[0x8]; /* IP priority mapping table. */
409 u16 vlantype; /* vlan type */
410 u16 vlantci; /* default vlan tci */
411 u8 addressfiltering[64];/* address filtering data structure */
412 u32 exfGlobalParam; /* extended filtering global parameters */
413 u8 res6[0x100-0xC4]; /* Initialize to zero */
414} __attribute__ ((packed)) uec_rx_global_pram_t;
415
416#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
417
418
419/****** UEC common ******/
420/* UCC statistics - hardware counters
421*/
422typedef struct uec_hardware_statistics {
423 u32 tx64;
424 u32 tx127;
425 u32 tx255;
426 u32 rx64;
427 u32 rx127;
428 u32 rx255;
429 u32 txok;
430 u16 txcf;
431 u32 tmca;
432 u32 tbca;
433 u32 rxfok;
434 u32 rxbok;
435 u32 rbyt;
436 u32 rmca;
437 u32 rbca;
438} __attribute__ ((packed)) uec_hardware_statistics_t;
439
440/* InitEnet command parameter
441*/
442typedef struct uec_init_cmd_pram {
443 u8 resinit0;
444 u8 resinit1;
445 u8 resinit2;
446 u8 resinit3;
447 u16 resinit4;
448 u8 res1[0x1];
449 u8 largestexternallookupkeysize;
450 u32 rgftgfrxglobal;
451 u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
452 u8 res2[0x38 - 0x30];
453 u32 txglobal; /* tx global */
454 u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
455 u8 res3[0x1];
456} __attribute__ ((packed)) uec_init_cmd_pram_t;
457
458#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
459#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
460
461#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
462#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
463#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
464#define ENET_INIT_PARAM_SNUM_SHIFT 24
465
466#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
467#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
468#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
469#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
470#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
471
472/* structure representing 82xx Address Filtering Enet Address in PRAM
473*/
474typedef struct uec_82xx_enet_address {
475 u8 res1[0x2];
476 u16 h; /* address (MSB) */
477 u16 m; /* address */
478 u16 l; /* address (LSB) */
479} __attribute__ ((packed)) uec_82xx_enet_address_t;
480
481/* structure representing 82xx Address Filtering PRAM
482*/
483typedef struct uec_82xx_address_filtering_pram {
484 u32 iaddr_h; /* individual address filter, high */
485 u32 iaddr_l; /* individual address filter, low */
486 u32 gaddr_h; /* group address filter, high */
487 u32 gaddr_l; /* group address filter, low */
488 uec_82xx_enet_address_t taddr;
489 uec_82xx_enet_address_t paddr[4];
490 u8 res0[0x40-0x38];
491} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
492
493/* Buffer Descriptor
494*/
495typedef struct buffer_descriptor {
496 u16 status;
497 u16 len;
498 u32 data;
499} __attribute__ ((packed)) qe_bd_t, *p_bd_t;
500
501#define SIZEOFBD sizeof(qe_bd_t)
502
503/* Common BD flags
504*/
505#define BD_WRAP 0x2000
506#define BD_INT 0x1000
507#define BD_LAST 0x0800
508#define BD_CLEAN 0x3000
509
510/* TxBD status flags
511*/
512#define TxBD_READY 0x8000
513#define TxBD_PADCRC 0x4000
514#define TxBD_WRAP BD_WRAP
515#define TxBD_INT BD_INT
516#define TxBD_LAST BD_LAST
517#define TxBD_TXCRC 0x0400
518#define TxBD_DEF 0x0200
519#define TxBD_PP 0x0100
520#define TxBD_LC 0x0080
521#define TxBD_RL 0x0040
522#define TxBD_RC 0x003C
523#define TxBD_UNDERRUN 0x0002
524#define TxBD_TRUNC 0x0001
525
526#define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC)
527
528/* RxBD status flags
529*/
530#define RxBD_EMPTY 0x8000
531#define RxBD_OWNER 0x4000
532#define RxBD_WRAP BD_WRAP
533#define RxBD_INT BD_INT
534#define RxBD_LAST BD_LAST
535#define RxBD_FIRST 0x0400
536#define RxBD_CMR 0x0200
537#define RxBD_MISS 0x0100
538#define RxBD_BCAST 0x0080
539#define RxBD_MCAST 0x0040
540#define RxBD_LG 0x0020
541#define RxBD_NO 0x0010
542#define RxBD_SHORT 0x0008
543#define RxBD_CRCERR 0x0004
544#define RxBD_OVERRUN 0x0002
545#define RxBD_IPCH 0x0001
546
547#define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \
548 RxBD_CRCERR | RxBD_OVERRUN)
549
550/* BD access macros
551*/
552#define BD_STATUS(_bd) (((p_bd_t)(_bd))->status)
553#define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val)
554#define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len)
555#define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val)
556#define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0)
557#define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data)
558#define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data))
559#define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data))
560#define BD_ADVANCE(_bd,_status,_base) \
561 (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
562
563/* Rx Prefetched BDs
564*/
565typedef struct uec_rx_prefetched_bds {
566 qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
567} __attribute__ ((packed)) uec_rx_prefetched_bds_t;
568
569/* Alignments
570 */
571#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
572#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
573#define UEC_THREAD_RX_PRAM_ALIGNMENT 128
574#define UEC_THREAD_TX_PRAM_ALIGNMENT 64
575#define UEC_THREAD_DATA_ALIGNMENT 256
576#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
577#define UEC_SCHEDULER_ALIGNMENT 4
578#define UEC_TX_STATISTICS_ALIGNMENT 4
579#define UEC_RX_STATISTICS_ALIGNMENT 4
580#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
581#define UEC_RX_BD_QUEUES_ALIGNMENT 8
582#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
583#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
584#define UEC_RX_BD_RING_ALIGNMENT 32
585#define UEC_TX_BD_RING_ALIGNMENT 32
586#define UEC_MRBLR_ALIGNMENT 128
587#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
588#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
589#define UEC_RX_DATA_BUF_ALIGNMENT 64
590
591#define UEC_VLAN_PRIORITY_MAX 8
592#define UEC_IP_PRIORITY_MAX 64
593#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
594#define UEC_RX_BD_RING_SIZE_MIN 8
595#define UEC_TX_BD_RING_SIZE_MIN 2
596
597/* Ethernet speed
598*/
599typedef enum enet_speed {
600 ENET_SPEED_10BT, /* 10 Base T */
601 ENET_SPEED_100BT, /* 100 Base T */
602 ENET_SPEED_1000BT /* 1000 Base T */
603} enet_speed_e;
604
605/* Ethernet Address Type.
606*/
607typedef enum enet_addr_type {
608 ENET_ADDR_TYPE_INDIVIDUAL,
609 ENET_ADDR_TYPE_GROUP,
610 ENET_ADDR_TYPE_BROADCAST
611} enet_addr_type_e;
612
613/* TBI / MII Set Register
614*/
615typedef enum enet_tbi_mii_reg {
616 ENET_TBI_MII_CR = 0x00,
617 ENET_TBI_MII_SR = 0x01,
618 ENET_TBI_MII_ANA = 0x04,
619 ENET_TBI_MII_ANLPBPA = 0x05,
620 ENET_TBI_MII_ANEX = 0x06,
621 ENET_TBI_MII_ANNPT = 0x07,
622 ENET_TBI_MII_ANLPANP = 0x08,
623 ENET_TBI_MII_EXST = 0x0F,
624 ENET_TBI_MII_JD = 0x10,
625 ENET_TBI_MII_TBICON = 0x11
626} enet_tbi_mii_reg_e;
627
Haiying Wange8efef72009-06-04 16:12:42 -0400628/* TBI MDIO register bit fields*/
629#define TBICON_CLK_SELECT 0x0020
630#define TBIANA_ASYMMETRIC_PAUSE 0x0100
631#define TBIANA_SYMMETRIC_PAUSE 0x0080
632#define TBIANA_HALF_DUPLEX 0x0040
633#define TBIANA_FULL_DUPLEX 0x0020
634#define TBICR_PHY_RESET 0x8000
635#define TBICR_ANEG_ENABLE 0x1000
636#define TBICR_RESTART_ANEG 0x0200
637#define TBICR_FULL_DUPLEX 0x0100
638#define TBICR_SPEED1_SET 0x0040
639
640#define TBIANA_SETTINGS ( \
641 TBIANA_ASYMMETRIC_PAUSE \
642 | TBIANA_SYMMETRIC_PAUSE \
643 | TBIANA_FULL_DUPLEX \
644 )
645
646#define TBICR_SETTINGS ( \
647 TBICR_PHY_RESET \
648 | TBICR_ANEG_ENABLE \
649 | TBICR_FULL_DUPLEX \
650 | TBICR_SPEED1_SET \
651 )
652
Dave Liu7737d5c2006-11-03 12:11:15 -0600653/* UEC number of threads
654*/
655typedef enum uec_num_of_threads {
656 UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
657 UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
658 UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
659 UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
660 UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
661} uec_num_of_threads_e;
662
663/* UEC ethernet interface type
664*/
665typedef enum enet_interface {
666 ENET_10_MII,
667 ENET_10_RMII,
668 ENET_10_RGMII,
669 ENET_100_MII,
670 ENET_100_RMII,
671 ENET_100_RGMII,
672 ENET_1000_GMII,
673 ENET_1000_RGMII,
Haiying Wang41410ee2008-09-24 11:42:12 -0500674 ENET_1000_RGMII_ID,
Anton Vorontsov6a600c32008-03-24 20:46:28 +0300675 ENET_1000_RGMII_RXID,
Anton Vorontsov6185f802009-09-16 23:21:53 +0400676 ENET_1000_RGMII_TXID,
Dave Liu7737d5c2006-11-03 12:11:15 -0600677 ENET_1000_TBI,
Haiying Wange8efef72009-06-04 16:12:42 -0400678 ENET_1000_RTBI,
679 ENET_1000_SGMII
Dave Liu7737d5c2006-11-03 12:11:15 -0600680} enet_interface_e;
681
682/* UEC initialization info struct
683*/
Haiying Wang8e552582009-06-04 16:12:41 -0400684#define STD_UEC_INFO(num) \
685{ \
686 .uf_info = { \
687 .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
688 .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
689 .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
690 .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
691 }, \
692 .num_threads_tx = UEC_NUM_OF_THREADS_1, \
693 .num_threads_rx = UEC_NUM_OF_THREADS_1, \
694 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
695 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
696 .tx_bd_ring_len = 16, \
697 .rx_bd_ring_len = 16, \
698 .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
699 .enet_interface = CONFIG_SYS_UEC##num##_INTERFACE_MODE, \
700}
701
Dave Liu7737d5c2006-11-03 12:11:15 -0600702typedef struct uec_info {
703 ucc_fast_info_t uf_info;
704 uec_num_of_threads_e num_threads_tx;
705 uec_num_of_threads_e num_threads_rx;
Haiying Wang7211fbf2009-05-21 15:34:14 -0400706 unsigned int risc_tx;
707 unsigned int risc_rx;
Dave Liu7737d5c2006-11-03 12:11:15 -0600708 u16 rx_bd_ring_len;
709 u16 tx_bd_ring_len;
710 u8 phy_address;
711 enet_interface_e enet_interface;
712} uec_info_t;
713
714/* UEC driver initialized info
715*/
716#define MAX_RXBUF_LEN 1536
717#define MAX_FRAME_LEN 1518
718#define MIN_FRAME_LEN 64
719#define MAX_DMA1_LEN 1520
720#define MAX_DMA2_LEN 1520
721
722/* UEC driver private struct
723*/
724typedef struct uec_private {
725 uec_info_t *uec_info;
726 ucc_fast_private_t *uccf;
727 struct eth_device *dev;
728 uec_t *uec_regs;
Andy Flemingda9d4612007-08-14 00:14:25 -0500729 uec_mii_t *uec_mii_regs;
Dave Liu7737d5c2006-11-03 12:11:15 -0600730 /* enet init command parameter */
731 uec_init_cmd_pram_t *p_init_enet_param;
732 u32 init_enet_param_offset;
733 /* Rx and Tx paramter */
734 uec_rx_global_pram_t *p_rx_glbl_pram;
735 u32 rx_glbl_pram_offset;
736 uec_tx_global_pram_t *p_tx_glbl_pram;
737 u32 tx_glbl_pram_offset;
738 uec_send_queue_mem_region_t *p_send_q_mem_reg;
739 u32 send_q_mem_reg_offset;
740 uec_thread_data_tx_t *p_thread_data_tx;
741 u32 thread_dat_tx_offset;
742 uec_thread_data_rx_t *p_thread_data_rx;
743 u32 thread_dat_rx_offset;
744 uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl;
745 u32 rx_bd_qs_tbl_offset;
746 /* BDs specific */
747 u8 *p_tx_bd_ring;
748 u32 tx_bd_ring_offset;
749 u8 *p_rx_bd_ring;
750 u32 rx_bd_ring_offset;
751 u8 *p_rx_buf;
752 u32 rx_buf_offset;
753 volatile qe_bd_t *txBd;
754 volatile qe_bd_t *rxBd;
755 /* Status */
756 int mac_tx_enabled;
757 int mac_rx_enabled;
758 int grace_stopped_tx;
759 int grace_stopped_rx;
760 int the_first_run;
761 /* PHY specific */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200762 struct uec_mii_info *mii_info;
Dave Liu7737d5c2006-11-03 12:11:15 -0600763 int oldspeed;
764 int oldduplex;
765 int oldlink;
766} uec_private_t;
767
Haiying Wang8e552582009-06-04 16:12:41 -0400768int uec_initialize(bd_t *bis, uec_info_t *uec_info);
769int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
770int uec_standard_init(bd_t *bis);
Dave Liu7737d5c2006-11-03 12:11:15 -0600771#endif /* __UEC_H__ */