blob: 95f26524948fd56ba9313b14bf26eecab8cb7bfb [file] [log] [blame]
Heiko Stuebner02ce99e2020-07-01 11:28:42 +02001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
4 */
5
6/ {
7 chosen {
8 u-boot,spl-boot-order = &sdmmc;
9 };
Chris Morgand70c0ca2021-08-05 16:27:52 +080010
11 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 mmc0 = &sdmmc;
15 serial1 = &uart1;
16 serial2 = &uart2;
17 spi0 = &sfc;
18 };
Chris Morganb774be92021-08-25 11:23:57 -050019
Jagan Teki43419b92021-11-15 23:08:19 +053020 dmc {
21 u-boot,dm-pre-reloc;
22 compatible = "rockchip,px30-dmc", "syscon";
23 reg = <0x0 0xff2a0000 0x0 0x1000>;
24 };
25
Chris Morganb774be92021-08-25 11:23:57 -050026 rng: rng@ff0b0000 {
27 compatible = "rockchip,cryptov2-rng";
28 reg = <0x0 0xff0b0000 0x0 0x4000>;
29 status = "okay";
30 };
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020031};
32
Chris Morgan8d43e242021-08-05 11:48:48 -050033/* U-Boot clk driver for px30 cannot set GPU_CLK */
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020034&cru {
35 u-boot,dm-pre-reloc;
Chris Morgan8d43e242021-08-05 11:48:48 -050036 assigned-clocks = <&cru PLL_NPLL>,
37 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
38 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
39 <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
40
41 assigned-clock-rates = <1188000000>,
42 <200000000>, <200000000>,
43 <150000000>, <150000000>,
44 <100000000>, <17000000>;
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020045};
46
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020047&gpio0 {
48 u-boot,dm-pre-reloc;
49};
50
51&gpio1 {
52 u-boot,dm-pre-reloc;
53};
54
55&gpio2 {
56 u-boot,dm-pre-reloc;
57};
58
59&gpio3 {
60 u-boot,dm-pre-reloc;
61};
62
63&grf {
64 u-boot,dm-pre-reloc;
65};
66
67&pmucru {
68 u-boot,dm-pre-reloc;
69};
70
71&pmugrf {
72 u-boot,dm-pre-reloc;
73};
74
75&saradc {
76 u-boot,dm-pre-reloc;
77 status = "okay";
78};
79
80&sdmmc {
81 u-boot,dm-pre-reloc;
82
83 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
84 u-boot,spl-fifo-mode;
85};
86
Chris Morgand70c0ca2021-08-05 16:27:52 +080087&sfc {
88 u-boot,dm-pre-reloc;
89};
90
Jagan Teki19a4d312021-11-15 23:08:20 +053091&{/spi@ff3a0000/flash@0} {
Chris Morgand70c0ca2021-08-05 16:27:52 +080092 u-boot,dm-pre-reloc;
93};
94
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020095&uart1 {
96 clock-frequency = <24000000>;
97 u-boot,dm-pre-reloc;
98};
99
100&uart2 {
101 clock-frequency = <24000000>;
102 u-boot,dm-pre-reloc;
103};
104
105&xin24m {
106 u-boot,dm-pre-reloc;
107};