blob: ea3641800d6b01a4091078ee166247b92d8fc7f4 [file] [log] [blame]
Heiko Stuebner02ce99e2020-07-01 11:28:42 +02001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
4 */
5
6/ {
7 chosen {
8 u-boot,spl-boot-order = &sdmmc;
9 };
Chris Morgand70c0ca2021-08-05 16:27:52 +080010
11 aliases {
12 i2c0 = &i2c0;
13 i2c1 = &i2c1;
14 mmc0 = &sdmmc;
15 serial1 = &uart1;
16 serial2 = &uart2;
17 spi0 = &sfc;
18 };
Chris Morganb774be92021-08-25 11:23:57 -050019
20 rng: rng@ff0b0000 {
21 compatible = "rockchip,cryptov2-rng";
22 reg = <0x0 0xff0b0000 0x0 0x4000>;
23 status = "okay";
24 };
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020025};
26
Chris Morgan8d43e242021-08-05 11:48:48 -050027/* U-Boot clk driver for px30 cannot set GPU_CLK */
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020028&cru {
29 u-boot,dm-pre-reloc;
Chris Morgan8d43e242021-08-05 11:48:48 -050030 assigned-clocks = <&cru PLL_NPLL>,
31 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
32 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
33 <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
34
35 assigned-clock-rates = <1188000000>,
36 <200000000>, <200000000>,
37 <150000000>, <150000000>,
38 <100000000>, <17000000>;
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020039};
40
41&dmc {
42 u-boot,dm-pre-reloc;
43};
44
45&gpio0 {
46 u-boot,dm-pre-reloc;
47};
48
49&gpio1 {
50 u-boot,dm-pre-reloc;
51};
52
53&gpio2 {
54 u-boot,dm-pre-reloc;
55};
56
57&gpio3 {
58 u-boot,dm-pre-reloc;
59};
60
61&grf {
62 u-boot,dm-pre-reloc;
63};
64
65&pmucru {
66 u-boot,dm-pre-reloc;
67};
68
69&pmugrf {
70 u-boot,dm-pre-reloc;
71};
72
73&saradc {
74 u-boot,dm-pre-reloc;
75 status = "okay";
76};
77
78&sdmmc {
79 u-boot,dm-pre-reloc;
80
81 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
82 u-boot,spl-fifo-mode;
83};
84
Chris Morgand70c0ca2021-08-05 16:27:52 +080085&sfc {
86 u-boot,dm-pre-reloc;
87};
88
Chris Morgan193ab222021-08-20 20:46:58 -050089&{/sfc@ff3a0000/flash@0} {
Chris Morgand70c0ca2021-08-05 16:27:52 +080090 u-boot,dm-pre-reloc;
91};
92
Heiko Stuebner02ce99e2020-07-01 11:28:42 +020093&uart1 {
94 clock-frequency = <24000000>;
95 u-boot,dm-pre-reloc;
96};
97
98&uart2 {
99 clock-frequency = <24000000>;
100 u-boot,dm-pre-reloc;
101};
102
103&xin24m {
104 u-boot,dm-pre-reloc;
105};