blob: 30e6c65805324388cad6bac27a507052935a212b [file] [log] [blame]
Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
wdenkc6097192002-11-03 00:24:07 +00003 *
4 * File Name: 405gp_pci.c
5 *
6 * Function: Initialization code for the 405GP PCI Configuration regs.
7 *
8 * Author: Mark Game
9 *
10 * Change Activity-
11 *
12 * Date Description of Change BY
13 * --------- --------------------- ---
14 * 09-Sep-98 Created MCG
15 * 02-Nov-98 Removed External arbiter selected message JWB
16 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
17 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
18 * from (0 to n) to (1 to n).
19 * 17-May-99 Port to Walnut JWB
20 * 17-Jun-99 Updated for VGA support JWB
21 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
22 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
23 * target latency timer values are not supported).
24 * Should be fixed in pass 2.
25 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
26 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
27 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
28 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
29 * really required after a reset since PMMxMAs are already
Wolfgang Denk53677ef2008-05-20 16:00:29 +020030 * disabled but is a good practice nonetheless. JWB
wdenkc6097192002-11-03 00:24:07 +000031 * 12-Jun-01 stefan.roese@esd-electronics.com
32 * - PCI host/adapter handling reworked
33 * 09-Jul-01 stefan.roese@esd-electronics.com
34 * - PCI host now configures from device 0 (not 1) to max_dev,
35 * (host configures itself)
36 * - On CPCI-405 pci base address and size is generated from
37 * SDRAM and FLASH size (CFG regs not used anymore)
38 * - Some minor changes for CPCI-405-A (adapter version)
39 * 14-Sep-01 stefan.roese@esd-electronics.com
40 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
41 * 28-Sep-01 stefan.roese@esd-electronics.com
42 * - Changed pci master configuration for linux compatibility
43 * (no need for bios_fixup() anymore)
44 * 26-Feb-02 stefan.roese@esd-electronics.com
45 * - Bug fixed in pci configuration (Andrew May)
46 * - Removed pci class code init for CPCI405 board
47 * 15-May-02 stefan.roese@esd-electronics.com
48 * - New vga device handling
49 * 29-May-02 stefan.roese@esd-electronics.com
50 * - PCI class code init added (if defined)
51 *----------------------------------------------------------------------------*/
52
53#include <common.h>
54#include <command.h>
Stefan Roese3048bcb2007-10-03 15:01:02 +020055#include <asm/4xx_pci.h>
wdenkc6097192002-11-03 00:24:07 +000056#include <asm/processor.h>
Stefan Roese10954932009-11-12 12:00:49 +010057#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000058#include <pci.h>
59
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +020060#ifdef CONFIG_PCI
61
Wolfgang Denkd87080b2006-03-31 18:32:53 +020062DECLARE_GLOBAL_DATA_PTR;
63
Stefan Roesea760b022009-11-12 16:41:09 +010064#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
65
Stefan Roesea760b022009-11-12 16:41:09 +010066/*#define DEBUG*/
67
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +020068/*
69 * Board-specific pci initialization
70 * Platform code can reimplement pci_pre_init() if needed
71 */
72int __pci_pre_init(struct pci_controller *hose)
73{
Stefan Roesea760b022009-11-12 16:41:09 +010074#if defined(CONFIG_405EP)
Matthias Fuchs123f1022009-07-08 13:43:55 +020075 /*
76 * Enable the internal PCI arbiter by default.
77 *
78 * On 405EP CPUs the internal arbiter can be controlled
79 * by the I2C strapping EEPROM. If you want to do so
80 * or if you want to disable the arbiter pci_pre_init()
81 * must be reimplemented without enabling the arbiter.
82 * The arbiter is enabled in this place because of
83 * compatibility reasons.
84 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020085 mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
Matthias Fuchs123f1022009-07-08 13:43:55 +020086#endif /* CONFIG_405EP */
87
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +020088 return 1;
89}
Stefan Roesea760b022009-11-12 16:41:09 +010090int pci_pre_init(struct pci_controller *hose)
91 __attribute__((weak, alias("__pci_pre_init")));
wdenkc6097192002-11-03 00:24:07 +000092
Matthias Fuchsd0a13642009-07-03 16:06:06 +020093int __is_pci_host(struct pci_controller *hose)
94{
95#if defined(CONFIG_405GP)
Stefan Roesed1c3b272009-09-09 16:25:29 +020096 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
Matthias Fuchsd0a13642009-07-03 16:06:06 +020097 return 1;
98#elif defined (CONFIG_405EP)
Stefan Roesed1c3b272009-09-09 16:25:29 +020099 if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200100 return 1;
101#endif
102 return 0;
103}
104int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
105
wdenkc6097192002-11-03 00:24:07 +0000106/*-----------------------------------------------------------------------------+
107 * pci_init. Initializes the 405GP PCI Configuration regs.
108 *-----------------------------------------------------------------------------*/
109void pci_405gp_init(struct pci_controller *hose)
110{
wdenkc6097192002-11-03 00:24:07 +0000111 int i, reg_num = 0;
112 bd_t *bd = gd->bd;
113
114 unsigned short temp_short;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
Matthias Fuchs99bcf142009-09-07 17:00:40 +0200116#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
stroesefddae7b2005-04-20 06:52:40 +0000117 char *ptmla_str, *ptmms_str;
Stefan Roese2076d0a2006-01-18 20:03:15 +0100118#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
120 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
wdenkc6097192002-11-03 00:24:07 +0000121#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
122 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
123 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
124 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
125 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
126#else
127 unsigned long pmmla[3] = {0x80000000, 0,0};
128 unsigned long pmmma[3] = {0xC0000001, 0,0};
129 unsigned long pmmpcila[3] = {0x80000000, 0,0};
130 unsigned long pmmpciha[3] = {0x00000000, 0,0};
131#endif
stroese5e746fc2004-12-16 18:15:52 +0000132#ifdef CONFIG_PCI_PNP
133#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
134 char *s;
135#endif
136#endif
wdenkc6097192002-11-03 00:24:07 +0000137
Matthias Fuchs99bcf142009-09-07 17:00:40 +0200138#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
stroesefddae7b2005-04-20 06:52:40 +0000139 ptmla_str = getenv("ptm1la");
140 ptmms_str = getenv("ptm1ms");
141 if(NULL != ptmla_str && NULL != ptmms_str ) {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200142 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
stroesefddae7b2005-04-20 06:52:40 +0000143 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
144 }
145
146 ptmla_str = getenv("ptm2la");
147 ptmms_str = getenv("ptm2ms");
148 if(NULL != ptmla_str && NULL != ptmms_str ) {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200149 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
stroesefddae7b2005-04-20 06:52:40 +0000150 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
151 }
152#endif
153
wdenkc6097192002-11-03 00:24:07 +0000154 /*
155 * Register the hose
156 */
157 hose->first_busno = 0;
158 hose->last_busno = 0xff;
159
160 /* ISA/PCI I/O space */
161 pci_set_region(hose->regions + reg_num++,
162 MIN_PCI_PCI_IOADDR,
163 MIN_PLB_PCI_IOADDR,
164 0x10000,
165 PCI_REGION_IO);
166
167 /* PCI I/O space */
168 pci_set_region(hose->regions + reg_num++,
169 0x00800000,
170 0xe8800000,
171 0x03800000,
172 PCI_REGION_IO);
173
174 reg_num = 2;
175
176 /* Memory spaces */
177 for (i=0; i<2; i++)
178 if (ptmms[i] & 1)
179 {
180 if (!i) hose->pci_fb = hose->regions + reg_num;
181
182 pci_set_region(hose->regions + reg_num++,
183 ptmpcila[i], ptmla[i],
184 ~(ptmms[i] & 0xfffff000) + 1,
185 PCI_REGION_MEM |
Kumar Galaff4e66e2009-02-06 09:49:31 -0600186 PCI_REGION_SYS_MEMORY);
wdenkc6097192002-11-03 00:24:07 +0000187 }
188
189 /* PCI memory spaces */
190 for (i=0; i<3; i++)
191 if (pmmma[i] & 1)
192 {
193 pci_set_region(hose->regions + reg_num++,
194 pmmpcila[i], pmmla[i],
195 ~(pmmma[i] & 0xfffff000) + 1,
196 PCI_REGION_MEM);
197 }
198
199 hose->region_count = reg_num;
200
201 pci_setup_indirect(hose,
202 PCICFGADR,
203 PCICFGDATA);
204
205 if (hose->pci_fb)
206 pciauto_region_init(hose->pci_fb);
207
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200208 /* Let board change/modify hose & do initial checks */
Stefan Roesea760b022009-11-12 16:41:09 +0100209 if (pci_pre_init(hose) == 0) {
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200210 printf("PCI: Board-specific initialization failed.\n");
211 printf("PCI: Configuration aborted.\n");
212 return;
213 }
214
wdenkc6097192002-11-03 00:24:07 +0000215 pci_register_hose(hose);
216
217 /*--------------------------------------------------------------------------+
218 * 405GP PCI Master configuration.
219 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
220 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
221 * Use byte reversed out routines to handle endianess.
222 *--------------------------------------------------------------------------*/
wdenkf3e0de62003-06-04 15:05:30 +0000223 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
wdenkc6097192002-11-03 00:24:07 +0000224 out32r(PMM0LA, pmmla[0]);
225 out32r(PMM0PCILA, pmmpcila[0]);
226 out32r(PMM0PCIHA, pmmpciha[0]);
227 out32r(PMM0MA, pmmma[0]);
228
229 /*--------------------------------------------------------------------------+
230 * PMM1 is not used. Initialize them to zero.
231 *--------------------------------------------------------------------------*/
wdenkf3e0de62003-06-04 15:05:30 +0000232 out32r(PMM1MA, (pmmma[1]&~0x1));
wdenkc6097192002-11-03 00:24:07 +0000233 out32r(PMM1LA, pmmla[1]);
234 out32r(PMM1PCILA, pmmpcila[1]);
235 out32r(PMM1PCIHA, pmmpciha[1]);
236 out32r(PMM1MA, pmmma[1]);
237
238 /*--------------------------------------------------------------------------+
239 * PMM2 is not used. Initialize them to zero.
240 *--------------------------------------------------------------------------*/
wdenk8bde7f72003-06-27 21:31:46 +0000241 out32r(PMM2MA, (pmmma[2]&~0x1));
wdenkc6097192002-11-03 00:24:07 +0000242 out32r(PMM2LA, pmmla[2]);
243 out32r(PMM2PCILA, pmmpcila[2]);
244 out32r(PMM2PCIHA, pmmpciha[2]);
245 out32r(PMM2MA, pmmma[2]);
246
247 /*--------------------------------------------------------------------------+
248 * 405GP PCI Target configuration. (PTM1)
249 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
250 *--------------------------------------------------------------------------*/
251 out32r(PTM1LA, ptmla[0]); /* insert address */
252 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
wdenk4654af22003-10-22 09:00:28 +0000253 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
wdenkc6097192002-11-03 00:24:07 +0000254
255 /*--------------------------------------------------------------------------+
256 * 405GP PCI Target configuration. (PTM2)
257 *--------------------------------------------------------------------------*/
258 out32r(PTM2LA, ptmla[1]); /* insert address */
wdenk4654af22003-10-22 09:00:28 +0000259 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
260
wdenkc6097192002-11-03 00:24:07 +0000261 if (ptmms[1] == 0)
262 {
263 out32r(PTM2MS, 0x00000001); /* set enable bit */
264 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
265 out32r(PTM2MS, 0x00000000); /* disable */
266 }
267 else
268 {
269 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
270 }
271
272 /*
273 * Insert Subsystem Vendor and Device ID
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
wdenkc6097192002-11-03 00:24:07 +0000276#ifdef CONFIG_CPCI405
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200277 if (is_pci_host(hose))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
wdenkc6097192002-11-03 00:24:07 +0000279 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
wdenkc6097192002-11-03 00:24:07 +0000281#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
wdenkc6097192002-11-03 00:24:07 +0000283#endif
284
285 /*
286 * Insert Class-code
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#ifdef CONFIG_SYS_PCI_CLASSCODE
289 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
290#endif /* CONFIG_SYS_PCI_CLASSCODE */
wdenkc6097192002-11-03 00:24:07 +0000291
292 /*--------------------------------------------------------------------------+
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200293 * If PCI speed = 66MHz, set 66MHz capable bit.
wdenkc6097192002-11-03 00:24:07 +0000294 *--------------------------------------------------------------------------*/
295 if (bd->bi_pci_busfreq >= 66000000) {
296 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
297 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
298 }
299
300#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
wdenk4654af22003-10-22 09:00:28 +0000301#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200302 if (is_pci_host(hose) ||
stroese5e746fc2004-12-16 18:15:52 +0000303 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
wdenkc6097192002-11-03 00:24:07 +0000304#endif
305 {
306 /*--------------------------------------------------------------------------+
307 * Write the 405GP PCI Configuration regs.
308 * Enable 405GP to be a master on the PCI bus (PMM).
309 * Enable 405GP to act as a PCI memory target (PTM).
310 *--------------------------------------------------------------------------*/
311 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
312 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
313 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
314 }
315#endif
316
Matthias Fuchs632e9b62009-07-08 15:31:57 +0200317#if defined(CONFIG_405EP)
318 /*
319 * on ppc405ep vendor/device id is not set
320 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
321 * are the correct values.
322 */
323 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
324 pci_write_config_word(PCIDEVID_405GP,
325 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
stroese428c5632003-09-12 08:52:09 +0000326#endif
327
wdenkc6097192002-11-03 00:24:07 +0000328 /*
329 * Set HCE bit (Host Configuration Enabled)
330 */
331 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
332 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
333
334#ifdef CONFIG_PCI_PNP
335 /*--------------------------------------------------------------------------+
336 * Scan the PCI bus and configure devices found.
337 *--------------------------------------------------------------------------*/
338#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200339 if (is_pci_host(hose) ||
stroese5e746fc2004-12-16 18:15:52 +0000340 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
wdenkc6097192002-11-03 00:24:07 +0000341#endif
342 {
343#ifdef CONFIG_PCI_SCAN_SHOW
344 printf("PCI: Bus Dev VenId DevId Class Int\n");
345#endif
wdenkc6097192002-11-03 00:24:07 +0000346 hose->last_busno = pci_hose_scan(hose);
347 }
348#endif /* CONFIG_PCI_PNP */
349
350}
351
352/*
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100353 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
wdenkc6097192002-11-03 00:24:07 +0000354 * be set as an Adapter.
355 *
356 * I (Andrew May) don't know what we should do here, but I don't want
357 * the auto setup of a PCI device disabling what is done pci_405gp_init
358 * as has happened before.
359 */
360void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
361 struct pci_config_table *entry)
362{
363#ifdef DEBUG
wdenk8bde7f72003-06-27 21:31:46 +0000364 printf("405gp_setup_bridge\n");
wdenkc6097192002-11-03 00:24:07 +0000365#endif
366}
367
368/*
369 *
370 */
371
372void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
373{
374 unsigned char int_line = 0xff;
375
376 /*
377 * Write pci interrupt line register (cpci405 specific)
378 */
379 switch (PCI_DEV(dev) & 0x03)
380 {
381 case 0:
382 int_line = 27 + 2;
383 break;
384 case 1:
385 int_line = 27 + 3;
386 break;
387 case 2:
388 int_line = 27 + 0;
389 break;
390 case 3:
391 int_line = 27 + 1;
392 break;
393 }
394
395 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
396}
397
398void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
399 struct pci_config_table *entry)
400{
401 unsigned int cmdstat = 0;
402
Stefan Roesef3fecfe2006-03-13 09:43:01 +0100403 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000404
405 /* always enable io space on vga boards */
406 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
407 cmdstat |= PCI_COMMAND_IO;
408 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
409}
410
Stefan Roese27e72152015-05-07 13:00:23 +0200411#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
wdenkc6097192002-11-03 00:24:07 +0000412
413/*
414 *As is these functs get called out of flash Not a horrible
415 *thing, but something to keep in mind. (no statics?)
416 */
417static struct pci_config_table pci_405gp_config_table[] = {
418/*if VendID is 0 it terminates the table search (ie Walnut)*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
420 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
wdenkc6097192002-11-03 00:24:07 +0000421 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
422#endif
423 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
424 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
425
426 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
427 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
428
429 { }
430};
431
432static struct pci_controller hose = {
433 fixup_irq: pci_405gp_fixup_irq,
434 config_table: pci_405gp_config_table,
435};
436
stroesead10dd92003-02-14 11:21:23 +0000437void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +0000438{
439 /*we want the ptrs to RAM not flash (ie don't use init list)*/
440 hose.fixup_irq = pci_405gp_fixup_irq;
441 hose.config_table = pci_405gp_config_table;
442 pci_405gp_init(&hose);
443}
444
445#endif
446
wdenkc6097192002-11-03 00:24:07 +0000447#endif /* CONFIG_405GP */
448
449/*-----------------------------------------------------------------------------+
450 * CONFIG_440
451 *-----------------------------------------------------------------------------*/
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200452#if defined(CONFIG_440)
wdenkc6097192002-11-03 00:24:07 +0000453
Stefan Roesedb643772010-05-21 15:06:19 +0200454#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
wdenkc6097192002-11-03 00:24:07 +0000455static struct pci_controller ppc440_hose = {0};
Stefan Roesedb643772010-05-21 15:06:19 +0200456#endif
wdenkc6097192002-11-03 00:24:07 +0000457
Stefan Roese9a81c612009-10-29 16:54:52 +0100458/*
459 * This routine is called to determine if a pci scan should be
460 * performed. With various hardware environments (especially cPCI and
461 * PPMC) it's insufficient to depend on the state of the arbiter enable
462 * bit in the strap register, or generic host/adapter assumptions.
463 *
464 * Rather than hard-code a bad assumption in the general 440 code, the
465 * 440 pci code requires the board to decide at runtime.
466 *
467 * Return 0 for adapter mode, non-zero for host (monarch) mode.
468 *
469 * Weak default implementation: "Normal" boards implement the PCI
470 * host functionality. This can be overridden for PCI adapter boards.
471 */
472int __is_pci_host(struct pci_controller *hose)
473{
474 return 1;
475}
476int is_pci_host(struct pci_controller *hose)
477 __attribute__((weak, alias("__is_pci_host")));
wdenkc6097192002-11-03 00:24:07 +0000478
Stefan Roese10954932009-11-12 12:00:49 +0100479#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
480 defined(CONFIG_440GR) || defined(CONFIG_440GRX)
Stefan Roesea760b022009-11-12 16:41:09 +0100481
482#if defined(CONFIG_SYS_PCI_TARGET_INIT)
483/*
484 * pci_target_init
485 *
486 * The bootstrap configuration provides default settings for the pci
487 * inbound map (PIM). But the bootstrap config choices are limited and
488 * may not be sufficient for a given board.
489 */
Stefan Roese10954932009-11-12 12:00:49 +0100490void __pci_target_init(struct pci_controller *hose)
491{
492 /*
493 * Set up Direct MMIO registers
494 */
495
496 /*
497 * PowerPC440 EP PCI Master configuration.
498 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
499 * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
500 * Use byte reversed out routines to handle endianess.
501 * Make this region non-prefetchable.
502 */
503 /* PMM0 Mask/Attribute - disabled b4 setting */
504 out_le32((void *)PCIL0_PMM0MA, 0x00000000);
505 /* PMM0 Local Address */
506 out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
507 /* PMM0 PCI Low Address */
508 out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
509 /* PMM0 PCI High Address */
510 out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
511 /* 512M + No prefetching, and enable region */
512 out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
513
514 /* PMM1 Mask/Attribute - disabled b4 setting */
515 out_le32((void *)PCIL0_PMM1MA, 0x00000000);
516 /* PMM1 Local Address */
517 out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
518 /* PMM1 PCI Low Address */
519 out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
520 /* PMM1 PCI High Address */
521 out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
522 /* 512M + No prefetching, and enable region */
523 out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
524
525 out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
526 out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
527 out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
528 out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
529
530 /*
531 * Set up Configuration registers
532 */
533
534 /* Program the board's subsystem id/vendor id */
535 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
536 CONFIG_SYS_PCI_SUBSYS_VENDORID);
537 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
538
539 /* Configure command register as bus master */
540 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
541
542 /* 240nS PCI clock */
543 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
544
545 /* No error reporting */
546 pci_write_config_word(0, PCI_ERREN, 0);
547
548 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
549}
Stefan Roesea760b022009-11-12 16:41:09 +0100550#endif /* CONFIG_SYS_PCI_TARGET_INIT */
551
552/*
553 * pci_pre_init
554 *
555 * This routine is called just prior to registering the hose and gives
556 * the board the opportunity to check things. Returning a value of zero
557 * indicates that things are bad & PCI initialization should be aborted.
558 *
559 * Different boards may wish to customize the pci controller structure
560 * (add regions, override default access routines, etc) or perform
561 * certain pre-initialization actions.
562 *
563 */
564int __pci_pre_init(struct pci_controller *hose)
565{
566 u32 reg;
567
568 /*
569 * Set priority for all PLB3 devices to 0.
570 * Set PLB3 arbiter to fair mode.
571 */
Stefan Roese5e7abce2010-09-11 09:31:43 +0200572 mfsdr(SDR0_AMP1, reg);
573 mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
574 reg = mfdcr(PLB3A0_ACR);
575 mtdcr(PLB3A0_ACR, reg | 0x80000000);
Stefan Roesea760b022009-11-12 16:41:09 +0100576
577 /*
578 * Set priority for all PLB4 devices to 0.
579 */
Stefan Roese5e7abce2010-09-11 09:31:43 +0200580 mfsdr(SDR0_AMP0, reg);
581 mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
582 reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
583 mtdcr(PLB4A0_ACR, reg);
Stefan Roesea760b022009-11-12 16:41:09 +0100584
585 /*
586 * Set Nebula PLB4 arbiter to fair mode.
587 */
588 /* Segment0 */
Stefan Roese5e7abce2010-09-11 09:31:43 +0200589 reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
590 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
591 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
592 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
593 mtdcr(PLB4A0_ACR, reg);
Stefan Roesea760b022009-11-12 16:41:09 +0100594
595 /* Segment1 */
Stefan Roese5e7abce2010-09-11 09:31:43 +0200596 reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
597 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
598 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
599 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
600 mtdcr(PLB4A1_ACR, reg);
Stefan Roesea760b022009-11-12 16:41:09 +0100601
602#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
603 hose->fixup_irq = board_pci_fixup_irq;
604#endif
605
606 return 1;
607}
608
Stefan Roese10954932009-11-12 12:00:49 +0100609#else /* defined(CONFIG_440EP) ... */
Stefan Roesea760b022009-11-12 16:41:09 +0100610
611#if defined(CONFIG_SYS_PCI_TARGET_INIT)
Stefan Roese10954932009-11-12 12:00:49 +0100612void __pci_target_init(struct pci_controller * hose)
613{
614 /*
615 * Disable everything
616 */
617 out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
618 out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
619 out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
620 out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
621
622 /*
623 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
624 * strapping options do not support sizes such as 128/256 MB.
625 */
626 out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
627 out_le32((void *)PCIL0_PIM0LAH, 0);
628 out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
629 out_le32((void *)PCIL0_BAR0, 0);
630
631 /*
632 * Program the board's subsystem id/vendor id
633 */
634 out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
635 out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
636
637 out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
638 PCI_COMMAND_MEMORY);
639}
Stefan Roesea760b022009-11-12 16:41:09 +0100640#endif /* CONFIG_SYS_PCI_TARGET_INIT */
641
642int __pci_pre_init(struct pci_controller *hose)
643{
644 /*
645 * This board is always configured as the host & requires the
646 * PCI arbiter to be enabled.
647 */
648 if (!pci_arbiter_enabled()) {
649 printf("PCI: PCI Arbiter disabled!\n");
650 return 0;
651 }
652
653 return 1;
654}
655
Stefan Roese10954932009-11-12 12:00:49 +0100656#endif /* defined(CONFIG_440EP) ... */
Stefan Roesea760b022009-11-12 16:41:09 +0100657
658#if defined(CONFIG_SYS_PCI_TARGET_INIT)
Stefan Roese10954932009-11-12 12:00:49 +0100659void pci_target_init(struct pci_controller * hose)
660 __attribute__((weak, alias("__pci_target_init")));
Stefan Roesea760b022009-11-12 16:41:09 +0100661#endif /* CONFIG_SYS_PCI_TARGET_INIT */
Stefan Roese10954932009-11-12 12:00:49 +0100662
Stefan Roesea760b022009-11-12 16:41:09 +0100663int pci_pre_init(struct pci_controller *hose)
664 __attribute__((weak, alias("__pci_pre_init")));
Stefan Roese10954932009-11-12 12:00:49 +0100665
Stefan Roese6c700492009-11-12 17:19:37 +0100666#if defined(CONFIG_SYS_PCI_MASTER_INIT)
667void __pci_master_init(struct pci_controller *hose)
668{
669 u16 reg;
670
671 /*
672 * Write the PowerPC440 EP PCI Configuration regs.
673 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
674 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
675 */
676 pci_read_config_word(0, PCI_COMMAND, &reg);
677 pci_write_config_word(0, PCI_COMMAND, reg |
678 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
679}
680void pci_master_init(struct pci_controller *hose)
681 __attribute__((weak, alias("__pci_master_init")));
682#endif /* CONFIG_SYS_PCI_MASTER_INIT */
683
Stefan Roesedb643772010-05-21 15:06:19 +0200684#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
Wolfgang Denke5d5ed42011-10-29 09:38:31 +0000685static int pci_440_init (struct pci_controller *hose)
wdenkc6097192002-11-03 00:24:07 +0000686{
687 int reg_num = 0;
wdenkc6097192002-11-03 00:24:07 +0000688
Stefan Roese5568e612005-11-22 13:20:42 +0100689#ifndef CONFIG_DISABLE_PISE_TEST
wdenkc6097192002-11-03 00:24:07 +0000690 /*--------------------------------------------------------------------------+
691 * The PCI initialization sequence enable bit must be set ... if not abort
wdenk3c74e322004-02-22 23:46:08 +0000692 * pci setup since updating the bit requires chip reset.
wdenkc6097192002-11-03 00:24:07 +0000693 *--------------------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200694#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese5568e612005-11-22 13:20:42 +0100695 unsigned long strap;
696
Stefan Roesed1c3b272009-09-09 16:25:29 +0200697 mfsdr(SDR0_SDSTP1,strap);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100698 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
wdenk3c74e322004-02-22 23:46:08 +0000699 printf("PCI: SDR0_STRP1[PISE] not set.\n");
700 printf("PCI: Configuration aborted.\n");
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200701 return -1;
wdenk3c74e322004-02-22 23:46:08 +0000702 }
Stefan Roese5568e612005-11-22 13:20:42 +0100703#elif defined(CONFIG_440GP)
704 unsigned long strap;
705
Stefan Roesed1c3b272009-09-09 16:25:29 +0200706 strap = mfdcr(CPC0_STRP1);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100707 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
wdenk3c74e322004-02-22 23:46:08 +0000708 printf("PCI: CPC0_STRP1[PISE] not set.\n");
709 printf("PCI: Configuration aborted.\n");
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200710 return -1;
wdenk3c74e322004-02-22 23:46:08 +0000711 }
712#endif
Stefan Roese5568e612005-11-22 13:20:42 +0100713#endif /* CONFIG_DISABLE_PISE_TEST */
714
wdenkc6097192002-11-03 00:24:07 +0000715 /*--------------------------------------------------------------------------+
716 * PCI controller init
717 *--------------------------------------------------------------------------*/
718 hose->first_busno = 0;
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200719 hose->last_busno = 0;
wdenkc6097192002-11-03 00:24:07 +0000720
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200721 /* PCI I/O space */
wdenkc6097192002-11-03 00:24:07 +0000722 pci_set_region(hose->regions + reg_num++,
723 0x00000000,
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200724 PCIL0_IOBASE,
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100725 0x10000,
726 PCI_REGION_IO);
wdenkc6097192002-11-03 00:24:07 +0000727
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200728 /* PCI memory space */
wdenkc6097192002-11-03 00:24:07 +0000729 pci_set_region(hose->regions + reg_num++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200730 CONFIG_SYS_PCI_TARGBASE,
731 CONFIG_SYS_PCI_MEMBASE,
732#ifdef CONFIG_SYS_PCI_MEMSIZE
733 CONFIG_SYS_PCI_MEMSIZE,
Stefan Roese899620c2006-08-15 14:22:35 +0200734#else
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100735 0x10000000,
Stefan Roese899620c2006-08-15 14:22:35 +0200736#endif
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100737 PCI_REGION_MEM );
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200738
739#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
740 defined(CONFIG_PCI_SYS_MEM_SIZE)
741 /* System memory space */
742 pci_set_region(hose->regions + reg_num++,
743 CONFIG_PCI_SYS_MEM_BUS,
744 CONFIG_PCI_SYS_MEM_PHYS,
745 CONFIG_PCI_SYS_MEM_SIZE,
Kumar Galaff4e66e2009-02-06 09:49:31 -0600746 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200747#endif
748
wdenkc6097192002-11-03 00:24:07 +0000749 hose->region_count = reg_num;
750
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200751 pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
wdenkc6097192002-11-03 00:24:07 +0000752
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100753 /* Let board change/modify hose & do initial checks */
Stefan Roesea760b022009-11-12 16:41:09 +0100754 if (pci_pre_init(hose) == 0) {
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100755 printf("PCI: Board-specific initialization failed.\n");
756 printf("PCI: Configuration aborted.\n");
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200757 return -1;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100758 }
wdenkc6097192002-11-03 00:24:07 +0000759
760 pci_register_hose( hose );
761
762 /*--------------------------------------------------------------------------+
763 * PCI target init
764 *--------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200765#if defined(CONFIG_SYS_PCI_TARGET_INIT)
wdenkc6097192002-11-03 00:24:07 +0000766 pci_target_init(hose); /* Let board setup pci target */
767#else
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200768 out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
769 out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
770 out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
wdenkc6097192002-11-03 00:24:07 +0000771#endif
772
Stefan Roese8ac41e32008-03-11 15:05:26 +0100773#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
774 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200775 out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
776 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
777#elif defined(PCIL0_BRDGOPT1)
778 out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
779 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
wdenk3c74e322004-02-22 23:46:08 +0000780#endif
wdenkc6097192002-11-03 00:24:07 +0000781
782 /*--------------------------------------------------------------------------+
783 * PCI master init: default is one 256MB region for PCI memory:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200784 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
wdenkc6097192002-11-03 00:24:07 +0000785 *--------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200786#if defined(CONFIG_SYS_PCI_MASTER_INIT)
wdenkc6097192002-11-03 00:24:07 +0000787 pci_master_init(hose); /* Let board setup pci master */
788#else
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200789 out32r( PCIL0_POM0SA, 0 ); /* disable */
790 out32r( PCIL0_POM1SA, 0 ); /* disable */
791 out32r( PCIL0_POM2SA, 0 ); /* disable */
Anatolij Gustschinf8853d12009-03-20 12:45:50 +0100792#if defined(CONFIG_440SPE)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200793 out32r( PCIL0_POM0LAL, 0x10000000 );
794 out32r( PCIL0_POM0LAH, 0x0000000c );
Anatolij Gustschinf8853d12009-03-20 12:45:50 +0100795#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200796 out32r( PCIL0_POM0LAL, 0x20000000 );
797 out32r( PCIL0_POM0LAH, 0x0000000c );
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200798#else
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200799 out32r( PCIL0_POM0LAL, 0x00000000 );
800 out32r( PCIL0_POM0LAH, 0x00000003 );
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200801#endif
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200802 out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
803 out32r( PCIL0_POM0PCIAH, 0x00000000 );
804 out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
805 out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
wdenkc6097192002-11-03 00:24:07 +0000806#endif
807
808 /*--------------------------------------------------------------------------+
809 * PCI host configuration -- we don't make any assumptions here ... the
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100810 * _board_must_indicate_ what to do -- there's just too many runtime
811 * scenarios in environments like cPCI, PPMC, etc. to make a determination
812 * based on hard-coded values or state of arbiter enable.
wdenkc6097192002-11-03 00:24:07 +0000813 *--------------------------------------------------------------------------*/
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100814 if (is_pci_host(hose)) {
wdenkc6097192002-11-03 00:24:07 +0000815#ifdef CONFIG_PCI_SCAN_SHOW
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100816 printf("PCI: Bus Dev VenId DevId Class Int\n");
wdenkc6097192002-11-03 00:24:07 +0000817#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200818#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
819 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200820 out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200821#endif
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100822 hose->last_busno = pci_hose_scan(hose);
823 }
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200824 return hose->last_busno;
wdenkc6097192002-11-03 00:24:07 +0000825}
Stefan Roesedb643772010-05-21 15:06:19 +0200826#endif
wdenkc6097192002-11-03 00:24:07 +0000827
stroesead10dd92003-02-14 11:21:23 +0000828void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +0000829{
Stefan Roesedb643772010-05-21 15:06:19 +0200830 int busno = 0;
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200831
Stefan Roesedb643772010-05-21 15:06:19 +0200832 /*
833 * Only init PCI when either master or target functionality
834 * is selected.
835 */
836#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
Wolfgang Denke5d5ed42011-10-29 09:38:31 +0000837 busno = pci_440_init(&ppc440_hose);
838 if (busno < 0)
839 return;
Stefan Roesedb643772010-05-21 15:06:19 +0200840#endif
Dirk Eibach59d1bda2009-02-03 15:15:21 +0100841#if (defined(CONFIG_440SPE) || \
842 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
843 !defined(CONFIG_PCI_DISABLE_PCIE)
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200844 pcie_setup_hoses(busno + 1);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200845#endif
wdenkc6097192002-11-03 00:24:07 +0000846}
847
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200848#endif /* CONFIG_440 */
Stefan Roese1d7b8742007-10-05 17:09:36 +0200849
850#if defined(CONFIG_405EX)
851void pci_init_board(void)
852{
853#ifdef CONFIG_PCI_SCAN_SHOW
854 printf("PCI: Bus Dev VenId DevId Class Int\n");
855#endif
856 pcie_setup_hoses(0);
857}
858#endif /* CONFIG_405EX */
859
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200860#endif /* CONFIG_PCI */