Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / d26e34c4c4b6473fdbd412a3b2dc33a94b08e8ff / . / arch / powerpc / include / asm / fsl_serdes.h
blob: cb259cce017bcb49585299774f20330ddef96671 [file] [log] [blame]
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]1/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]5 */
6
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]7#ifndef __FSL_SERDES_H
8#define __FSL_SERDES_H
9
10#include <config.h>
11
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]12enum srds_prtcl {
Hou Zhiqiang71fe2222016-08-02 19:03:22 +0800[diff] [blame]13 /*
14 * Nobody will check whether the device 'NONE' has been configured,
15 * So use it to indicate if the serdes_prtcl_map has been initialized.
16 */
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]17 NONE = 0,
18 PCIE1,
19 PCIE2,
20 PCIE3,
21 PCIE4,
22 SATA1,
23 SATA2,
24 SRIO1,
25 SRIO2,
Kumar Gala34a82582010-07-12 22:51:29 -0500[diff] [blame]26 SGMII_FM1_DTSEC1,
27 SGMII_FM1_DTSEC2,
28 SGMII_FM1_DTSEC3,
29 SGMII_FM1_DTSEC4,
30 SGMII_FM1_DTSEC5,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]31 SGMII_FM1_DTSEC6,
32 SGMII_FM1_DTSEC9,
33 SGMII_FM1_DTSEC10,
Kumar Gala34a82582010-07-12 22:51:29 -0500[diff] [blame]34 SGMII_FM2_DTSEC1,
35 SGMII_FM2_DTSEC2,
36 SGMII_FM2_DTSEC3,
37 SGMII_FM2_DTSEC4,
Timur Tabi99abf7d2012-08-14 06:47:21 +0000[diff] [blame]38 SGMII_FM2_DTSEC5,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]39 SGMII_FM2_DTSEC6,
40 SGMII_FM2_DTSEC9,
41 SGMII_FM2_DTSEC10,
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]42 SGMII_TSEC1,
43 SGMII_TSEC2,
44 SGMII_TSEC3,
45 SGMII_TSEC4,
46 XAUI_FM1,
47 XAUI_FM2,
48 AURORA,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]49 CPRI1,
50 CPRI2,
51 CPRI3,
52 CPRI4,
53 CPRI5,
54 CPRI6,
55 CPRI7,
56 CPRI8,
57 XAUI_FM1_MAC9,
58 XAUI_FM1_MAC10,
59 XAUI_FM2_MAC9,
60 XAUI_FM2_MAC10,
61 HIGIG_FM1_MAC9,
62 HIGIG_FM1_MAC10,
63 HIGIG_FM2_MAC9,
64 HIGIG_FM2_MAC10,
65 QSGMII_FM1_A, /* A indicates MACs 1-4 */
66 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
67 QSGMII_FM2_A,
68 QSGMII_FM2_B,
Shengzhou Liu82a55c12013-11-22 17:39:09 +0800[diff] [blame]69 XFI_FM1_MAC1,
70 XFI_FM1_MAC2,
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]71 XFI_FM1_MAC9,
72 XFI_FM1_MAC10,
73 XFI_FM2_MAC9,
74 XFI_FM2_MAC10,
75 INTERLAKEN,
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +0530[diff] [blame]76 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
York Sun5f208d12013-03-25 07:40:06 +0000[diff] [blame]77 QSGMII_SW1_B,
Shengzhou Liuc35f8692014-10-23 17:20:57 +0800[diff] [blame]78 SGMII_2500_FM1_DTSEC1,
79 SGMII_2500_FM1_DTSEC2,
80 SGMII_2500_FM1_DTSEC3,
81 SGMII_2500_FM1_DTSEC4,
82 SGMII_2500_FM1_DTSEC5,
83 SGMII_2500_FM1_DTSEC6,
84 SGMII_2500_FM1_DTSEC9,
85 SGMII_2500_FM1_DTSEC10,
86 SGMII_2500_FM2_DTSEC1,
87 SGMII_2500_FM2_DTSEC2,
88 SGMII_2500_FM2_DTSEC3,
89 SGMII_2500_FM2_DTSEC4,
90 SGMII_2500_FM2_DTSEC5,
91 SGMII_2500_FM2_DTSEC6,
92 SGMII_2500_FM2_DTSEC9,
93 SGMII_2500_FM2_DTSEC10,
Codrin Ciubotariuc2a61cd2015-01-12 14:08:31 +0200[diff] [blame]94 SGMII_SW1_MAC1,
95 SGMII_SW1_MAC2,
96 SGMII_SW1_MAC3,
97 SGMII_SW1_MAC4,
98 SGMII_SW1_MAC5,
99 SGMII_SW1_MAC6,
Codrin Ciubotariu7d33a872015-01-12 14:08:30 +0200[diff] [blame]100 SERDES_PRCTL_COUNT /* Keep this item the last one */
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]101};
102
103enum srds {
104 FSL_SRDS_1 = 0,
105 FSL_SRDS_2 = 1,
106 FSL_SRDS_3 = 2,
107 FSL_SRDS_4 = 3,
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]108};
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]109
Kumar Gala6ab40112010-04-20 10:20:33 -0500[diff] [blame]110int is_serdes_configured(enum srds_prtcl device);
Kumar Galaaf025062010-05-22 13:21:39 -0500[diff] [blame]111void fsl_serdes_init(void);
Valentin Longchamp935b4022013-10-18 11:47:23 +0200[diff] [blame]112const char *serdes_clock_to_string(u32 clock);
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]113
Emil Medve3d28c5c2010-08-31 22:57:36 -0500[diff] [blame]114#ifdef CONFIG_FSL_CORENET
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]115#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
116int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
Shaveta Leekha40f398a2013-07-02 14:42:07 +0530[diff] [blame]117enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]118#else
Emil Medve3d28c5c2010-08-31 22:57:36 -0500[diff] [blame]119int serdes_get_first_lane(enum srds_prtcl device);
York Sund1001e32012-10-08 07:44:15 +0000[diff] [blame]120#endif
Emil Medvedf8af0b2010-08-31 22:57:38 -0500[diff] [blame]121#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
122void serdes_reset_rx(enum srds_prtcl device);
123#endif
Emil Medve3d28c5c2010-08-31 22:57:36 -0500[diff] [blame]124#endif
125
Anton Vorontsov453316a2008-03-24 17:40:32 +0300[diff] [blame]126#endif /* __FSL_SERDES_H */