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Kumar Gala6ab40112010-04-20 10:20:33 -05001/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala6ab40112010-04-20 10:20:33 -05005 */
6
Anton Vorontsov453316a2008-03-24 17:40:32 +03007#ifndef __FSL_SERDES_H
8#define __FSL_SERDES_H
9
10#include <config.h>
11
Kumar Gala6ab40112010-04-20 10:20:33 -050012enum srds_prtcl {
13 NONE = 0,
14 PCIE1,
15 PCIE2,
16 PCIE3,
17 PCIE4,
18 SATA1,
19 SATA2,
20 SRIO1,
21 SRIO2,
Kumar Gala34a82582010-07-12 22:51:29 -050022 SGMII_FM1_DTSEC1,
23 SGMII_FM1_DTSEC2,
24 SGMII_FM1_DTSEC3,
25 SGMII_FM1_DTSEC4,
26 SGMII_FM1_DTSEC5,
York Sund1001e32012-10-08 07:44:15 +000027 SGMII_FM1_DTSEC6,
28 SGMII_FM1_DTSEC9,
29 SGMII_FM1_DTSEC10,
Kumar Gala34a82582010-07-12 22:51:29 -050030 SGMII_FM2_DTSEC1,
31 SGMII_FM2_DTSEC2,
32 SGMII_FM2_DTSEC3,
33 SGMII_FM2_DTSEC4,
Timur Tabi99abf7d2012-08-14 06:47:21 +000034 SGMII_FM2_DTSEC5,
York Sund1001e32012-10-08 07:44:15 +000035 SGMII_FM2_DTSEC6,
36 SGMII_FM2_DTSEC9,
37 SGMII_FM2_DTSEC10,
Kumar Gala6ab40112010-04-20 10:20:33 -050038 SGMII_TSEC1,
39 SGMII_TSEC2,
40 SGMII_TSEC3,
41 SGMII_TSEC4,
42 XAUI_FM1,
43 XAUI_FM2,
44 AURORA,
York Sund1001e32012-10-08 07:44:15 +000045 CPRI1,
46 CPRI2,
47 CPRI3,
48 CPRI4,
49 CPRI5,
50 CPRI6,
51 CPRI7,
52 CPRI8,
53 XAUI_FM1_MAC9,
54 XAUI_FM1_MAC10,
55 XAUI_FM2_MAC9,
56 XAUI_FM2_MAC10,
57 HIGIG_FM1_MAC9,
58 HIGIG_FM1_MAC10,
59 HIGIG_FM2_MAC9,
60 HIGIG_FM2_MAC10,
61 QSGMII_FM1_A, /* A indicates MACs 1-4 */
62 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
63 QSGMII_FM2_A,
64 QSGMII_FM2_B,
Shengzhou Liu82a55c12013-11-22 17:39:09 +080065 XFI_FM1_MAC1,
66 XFI_FM1_MAC2,
York Sund1001e32012-10-08 07:44:15 +000067 XFI_FM1_MAC9,
68 XFI_FM1_MAC10,
69 XFI_FM2_MAC9,
70 XFI_FM2_MAC10,
71 INTERLAKEN,
Prabhakar Kushwaha96bda022014-01-24 17:51:50 +053072 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
York Sun5f208d12013-03-25 07:40:06 +000073 QSGMII_SW1_B,
York Sund1001e32012-10-08 07:44:15 +000074};
75
76enum srds {
77 FSL_SRDS_1 = 0,
78 FSL_SRDS_2 = 1,
79 FSL_SRDS_3 = 2,
80 FSL_SRDS_4 = 3,
Kumar Gala6ab40112010-04-20 10:20:33 -050081};
Anton Vorontsov453316a2008-03-24 17:40:32 +030082
Kumar Gala6ab40112010-04-20 10:20:33 -050083int is_serdes_configured(enum srds_prtcl device);
Kumar Galaaf025062010-05-22 13:21:39 -050084void fsl_serdes_init(void);
Valentin Longchamp935b4022013-10-18 11:47:23 +020085const char *serdes_clock_to_string(u32 clock);
Anton Vorontsov453316a2008-03-24 17:40:32 +030086
Emil Medve3d28c5c2010-08-31 22:57:36 -050087#ifdef CONFIG_FSL_CORENET
York Sund1001e32012-10-08 07:44:15 +000088#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
89int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
Shaveta Leekha40f398a2013-07-02 14:42:07 +053090enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
York Sund1001e32012-10-08 07:44:15 +000091#else
Emil Medve3d28c5c2010-08-31 22:57:36 -050092int serdes_get_first_lane(enum srds_prtcl device);
York Sund1001e32012-10-08 07:44:15 +000093#endif
Emil Medvedf8af0b2010-08-31 22:57:38 -050094#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
95void serdes_reset_rx(enum srds_prtcl device);
96#endif
Emil Medve3d28c5c2010-08-31 22:57:36 -050097#endif
98
Anton Vorontsov453316a2008-03-24 17:40:32 +030099#endif /* __FSL_SERDES_H */