Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 1 | /* |
Kumar Gala | 561e710 | 2011-01-31 15:51:20 -0600 | [diff] [blame] | 2 | * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor. |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <pci.h> |
| 9 | #include <asm/processor.h> |
| 10 | #include <asm/immap_86xx.h> |
Kumar Gala | c851462 | 2009-04-02 13:22:48 -0500 | [diff] [blame] | 11 | #include <asm/fsl_pci.h> |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 12 | #include <asm/fsl_ddr_sdram.h> |
Kumar Gala | 5d27e02 | 2010-12-15 04:55:20 -0600 | [diff] [blame] | 13 | #include <asm/fsl_serdes.h> |
Haiying Wang | 3d98b85 | 2007-01-22 12:37:30 -0600 | [diff] [blame] | 14 | #include <asm/io.h> |
Jon Loeliger | ea9f739 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 15 | #include <libfdt.h> |
| 16 | #include <fdt_support.h> |
Ben Warren | 0b252f5 | 2008-08-31 21:41:08 -0700 | [diff] [blame] | 17 | #include <netdev.h> |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 18 | |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 19 | phys_size_t fixed_sdram(void); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 20 | |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 21 | int checkboard(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 22 | { |
Kumar Gala | 9af9c6b | 2009-07-15 13:45:00 -0500 | [diff] [blame] | 23 | u8 vboot; |
| 24 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
| 25 | |
| 26 | printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " |
| 27 | "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", |
| 28 | in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), |
| 29 | in_8(pixis_base + PIXIS_PVER)); |
| 30 | |
| 31 | vboot = in_8(pixis_base + PIXIS_VBOOT); |
| 32 | if (vboot & PIXIS_VBOOT_FMAP) |
| 33 | printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); |
| 34 | else |
| 35 | puts ("Promjet\n"); |
| 36 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 37 | return 0; |
| 38 | } |
| 39 | |
Becky Bruce | 9973e3c | 2008-06-09 16:03:40 -0500 | [diff] [blame] | 40 | phys_size_t |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 41 | initdram(int board_type) |
| 42 | { |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 43 | phys_size_t dram_size = 0; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 44 | |
| 45 | #if defined(CONFIG_SPD_EEPROM) |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 46 | dram_size = fsl_ddr_sdram(); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 47 | #else |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 48 | dram_size = fixed_sdram(); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 49 | #endif |
| 50 | |
Timur Tabi | 9ff32d8 | 2010-03-29 12:51:07 -0500 | [diff] [blame] | 51 | setup_ddr_bat(dram_size); |
| 52 | |
Wolfgang Denk | 21cd581 | 2011-07-25 10:13:53 +0200 | [diff] [blame] | 53 | debug(" DDR: "); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 54 | return dram_size; |
| 55 | } |
| 56 | |
| 57 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 58 | #if !defined(CONFIG_SPD_EEPROM) |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 59 | /* |
| 60 | * Fixed sdram init -- doesn't use serial presence detect. |
| 61 | */ |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 62 | phys_size_t |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 63 | fixed_sdram(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 64 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | #if !defined(CONFIG_SYS_RAMBOOT) |
| 66 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 67 | volatile ccsr_ddr_t *ddr = &immap->im_ddr1; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 68 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 70 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
| 71 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 72 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 73 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 74 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
Peter Tyser | e7ee23e | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 75 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
| 77 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 78 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; |
| 79 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; |
| 80 | ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; |
| 81 | ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 82 | |
| 83 | #if defined (CONFIG_DDR_ECC) |
| 84 | ddr->err_disable = 0x0000008D; |
| 85 | ddr->err_sbe = 0x00ff0000; |
| 86 | #endif |
| 87 | asm("sync;isync"); |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 88 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 89 | udelay(500); |
| 90 | |
| 91 | #if defined (CONFIG_DDR_ECC) |
| 92 | /* Enable ECC checking */ |
Peter Tyser | e7ee23e | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 93 | ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 94 | #else |
Peter Tyser | e7ee23e | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 95 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 97 | #endif |
| 98 | asm("sync; isync"); |
Jon Loeliger | cb5965f | 2006-05-31 12:44:44 -0500 | [diff] [blame] | 99 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 100 | udelay(500); |
| 101 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 103 | } |
| 104 | #endif /* !defined(CONFIG_SPD_EEPROM) */ |
| 105 | |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 106 | void pci_init_board(void) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 107 | { |
Kumar Gala | 64e55d5 | 2010-12-17 10:47:36 -0600 | [diff] [blame] | 108 | fsl_pcie_init_board(0); |
Peter Tyser | 9a268e4 | 2010-09-29 13:37:26 -0500 | [diff] [blame] | 109 | |
Kumar Gala | 46f3e38 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 110 | #ifdef CONFIG_PCIE1 |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 111 | /* |
| 112 | * Activate ULI1575 legacy chip by performing a fake |
| 113 | * memory access. Needed to make ULI RTC work. |
| 114 | */ |
Kumar Gala | 46f3e38 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 115 | in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT |
| 116 | + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); |
Kumar Gala | 46f3e38 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 117 | #endif /* CONFIG_PCIE1 */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 118 | } |
| 119 | |
Jon Loeliger | 13f5433 | 2008-02-18 14:01:56 -0600 | [diff] [blame] | 120 | |
Jon Loeliger | ea9f739 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 121 | #if defined(CONFIG_OF_BOARD_SETUP) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 122 | void |
| 123 | ft_board_setup(void *blob, bd_t *bd) |
| 124 | { |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 125 | int off; |
| 126 | u64 *tmp; |
| 127 | u32 *addrcells; |
| 128 | |
Jon Loeliger | 13f5433 | 2008-02-18 14:01:56 -0600 | [diff] [blame] | 129 | ft_cpu_setup(blob, bd); |
Jon Loeliger | ea9f739 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 130 | |
Kumar Gala | 6525d51 | 2010-07-08 22:37:44 -0500 | [diff] [blame] | 131 | FT_FSL_PCI_SETUP; |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 132 | |
| 133 | /* |
| 134 | * Warn if it looks like the device tree doesn't match u-boot. |
| 135 | * This is just an estimation, based on the location of CCSR, |
| 136 | * which is defined by the "reg" property in the soc node. |
| 137 | */ |
| 138 | off = fdt_path_offset(blob, "/soc8641"); |
| 139 | addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); |
| 140 | tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); |
| 141 | |
| 142 | if (tmp) { |
| 143 | u64 addr; |
Becky Bruce | 3f510db | 2008-11-10 19:45:35 -0600 | [diff] [blame] | 144 | if (addrcells && (*addrcells == 1)) |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 145 | addr = *(u32 *)tmp; |
Becky Bruce | 3f510db | 2008-11-10 19:45:35 -0600 | [diff] [blame] | 146 | else |
| 147 | addr = *tmp; |
Becky Bruce | d52082b | 2008-11-07 13:46:19 -0600 | [diff] [blame] | 148 | |
| 149 | if (addr != CONFIG_SYS_CCSRBAR_PHYS) |
| 150 | printf("WARNING: The CCSRBAR address in your .dts " |
| 151 | "does not match the address of the CCSR " |
| 152 | "in u-boot. This means your .dts might " |
| 153 | "be old.\n"); |
| 154 | } |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 155 | } |
| 156 | #endif |
| 157 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 158 | |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 159 | /* |
| 160 | * get_board_sys_clk |
| 161 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ |
| 162 | */ |
| 163 | |
Jon Loeliger | 80e955c | 2006-08-22 12:25:27 -0500 | [diff] [blame] | 164 | unsigned long |
| 165 | get_board_sys_clk(ulong dummy) |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 166 | { |
| 167 | u8 i, go_bit, rd_clks; |
| 168 | ulong val = 0; |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 169 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 170 | |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 171 | go_bit = in_8(pixis_base + PIXIS_VCTL); |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 172 | go_bit &= 0x01; |
| 173 | |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 174 | rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 175 | rd_clks &= 0x1C; |
| 176 | |
| 177 | /* |
| 178 | * Only if both go bit and the SCLK bit in VCFGEN0 are set |
| 179 | * should we be using the AUX register. Remember, we also set the |
| 180 | * GO bit to boot from the alternate bank on the on-board flash |
| 181 | */ |
| 182 | |
| 183 | if (go_bit) { |
| 184 | if (rd_clks == 0x1c) |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 185 | i = in_8(pixis_base + PIXIS_AUX); |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 186 | else |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 187 | i = in_8(pixis_base + PIXIS_SPD); |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 188 | } else { |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 189 | i = in_8(pixis_base + PIXIS_SPD); |
Haiying Wang | 239db37 | 2006-07-28 12:41:18 -0400 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | i &= 0x07; |
| 193 | |
| 194 | switch (i) { |
| 195 | case 0: |
| 196 | val = 33000000; |
| 197 | break; |
| 198 | case 1: |
| 199 | val = 40000000; |
| 200 | break; |
| 201 | case 2: |
| 202 | val = 50000000; |
| 203 | break; |
| 204 | case 3: |
| 205 | val = 66000000; |
| 206 | break; |
| 207 | case 4: |
| 208 | val = 83000000; |
| 209 | break; |
| 210 | case 5: |
| 211 | val = 100000000; |
| 212 | break; |
| 213 | case 6: |
| 214 | val = 134000000; |
| 215 | break; |
| 216 | case 7: |
| 217 | val = 166000000; |
| 218 | break; |
| 219 | } |
| 220 | |
| 221 | return val; |
| 222 | } |
Ben Warren | 0b252f5 | 2008-08-31 21:41:08 -0700 | [diff] [blame] | 223 | |
| 224 | int board_eth_init(bd_t *bis) |
| 225 | { |
| 226 | /* Initialize TSECs */ |
| 227 | cpu_eth_init(bis); |
| 228 | return pci_eth_init(bis); |
| 229 | } |
Peter Tyser | 4ef630d | 2009-02-05 11:25:25 -0600 | [diff] [blame] | 230 | |
| 231 | void board_reset(void) |
| 232 | { |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 233 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
| 234 | |
| 235 | out_8(pixis_base + PIXIS_RST, 0); |
Peter Tyser | 4ef630d | 2009-02-05 11:25:25 -0600 | [diff] [blame] | 236 | |
| 237 | while (1) |
| 238 | ; |
| 239 | } |